JPS6152504B2 - - Google Patents

Info

Publication number
JPS6152504B2
JPS6152504B2 JP58154833A JP15483383A JPS6152504B2 JP S6152504 B2 JPS6152504 B2 JP S6152504B2 JP 58154833 A JP58154833 A JP 58154833A JP 15483383 A JP15483383 A JP 15483383A JP S6152504 B2 JPS6152504 B2 JP S6152504B2
Authority
JP
Japan
Prior art keywords
memory
address
output
signals
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58154833A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5963084A (ja
Inventor
Mamoru Hinai
Chikahiko Izumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58154833A priority Critical patent/JPS5963084A/ja
Publication of JPS5963084A publication Critical patent/JPS5963084A/ja
Publication of JPS6152504B2 publication Critical patent/JPS6152504B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP58154833A 1983-08-26 1983-08-26 メモリ制御装置 Granted JPS5963084A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58154833A JPS5963084A (ja) 1983-08-26 1983-08-26 メモリ制御装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58154833A JPS5963084A (ja) 1983-08-26 1983-08-26 メモリ制御装置

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP959878A Division JPS54102930A (en) 1978-01-31 1978-01-31 Bipolar memory

Publications (2)

Publication Number Publication Date
JPS5963084A JPS5963084A (ja) 1984-04-10
JPS6152504B2 true JPS6152504B2 (cg-RX-API-DMAC7.html) 1986-11-13

Family

ID=15592873

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58154833A Granted JPS5963084A (ja) 1983-08-26 1983-08-26 メモリ制御装置

Country Status (1)

Country Link
JP (1) JPS5963084A (cg-RX-API-DMAC7.html)

Also Published As

Publication number Publication date
JPS5963084A (ja) 1984-04-10

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