JPS6152504B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a memory control device for an electronic computer that employs a virtual memory method and a buffer memory method.

[Background of the invention]

Recent large and medium-sized electronic computers generally use both the virtual memory method and the buffer memory method. The virtual memory method is a method that allows programs to code without being aware of the size of real memory.The programmer uses virtual addresses in virtual memory, which has an almost infinite memory capacity, instead of real addresses in real memory. is given. On the other hand, in the buffer memory method, a high-speed, small-capacity memory is placed between the central processing unit and the main memory to compensate for the gap with the main memory, which has a large capacity but is slow compared to the calculation speed. This is a method of configuring.

Virtual memory schemes require that virtual addresses be translated to real addresses prior to memory reference. Conversion of a virtual address to a real address is performed by referring to a conversion table in main memory prepared by the program, but if the slow main memory is referred to each time, the overhead of address conversion is large. Therefore, a high-speed address translation table (hereinafter referred to as
Translation Lookaside Buffer (TLB) is placed, and when the memory is referenced, the corresponding virtual address is
It checks whether the address exists in the address, and when it does exist (the probability of this is very high due to the locality of the program), the real address can be obtained quickly.

In the buffer memory method, buffer
Since memory is a copy of a portion of main memory, buffer memory is required to remember the correspondence.
Address array (BAA: Buffer Address
Array) is arranged. When the central processing unit initiates a memory reference at a virtual address, the TLB
It is checked whether the real address converted by BAA exists or not, and if it exists (the probability of this is very high due to the locality of the program), the corresponding data is read out from the buffer memory at high speed and sent to the central processing unit. sent to.

In the above explanation, the TLB and BAA are referenced serially, but in order to speed up processing, it is necessary to reference them in parallel. In this case, the BAA is referenced by the virtual address. To be more precise, the BAA is referenced in the real address part (intra-page relative address) within the virtual address. The data correspondence between main memory and buffer memory is called a block.
Since 2B or 64B is common,
The number of bits available for BAA reference is at most 6 to 7 bits.

FIG. 1 is a block diagram showing an example of a memory control device that refers to the TLB and BAA in parallel. A memory request request that occurs in the central processing unit stores a virtual address in register 1. With the page address above the virtual address
The corresponding entry in TLB2 is towed. In this example
TLB2 consists of 1 column x 2 rows, 2-1,
2-2 indicates each row. In other words, there are l sets of entries in each of the first row and the second row.
Each entry in rows 2-1 and 2-2 of TLB2 consists of a virtual address field (L field), a valid flag/bit field (V field), and a real address field (R field).
The contents of the L part and V part read from each row of TLB2 are stored in the corresponding virtual address comparison circuit 4-
1, 4-2, it is compared with the page address, which is the upper bit of the virtual address in register 1.

An in-page relative address below the virtual address.
BAA3 is in tow. BAA3 consists of m columns x n rows, and 3-1, 3-2, ...3-n are the first
The n-th row is shown. That is, each row has m sets of entries.
In the method of referencing TLB2 and BAA3 in parallel, it depends on the block size of buffer memory.
The number m of columns of BAA3 is determined. That is, if the page size is 4KB and the block size is 64B, m=64 columns. The number of rows n is a buffer.
Determined by memory capacity. Each entry in BAA3 consists of a real address field (R field) and a valid flag/bit field (V field). Real address comparison circuit 6
-1, 6-2, ..., 6-n are real addresses (page addresses) read from the R section of TLB2-1 that are input through the selection circuit 5, or stored directly in the register 1 by the central processing unit. The real address (page address) and the corresponding BAA3-
The contents read from the R section of 1, 3-2, . . . , 3-n are compared. The selection circuit 5 selects the contents of register 1 when the central processing unit directly stores a real address in the register, and selects the contents of TLB 2-1 when a virtual address is stored in register 1. Other real address comparison circuit 7-1, 7-
2,...,7-n are the real addresses read from the R section of TLB2-2 and the corresponding BAA3-1,
The real addresses read from the R section of 3-2, . . . , 3-n are compared. When the two inputs of each of the real address comparison circuits 6-1 to 6-n and 7-1 to 7n match, the output becomes "1".

Real address comparison circuits 6-1 to 6-n, 7-1 to
The comparison result by 7-n is sent to virtual address comparison circuit 4.
After being selected based on the results of -1 and 4-2, it is input to the encoder 8, and the encoded output is stored in the upper part of the register 9. The in-page relative address of register 1 is stored in the lower part of register 9. Thus, a buffer memory reference address corresponding to the virtual address or real address stored in register 1 is obtained in register 9. The data read out from the buffer memory by the address of register 9 is transferred to the central processing unit.

By the way, since the TLB2 and BAA3 require high speed as well as a certain amount of capacity, a conventional example of bipolar memory is shown in FIG.

In Figure 2, input pins A ₀ - _{A 2} and A ₃ - _{A 5}
The address signals applied to are X address decoder 10 and Y address degoder 1, respectively.
4, the memory cell 12 is activated via drivers 11 and 13. In this example, the memory cell 12 consists of 64 bits each consisting of 8 bits x 8 bits.
It has a bit configuration. One bit selected from the memory cell 12 is led to the output circuit 16 via the sense amplifier 15, and the output circuit 16 is connected to the input pin CS.
Output pin DO when (chip select) is enabled.
Outputs read data to (data out).
Write mode is entered when input pins CS (chip select) and WE (write enable) are enabled. In the write mode, the input pin DI (data in) is ANDed with CS and WE by the AND circuits 18 and 19 through the gate 17, and the output of these AND circuits 18 and 19 writes "1" to the output. Or the write “0” signal is valid,
A write instruction is given via the driver 13 to the bit of the memory cell 12 specified by addresses _A0 to _A5 .

When used as TLB or BAA mentioned above,
This type of bipolar memory is arranged in a matrix to achieve a desired word width and bit width.

Now, in recent years, electronic computers have developed ultra-high density LSIs,
Through improvements, larger scale and faster speeds began to be realized.
This trend is expected to continue in the future. In this way, many logic devices such as arithmetic units
While the logic section including bipolar memory is becoming faster and faster with LSI, the majority of the logic part is the gate for spreading the address to the bipolar memory and converging the data read from the bipolar memory, making it difficult to convert to LSI and taking advantage of the effect. There is a high possibility that this will become a critical path that limits the machine cycle of the electronic computer. Also, the main
There is also a tendency for memory capacity to increase, and accordingly, an increase in buffer memory capacity is also required. That is, an increase in the capacity of BAA is required. On the other hand, the integration of bipolar memory is progressing, and high-speed
4K bit memory is also becoming possible. However, regarding BAA, in the TLB and BAA parallel reference systems, the number of columns is only allowed to be 6 or 7 bits at most, as mentioned above, so bipolar
Higher integration of memory requires an increase in the number of bits. However, it is not possible to achieve large capacity BAA using conventional bipolar memory configured as shown in Figure 2.
configuring a bipolar memory is impractical because the number of package pins of the bipolar memory increases significantly.

By the way, if a 4K bit memory is configured with 64 words, it can accommodate 64 bits, but the required number of pins for both address lines and data lines reaches 140, and the package size of bipolar memory is limited to input/output. It is limited by the number of pins.

[Purpose of the invention]

The purpose of the present invention is to eliminate the above-mentioned conventional problems, and to reduce propagation delay and the number of input/output pins of the package by allocating memories of the same configuration to TLB and BAA. An object of the present invention is to provide a memory control device.

[Summary of the invention]

The present invention provides a memory control device including a TLB and a BAA, in which a memory with a built-in comparison circuit having the same configuration is arranged. The memory includes n memory sections, a circuit that selects and outputs the output data of each memory section according to a chip select signal, and compares the output data of the memory corresponding one-to-one to the memory section with an external signal. n comparison circuits are built-in. The memory allocated to the TLB makes only one chip select signal valid for one memory part, and the output data of one memory part and the external signal are compared. , all chip select signals for all memory sections are enabled, and each output from all memory sections is simultaneously compared with an external signal in each corresponding comparison circuit.

[Embodiments of the invention]

Next, one embodiment of the present invention will be described with reference to the drawings.

FIG. 3 shows a block diagram of a bipolar memory with a built-in comparator circuit used as a TLB and BAA memory as an embodiment of the present invention. In the figure, the numbers in parentheses represent the number of signals, but the number of signals varies depending on the degree of integration, and the present invention is not limited to this. 20-1 to 20-4
is a memory section, and the internal configuration of each may be the same as that of the conventional one. Each memory section 20-1, 20-
4 are chip select signals 24-1 and 2, respectively.
Address signal (terminal) 2 as a common signal with 4-4
5, the data in signal (terminal) 26 and write permission signal 27 are input, and as a result, the data in signal (terminal) 26 and write permission signal 27 are input.
Output signals 33-1 and 33-4. 23
is an output data selection circuit which outputs a set of data selected by the chip select signals 24-1 and 24-4 among the data out signals 33-1 and 33-4 to the output pin 32. 21-1, 21-4
is the comparison circuit A, and the memory sections 20-1 to 20-
Data out signal 33-1 read from 4
~33-4 and the compared signal 29 from the outside are compared, and when a mismatch between the two inputs is detected, "1" is output to the comparison outputs A30-1 to A30-4. Similarly, the comparison circuits B22-1 to 22-4 compare the data out signals 33-1 to 33-4 read from the memory units 20-1 to 20-4 with the compared signal 28 from the outside, Comparison detection power when a mismatch between two inputs is detected B31-1 to 31-
Output “1” to 4.

Operation of the Embodiment Each of the memory sections 20-1 to 20-4 and the output data selection circuit 23 are almost the same as those of a conventional bipolar memory, but in the present invention, the memory section is divided into a plurality of groups (in this example, there are four groups). The feature is that the address signal 25, data-in signal 26, and write permission signal 27 of each group are common. Each operation mode will be explained below.

(b) Read mode This mode is used when the memory is allocated to TLB. One of the chip select signals 24-1 to 24-4 and the address signal 25 are enabled, and the memory sections 20-1 and 20
-4 is activated and the read data signal 33-1~
Outputs 33-4. Data out signal 33
-1 to 33-4 are data sets input to the output data selection circuit 23 and for which the corresponding chip select signal 24 is valid, for example, when the chip select signal 24-1 is valid, the data out signal 33-
1 to the output pin 32.

(b) Write mode One of the chip select signals 24-1 to 24-4, the address signal 25, the data in signal 26, and the write permission signal 27 are enabled, and the chip select signal is selected. Data is transferred to the memory indicated by the address signal 25 of the memory section.
The contents of the IN signal 26 are written. When this bipolar memory is used as a BAA, each memory section 20-1, 20-2, 20-3, 20
-4 correspond to each row of BAA, and when a new address is registered, a specific row is selected according to a certain algorithm and then registration is performed, so the address signal, data in signal, write The enable signal can be shared, which has the effect of reducing the number of package pins.

(c) Comparison mode This mode is used when memory is allocated to BAA. In this mode,
All of the chip select signals 24-1 to 24-4 and the address signal 25 are enabled, and the data out signals 33-1 to 33-1 activate the memory sections 20-1 to 20-4 and output data out signals.
33-4 are comparison circuits A21-1 to A21-21, respectively.
-4 and comparison circuits B22-1 and 22-4. One input of the comparison circuits A21-1 to 21-4 receives the compared signal 29, and the comparison circuit B22-
The compared signal 28 is valid for one input of the signals 1 to 22-4. This bipolar memory is BAA
When used as
The first row real address part (R part) output of the TLB, the compared signal 28, corresponds to the second row real address part (R part) output of the TLB (see FIG. 1).

Comparing circuits 21 and 22 calculate the exclusive OR 7 of their respective inputs, and when there is a mismatch in even one bit among the input bits (28 bits in this example), the respective outputs 30-1 to 30-4, 31 are output.
-1 to 31-4 are set to "1". However, when a match is found, the outputs 30-1 to 30-4 are set to “1”.
Of course, the comparator circuits 21 and 22 may be configured as follows. In this mode, all chip select signals are enabled, so the contents of data output pin 32 are not guaranteed, but BAA
There is no problem when the read mode is used as a mode because it is not used in normal operation and does not overlap with the comparison mode. Read mode is only used as a maintenance function.

Note that each signal 24-1 to 24 in this embodiment
-4,25,26,27,28,29,30-
1 to 31-4 and 32 are respectively input and output on corresponding input/output pins provided on the package.

〔Effect of the invention〕

According to the present invention, addresses with the same configuration and built-in comparison circuit can be commonly used for TLB and BAA.
Extremely effective in manufacturing electronic computers. Also
In TLB and BAA, by mounting the memory section and comparison circuit section on the same memory package, it is possible to improve propagation delay, reduce the number of pins, and enable higher density.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a memory control device using TLB and BAA parallel reference methods, FIG. 2 is a block diagram showing the configuration of a conventional bipolar memory, and FIG. 3 is an example of a memory adopted in the present invention. 1 is a block diagram of a bipolar memory with a built-in comparison circuit showing an embodiment. FIG. 2...High-speed address translation table (TLB), 3
...Battle Address Array (BAA), 4...
...Virtual address comparison circuit, 6, 7...Real address comparison circuit, 20-1, 20-4...Memory section, 2
1-1 to 21-4, 22-1, 22-4... Comparison circuit, 23... Output data selection circuit, 28, 29
...compared signal.

Claims (1)

[Scope of Claims] 1. A high-speed address conversion table that stores translation pairs of virtual addresses and real addresses and converts virtual addresses to real addresses, and a buffer address array that stores addresses of data stored in buffer memory. A memory control device comprising n memory sections, a circuit that selects and outputs output data of each of the memory sections according to a chip select signal, and an output of the corresponding memory section that corresponds one to one with the memory sections. Built-in n comparison circuits that compare data and external signals, chip select signals are individually input to each memory section, and address signals, data-in signals, and write permission signals are commonly input. Memories of the same configuration configured to The output data of one memory section is compared with the external signal, and the memories arranged in the buffer address array enable all chip select signals for all memory sections. A memory control device characterized in that each output from all memory units is simultaneously compared with an external signal by each corresponding comparison circuit. 2. The memory includes n second comparison circuits corresponding one-to-one to each memory section, and the memory arranged in the high-speed address conversion table does not use the second comparison circuit, Claims characterized in that the memory arranged in the buffer address array is further configured such that each output from all the memory sections is simultaneously compared with an external signal by each second comparison circuit. 2. The memory control device according to item 1.