JPH0622000B2 - Microprocessor device - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to the field of address translation devices for memory management, especially in microprocessor devices.

[Prior art]

There are many well-known mechanisms for memory management. In some devices, large addresses (virtual addresses) are translated into smaller physical addresses. In other devices, smaller addresses are used to access large memory spaces, for example by using bank switching. The present invention is of the former category, namely:
It concerns a class where large virtual addresses are used to access limited physical memory.

It is also known to provide various protection mechanisms in memory management devices. For example, a user may be prevented from writing the operating system, or perhaps even reading the operating system to an external boat. As will be seen later, the present invention assigns "attributes" to data at two different levels,
It implements a protection mechanism as part of a wider control scheme.

The prior art that the inventor believes is closest to the present invention is disclosed in US Pat. No. 4,442,484. That US patent includes a commercially available microprocessor (Intel
(Intel) 286) discloses a memory management and protection mechanism. The microprocessor includes a segment station descriptor register containing a segment base address, limit information, and an attribute (eg, protect bit). Both the segment descriptor table and the segment descriptor register contain bits that define various control mechanisms such as priority level, type of protection, etc.

One problem with the Intel 286 is that segment offset
It is limited to 64K bytes. Intel 286
It requires contiguous locations in the physical memory for a segment, but maintaining it is not always easy. As will be seen later, one advantage of the device of the invention is that
The segment offset is as large as the physical address space. In addition, the device of the present invention is
It is compatible with the traditional segmentation mechanisms or functions found in the 286. Differences between the prior art device and its commercial implementation (Intel 286 microprocessor) disclosed in the above-mentioned US patents and the present invention, as well as other advantages of the present invention, will be apparent from the following description. .

[Outline of Invention]

In this specification, an improvement of a microprocessor device including a microprocessor and a data memory will be described. The microprocessor includes a segmentation mechanism or function for translating the virtual memory address into a second memory address (linear address) and for testing and controlling the attribute of the data memory segment. An improvement of the present invention includes a page cache memory in the microprocessor to translate the first field from a linear address for a hit or match condition. The data memory also stores page mapping data, especially page directories and page tables. If no hit occurs in the page cache memory, the first field accesses the page directory and page table.
The output from the page cache memory or page table is
Gives the physical base address for the page in memory. Another field of linear address provides an offset within the page.

The page mapping data in the page cache memory and the data memory stores signals representing the attribution of the data in a particular page. These attributions include read and write protection and indicate whether the page was previously written and other information. What is important is that page level protection provides a second level of control over the data that is distinct from the segment attributes of the data in the page.

〔Example〕

 Hereinafter, the present invention will be described in detail with reference to the drawings.

The preferred embodiment of the microprocessor device of the present invention includes a microprocessor 10 (FIG. 1). The microprocessor is fabricated on a single silicon substrate using a complementary metal monoxide-semiconductor (CMOS) process. Any of the many well-known CMOS methods can be used. The present invention can also be implemented in other technologies such as n-channel, bipolar, SOS, etc.

The memory management mechanism for certain conditions requires access to tables stored in main memory.
A random access memory (RAM) 13, which functions as the main memory for the microprocessor device, is shown in FIG. Normal RAM can be used, such as RAM with dynamic memory.

As shown in FIG. 1, the microprocessor 10 has a physical address of 32 bits, and the microprocessor itself is a 32-bit microprocessor. Other components commonly used in microprocessors, such as drivers, mathematical processors, etc., are not shown in FIG.

Summary The memory management of the present invention uses segmentation and paging. A segment is defined by a set of segment descriptor tables that is different from the page table used to describe the page translation. The two mechanisms are completely different and independent. Virtual addresses are translated into separate addresses in two stages using two different mapping mechanisms. A segmentation technique is used for the first stage and a paging technique is used for the second translation stage. The paging technique may not be used in order to perform the one-step translation only by the segmentation technique. This one-step translation is compatible with Intel 286.

The segmentation (first translation stage) translates a 48-bit virtual address into a 32-bit linear (intermediate) address. A 48-bit virtual address consists of a 16-bit segment selector and a 32-bit offset within this segment. The 16-bit segment selector is used to identify the segment and access the entry from the segment descriptor table. This segment descriptor entry contains the base address of the segment, the size of the segment (limit), and the various attributes of the segment. This translation step is 32
3 in virtual address to get bit linear address
2 Add segment base to bit offset. At the same time, the 32-bit offset in the virtual address is compared to the segment limit and the type of access is checked against the segment attribute. If the 32 bit offset is outside the segment limit or if the type of access is not allowed by the segment attribute, an error is generated and the addressing process is aborted.

Paging (the second translation stage) translates a 32-bit linear address into a 32-bit physical address using a 2-level paging table in the process described below.

The two stages are completely independent. This (large)
A segment can consist of several pages, or a page can consist of several (smaller) segments.

A segment can start at any boundary, and that segment can be any size,
And is not limited to starting at a page boundary, or having a length that is an exact multiple of a page. This allows a segment to describe separately protected areas of memory starting at any address and can be any size.

Segmentation can be used to combine several small segments, each with its own unique protection attribute and size, into a page. In this case,
Segmentation provides a protection attribute and pages provide a convenient way for physical memory to map groups of related units that must be protected separately.

Paging can be used to decompose very large segments into smaller units for physical memory management. This allows a single identifier (segment selector) and a single descriptor (segment descriptor) for separately protected units of memory, rather than requiring the use of a number of page descriptors. Given. Within a segment, paging provides an additional level of mapping that allows large segments to be mapped into separate pages in physical memory that do not require adjacency. In practice, larger segments can be mapped for paging, with only a few pages present in physical memory at a time and the rest of the segments being mapped to disk. Paging also supports the definition of substructures within a large segment, for example, supporting the writing of protection on some pages of the large segment while leaving other pages writable.

The segmentation provides a very comprehensive model that operates on "natural" units used by the program, ie, arbitrarily sized portions of linearly addressed memory. Paging provides a very convenient way to manage physical memory, the main and auxiliary storage of the system. The combination of these two methods in the present invention results in a very flexible and powerful protection model.

Overall Microprocessor Architecture In FIG. 1, the microprocessor includes a bus interface device 14. The bus interface device 14 allows transmission of a 32-bit address signal,
And a buffer for sending and receiving 32 bits of data. Inside the microprocessor, the bus interface device 14 communicates via an internal bus 19. The bus interface unit 14 includes a prefetch unit for fetching an instruction from the RAM 13 and a prefetch matrix for communicating with the instruction unit of the instruction decoder 16. The queued instructions are processed in an execution unit (arithmetic logic unit) 18 which includes a 3-bit register file. The execution unit 18 and the decoder 16 communicate with the internal bus 19.

The present invention mainly comprises the address translation device 20. The translator performs two functions, one associated with the segment descriptor register and one associated with the page descriptor cache memory. Most of this segment register is conventionally known,
This will be described in detail with reference to FIG. The page cache memory and the interaction between the page cache and the page table and page directory stored in the main memory 13 will be described with reference to FIGS. 3 to 7. They form the basis of the present invention.

Segmentation Mechanism The segmentation device 21 shown in FIG.
8 receives the virtual address and accesses the appropriate segmentation information from the register. The register contains the segment base address. This segment base address is coupled to page device 22 via line 23 along with the offset from the virtual address.

FIG. 2 shows a table access operation in the main memory when the segmentation register is loaded with mapping information for a new segment. The segment field becomes an index in the segment descriptor table in the main memory 13. The contents of the table include the base address and the attribute associated with the data in the segment. The base address and offset are compared in the comparator 27 with the segment limit. If it exceeds the limit, the output of the comparator gives an error (fault) signal. Adder 26, which is part of the microprocessor, combines the base and offset to provide the "physical" address on line 31. The address can be used as a physical address by the microprocessor or used by the paging device 22. This is done to provide compatibility with certain programs written for legacy microprocessors (Intel 286).
In the case of Intel 286, the physical address space is 24 bits.

A segment attribute containing details about the descriptors employed, such as various priority levels, is described in US Pat.
It is described in No. 4,442,484.

That the segmentation mechanism is known in the prior art is shown on the left side of the dashed line 28 in FIG.

The block 30 of the page field mapping including the page device of FIG. 1 and the interaction between the page directory and the page table stored in the main memory and the page field mapping are shown in FIGS. It is shown.

In the embodiment described here, the segmentation mechanism uses a shadow register, but the segmentation mechanism can also be implemented by a cache memory, as is done by the paging mechanism.

Page Descriptor Cache Memory In FIG. 3, the page descriptor cache memory of page device 22 of FIG. 1 is shown within dashed line 22a.
This cache memory consists of two arrays, an associative storage memory (content addressable memory or CAM) 34 and a page data (base) memory 35.
With. Both memories are composed of static memory cells. The structure of the memories 34 and 35 will be described with reference to FIG. The particular circuitry used in CAM 34 and its unique masking features will be described with reference to FIGS.

The linear address from the segment device 21 is coupled to the page device 22 of FIG. As shown in FIG. 3, this linear address has two fields, a page information field (20 bits) and a displacement field (12 bits). There is also a 4-bit page attribution field composed of microcode. The 20-bit page information field is compared to the CAM34 tags. Furthermore,
4 Attribut Bits ("dirty",
"Valid,""U / S," and "W / R") must also be matched to the attribute bits in the CAM before the hit occurs. (As explained below, there is an exception to this when "masking" is used.) For hit states, memory 35 provides 20 bit base words. The base word is combined into a 12-bit displacement field of linear address, as represented by adder 36 in FIG. Based on the physical address obtained as a result, selection from the 4 Kbyte page field in the main memory 13 is performed.

Page Addressing for No Hit State A page directory 13a and a page table 13b are stored in the main memory 13 (see FIG. 4). The base address for the page directory is given by the microprocessor. The base address is shown as page direct rebase 38 in FIG. Ten bits of page information field are used as an index (after being multiplied by 4) in the page directory, as shown by adder 40 in FIG. The page directory gives 32 bit words. 20 bits of this word
Used as a base for page tables. The other 10 bits of page information field are also used as indexes (after being multiplied by 4) in the page table, as shown by adder 41 in FIG. Page table 3
Give 2 bit words. The 20 bits of that word are page-based for physical addresses. This page base address is combined with the 12 bit displacement field in adder 42 to form a 32 bit physical address.

Five bits from the 12-bit field in the page directory and page table are used for attribution, especially for "Dirty", "Access Received", "U / S", "R / W" and "Present". They will be described later in detail with reference to FIG. The remaining bits in this feed are unassigned.

The stored attributes from the page directory and the page table are coupled to the control logic circuit 75, along with 4 bits of attribute information associated with the linear address. Portions of this logic circuit are shown in later figures. It will be described with reference to those figures.

Page directory attribution page 5 shows page directory words, page words,
The CAM word and are shown again. Page Direct 4
The protection / control attribute assigned to the bit is shown in brackets 43. The same four atelier views with one additional atelier view were used for page wording and they are shown in brackets 44. The four attributes used for the CAM word are shown in brackets 45.

Attributes are used for the following purposes:

1. "Dirty" ... This bit indicates whether the page has been written. When a page is written, its bit can be changed. This bit is used, for example, to inform the operating system that the entire page is not "clean". This bit is stored in the page table and CAM (not the page directory). When a page is written, the processor sets the bit in the page table.

2. "ACCESSED" ... This bit is stored only in the page directory and page table (not in the CAM) and is used to indicate that the page has been accessed. When a page is accessed, its bit is modified in memory by the processor. Unlike the dirty bit, the bit indicates whether a page has been accessed for writing or reading.

3. "U / S" ... The state of this bit is that the content of the page is accessible to the user and the supervisor (binary "1") or only to the supervisor (2
"0").

4. "R / W" ... This write / read protection bit must be a binary "1" in order for the page to be written by a user level program.

5. "Present" ... This bit in the page table indicates whether the associated page exists in physical memory. This bit in the page directory indicates whether the associated page table resides in physical memory.

6. "VALID" ... This bit, which is stored only in the CAM, is used to indicate whether or not the contents of the CAM are valid. This bit is set to the first state at initialization and then changed when a valid CAM word is loaded.

Five bits from the page directory and page table are coupled to the control logic circuit 75 to provide the appropriate error signal within the microprocessor.

The user / supervisor (U / S) bits from the page directory and the page table are ANDed as shown by gate 46 and stored in CAM 34 of FIG.
Give W bit. Similarly, the read / write protection (R / W) bits from the page directory and the page table are ANDed by the gate 47 and stored in the CAM.
/ R Give a bit. CA is the dirty bit from the page list
Stored in M. The gates are part of the control logic circuit 75 shown in FIG.

Attributions stored in the CAM are tested "automatically". The reason is that those attributes are treated as part of the address and are
This is because the bit can match. For example, if the linear address indicates that a "user" write cycle should occur in the page at R / W = 0, then an error condition will result even if a valid page base is stored in the CAM.

Allow the "worst case" to be stored in the cache memory by ANDing the U / S bits from the page directory and page table. Similarly, the R / W AND operation gives the worst case to the cache memory.

Structure of Page Descriptor Cache Memory CAM 34 is composed of 8 sets, each set containing 4 words, as shown in FIG. 21 bits (address 17, attribute 4) are used to find the match in this array. 4 stored in each set
Four comparator lines from the word are connected to the detector. For example, the comparator lines for the four words of set 1 are connected to the detector 53. Similarly, comparator lines for each of the four words in sets 2-8 are connected to the detector. The detector examines the comparator line to determine which word in the set matches the input (21 bits) of the CAM array. Each detector contains a "hardwired" logic. 20 by the logic connected to the detector
Depending on the status of 3 bits from the bit information field,
Allows selection of one of the detectors. (Note that the other 17 bits of this bit page information field are coupled to the CAM array.)
Eight detectors are assumed to be used in FIG. In the described embodiment, only one detector is used, and only three detectors are used to select a set of four lines for coupling to the detector. The detector itself is shown in FIG.

The data storage portion of the cache memory is the array 35a-35.
It is organized into four arrays, shown as d. CAM
Is divided into data words corresponding to each set of
Stored in each array of one array. For example, the data word (base address) selected by the hit with word 1 of set 1 is in array 35a and the data word (base address) selected by the hit with word 2 of set 1
Are in array 35b, and so on. The three bits used to select the detector are also used to select the words in each array. Therefore, at the same time, words are selected from each of the four arrays. The final selection of words from the array is done via the multiplexer. This multiplexer is controlled by four comparator lines in the detector.

When the cache memory is accessed, the relatively slow process, the matching process, is started using 21 bits. The other three bits can immediately select a set of four lines and the detector is made to detect a potential drop on the comparator line. (As will be explained later, all comparator (row) lines are precharged, selected (hits) lines remain charged, and unselected lines are discharged.) 4 words from set are array 35
Accessed within a ~ 35d. When a match occurs, the word in that set can be identified by the detector and its information field sent to a multiplexer 55 to allow the selection of a data word. With this configuration, the access time of the cache memory is shortened.

Associative Memory (CAM) A 21 bit coupled to a CAM array is again shown in FIG. Seventeen of the twenty-one bits are coupled to the complementary generator and override circuit 56, and the remaining four bits, the attribute bits, are VUDW logic circuit 57.
Be combined with. The three bits associated with the detector selection described with reference to FIG. 6 are not shown in FIG.

The circuit 56 produces a true signal for each address signal and a complementary signal to that true signal and couples those signals to parallel lines, such as lines 59 and 60 in the CAM array. Similarly, VUDW logic 57 generates the true signal for the attribute bit and its complement, and couples those signals to parallel lines in the CAM array. Lines 59 and 60 are made exactly as lids for each true bit line and each complementary bit line (ie 2
A pair of bits and Each of the 32 rows in the CAM array has a pair of parallel row lines, such as lines 68 and 70. Ordinary static memory cells, such as cell 67, are Connected between (columns) and associated with row line pairs.
In the described embodiment, the memory cell comprises a conventional flip-flop static memory cell using p-channel transistors. When data is written to the array, one of each row line pair (line 70) causes the memory cell to be a bit line and a line. Allow this join. If not, the contents of the memory cell are compared with the data on the column line and the result of the comparison is coupled to the hit line 68. The comparison is performed by a comparator associated with each cell. The comparator is
n channel transistors 61 to 64. Each transistor pair of the comparator, for example transistors 61, 6
2 is coupled between one side of the memory cell and the opposite bit line.

Assume that the data is stored in memory cell 67 and the junction of the cell closest to bit line 59 is high. CAM
When the contents of is examined, the hit line 68 is first precharged through transistor 69. Then the signal coupled to the CAM is applied to the column line. First, assume that line 59 is high. Transistor 62 does not conduct because line 60 is low. Since the side of the cell to which the transistor 63 is connected is low level, the transistor 63 does not become conductive. In such a condition, line 68 is not discharged, indicating that a match has occurred in the cell. The hit line performs the AND operation of the comparisons that occur along the rows. If no match occurs,
One or more comparators discharge the hit line.

During precharge, circuits 56 and 57 generate an override signal to drive all column lines (bits and Both sides) lower the level. This prevents discharge from the hit line by the comparator before the comparison begins.

It should be noted that the comparator looks at the "binary 1" state and actually ignores the "binary 0" state. That is, for example, the gate of transistor 64 is high (line 59).
Is high), transistors 63 and 64 control the comparison. Similarly, When 60 is high, transistors 61 and 62
Controls the comparison. This feature of the comparator allows cells to be ignored. Therefore, if a word is bound to CAM, the bit and A bit can be masked from the matching process by making the level low. This makes the contents of the cell appear to match the state on the column line. This feature is used by VUDW logic 57.

The microcode signal coupled to the logic circuit 57 is
Bits for selected bits of Attribut Bits and To a low level as a function of the microcode bit.
As a result, the attribute associated with that bit is ignored. This action is used, for example, to ignore U / S bits in supervision mode. That is, the supervisory mode can access the user data. Similarly, read / write bits can be ignored at the time of reading or during execution of the supervisory mode. The data bit can be ignored when reading. (This feature is not used for valid bits.) When attribute bits are stored in main memory, they can be accessed and examined, and access operations can be performed, for example, by U / S. Logic circuits are used to control based on the 1-state or 0-state of the bit. However, no separate logic is used for the cache memory. In fact, the bit and A low level allows extra matching logic by allowing the match (or blocking errors) even if the bit pattern of the attribute bit is not matched.

As shown in FIG. 8, the detector from FIG.
Includes multiple NOR gates such as 1,82,83,84. Three hit lines from the selected set of CAM lines are coupled to gate 81. The lines are shown as lines A, B, C. Various combinations of those lines are connected to each other NOR gate. For example, NOR gate 84 receives hit lines D, A, B. The output terminal of each NOR gate is NAND
Input to a NAND gate, such as gate 86. There is one
One hit number is one input to each NAND gate. The hit line is one line (of the four hit lines A, B, C, D) that is not the input to the NOR gate. That line is also the bit line from the set entry to select. For example, gate 86 must select the set associated with hit line D. For example, in the case of NOR gate 81, hit line D is coupled to NAND gate 86. Similarly, for NAND gate 90, hit line C is in addition to the output of gate 84 to this gate. Is an input. To prevent the output of this logic from being enabled for writing, the enable read signal is also set to its NAND.
Coupled to the gate. The output, such as line 87 of the NAND gate, is used to control the multiplexer 55 of FIG. In effect, the signal from the NAND, such as the signal on line 87, controls the multiplexer via the p-channel transistor. For the sake of explanation, an additional inverter 88 to which the output line 89 is connected is shown.

The advantage of this detector is that it allows the multiplexer 55 to use a precharge line. Alternatively, a static device can be used, but it requires considerably more power. With the configuration shown in FIG. 8, the output from the inverter maintains the same state until the potential of one hit line decreases. When the potential drop occurs, the potential on only one output line drops, allowing the multiplexer to select the correct word.

We have described a unique address translator that uses two levels of cache memory for segmentation and for paging. There is independent data attribution control (eg protection) for each level.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall architecture of a microprocessor that is currently implementing the present invention, and FIG. 2 is a block diagram showing the segmentation mechanism implemented in the microprocessor of FIG. FIG. 3 is a block diagram showing page field mapping for a hit or a match in the page cache memory.
Figure is a block diagram showing page field mapping for no hit or no match in page cache memory of Figure 3 such that the page directory and page tables in main memory are used, and Figure 5 is a page. Diagram used to show attributes stored in the page directory and page table of the cache memory, 6th
The figure is a block diagram showing the configuration of the associative description memory and data storage included in the page cache memory.
FIG. 8 is an electric circuit diagram of a part of the associative memory of FIG. 6, FIG.
The figure is an electrical schematic of the logic circuitry associated with the detector of FIG. 13 ... Main storage device, 14 ... Bus interface device, 16 ... Decoder, 18 ... Execution device, 20 ... Address translation device, 21 ... Segment device, 22 ... Page device, 27 ... Comparison Container, 30 ... Page field mapping block, 34 ... Associative memory (CAM),
35 ... page data memory, 38 ... page direct rebase, 53 ... detector, 55 ... multiplexer, 57 ... VUDW logic circuit, 67 ... memory cell, 75 ...
... control logic circuit.

 ─────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-61-84755 (JP, A) JP-B-55-40950 (JP, B2)

Claims (4)

[Claims] 1. A microprocessor device comprising: (a) address register means for providing a virtual memory address; (b) a bus interface device for providing an interface for address terminals and data terminals of the microprocessor device; c) An address translation device that receives a virtual memory address from the address register means, and (i) at least one segment descriptor register for storing a segment base address and a variable length limit, and at least one of the virtual memory addresses. Part
A comparator for generating an error signal when the limit is exceeded, the segment base address being added to a part of the virtual address, and a page information field and an offset being added. A segment device for generating linear addresses; (ii) a page cache storing a plurality of page entries representing memory addresses of fixed size pages and tags for those page entries; Means for signaling a match condition in comparison with the page information field of a linear address, whereby in the match condition a page entry output corresponding to one of the page entries is generated; (iii) match If no status is indicated, at least the page base address and the page information field are A page that generates a page table address from a part of the page interface address and sends the page table address to the bus interface device, and receives from the bus interface device a page table entry corresponding to one of the page entries corresponding to the page table address. An address translation device having table address means, (d) (i) the linear address from the segment device,
Or (ii) a page entry output from the page cache or a combination of the page table entry from the page table address means and the offset of the linear address, which is coupled to receive the bus interface device. A microprocessor device having an address generator that generates a physical address. 2. The apparatus according to claim 1, wherein an external memory that stores the page table entry and is accessed by a physical address received through the address terminal is combined. And a microprocessor device. 3. A memory management device comprising: (a) a microprocessor device for performing memory management using mutually independent segmentation and paging in a virtual memory device having a virtual address space divided into segments of arbitrary length. And a microprocessor device having a plurality of functional parts including an internal memory and having a plurality of terminals for address and data, and (b) addressing by the plurality of terminals for address and data An external memory; (i) an internal bus for transmitting information between the plurality of functional units; (ii) the internal bus; and the plurality of terminals for address and data. A bus interface device for sending information between, and (iii) pairing with a location in the virtual address space. An address register for giving a virtual memory address having only information not related to the paging function in the memory management device as a virtual memory address being set, and (iv) the virtual memory from the address register. An address translator that receives an address, (iv-A) at least one segment descriptor register that stores a segment descriptor, and a reference as to whether that segment descriptor is paged or not for a segment And at least one segment descriptor register, which provides information describing the segment and includes at least a segment base address and a segment length, and comparing at least a portion of the virtual address with the segment length, Part of the above Segume When it exceeds the door length, to generate an error signal, in combination with the portion of the virtual address and the segment base address,
A segment device having a first circuit for generating a linear address having a page information field and a page displacement field; and (iv-B) a page device which operates independently of the segment device and receives the linear address. (1) a page cache storing a plurality of page entries and tags for these page entries, which represent memory addresses of fixed length pages, and (2) comparing the page information field of the linear address with the tags. If the page information field matches one of the tags, a second circuit for generating a page entry output corresponding to one of the page entries, and (3) depending on the second circuit If the page info field does not match any of the tags,
A page table address is generated from one base address of a fixed length page and at least part of the page information field of the linear address, and the page table address is sent to the internal bus, thus the internal A page device having a page table address circuit for receiving a page table entry from the internal bus according to the page table address sent to the bus; and (iv-C) (i) receiving the linear address and receiving the linear address Or (ii) receives the page displacement field and the page entry output from the page cache or the page table entry from the page table address circuit, and outputs a page entry output or a page table entry Received from
Combining with the page displacement field to generate a physical address and sending the physical address to the plurality of terminals for address and data via the internal bus,
And an address translation circuit having an address generation circuit; the external memory stores a plurality of segment descriptors for sending to the segment descriptor register. 4. A method for memory management in a computer device that performs both segmentation and paging, comprising: (a) virtual information including address information and offset into a segment descriptor table as input for segmentation processing. Providing an address and a segment descriptor table addressable by the address information to the segment descriptor table; (b) providing a linear address as an output of the segmentation; and (c) the linear address: i) used as a physical address for an address to main memory, or (ii) based on a set of inputs containing the linear address and a set of inputs other than the inputs for the segmentation process, Entry into the paging process that generates the physical address A method of performing memory management, including the step of using the physical address as a force, and (d) the step of using the physical address to access the main storage device via a system bus.