GB1457423A - Associative memories - Google Patents

Abstract

1457423 Associative memories NATIONAL RESEARCH DEVELOPMENT CORP 2 April 1974 [17 Jan 1973] 2476/73 Heading G4C [Also in Divisions H3-H5] An associative memory comprises memory cells 10, Fig. 1, arranged in m rows each storing a single word and in n columns, each row having all its memory cells 10 connected by a line 27 and being accessed via a line 30, whereas each column is accessed via lines 25, 26, a control cell 12 being provided for each row to operatively connect the line 27 to at least one of a reference potential +V from lines 31-33, Fig. 2, to a potential - V, or to the line 30, to perform read, write, match and standby (refresh) operations for each memory cell. Each memory cell 10, Fig. 2, comprises cross-coupled MOS transistors 21, 24 formed on a substrate maintained at potential +V, the gate capacitance of one or other of transistors 21, 24 being charged from a respective one of lines 26, 25 via a respective one of MOS transistors 23, 22 to store binary 1 or 0 in the cell (binary 1 being stored by charging transistor 21). Further MOS transistors 28, 29 enable read-out of the stored information by means of detected currents between the respective lines 25, 26 and the line 30, or the "matching" of a stored binary 1 or 0 by means of the detected current in line 30, when suitable potentials are applied to the memory cell 10 from the control cell 12 on the lines 27, 30. Each control cell 12 receives reference potentials ŒV on the lines 31-33 (line 33 always carrying the inverse potential to line 32), and comprises MOS transistors 34-36 connecting the lines 31-33 to the lines 27, 30. In the following, the potentials on lines 25, 26, 27 and 30 are assumed to be zero unless otherwise stated, and the value of any non-zero potential is indicated in a bracket following the line number. Writing=27 (between - V and 0); 25(+V) for write 1 and 26(+V) for write 0. Masked write=27(nearly +V), 30(+V), 25 and 26 indifferent (this leaves memory cell unaffected by write operation). Reading = 27(+V), 30(+V). Masked read = 27(+V) only (for masking read-out of all other rows to a row being read-out). Match 1= 25(+V), 27(+V); match 0 : 26(+V), 27(+V). Masked match=25(0), 26(0), 27(+V) (resulting in cell being prevented from contributing a mismatch current to line 30). In the embodiment of Fig. 4 (not shown), each memory cell (40) comprises two MOS transistors (44), (46) and is accessed by a single column line (48) and row lines (50), (52). Information is stored in the cell (40) by charging the gate capacitance of transistor (44) via transistor (46). The operations permitted on the cell (40) are similar to those for the cell 10 of Figs. 1-2 except that only one "match" operation, e.g. "match 1", can be performed, "match 0" being forbidden. In this embodiment of Fig. 5 (not shown), a pair of memory cells each similar to the cell (40) of Fig. 4 are combined to form a single memory cell (70), the cell (70) being accessed by a pair of column lines (72) and (74) in order to permit both "matchl" and "match 0" operations.