JPS6149862B2 - - Google Patents

Info

Publication number
JPS6149862B2
JPS6149862B2 JP56023294A JP2329481A JPS6149862B2 JP S6149862 B2 JPS6149862 B2 JP S6149862B2 JP 56023294 A JP56023294 A JP 56023294A JP 2329481 A JP2329481 A JP 2329481A JP S6149862 B2 JPS6149862 B2 JP S6149862B2
Authority
JP
Japan
Prior art keywords
address
memory
circuit
written
read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56023294A
Other languages
English (en)
Japanese (ja)
Other versions
JPS57138238A (en
Inventor
Isao Naganuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Telecom Networks Ltd
Original Assignee
Fujitsu Telecom Networks Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Telecom Networks Ltd filed Critical Fujitsu Telecom Networks Ltd
Priority to JP56023294A priority Critical patent/JPS57138238A/ja
Publication of JPS57138238A publication Critical patent/JPS57138238A/ja
Publication of JPS6149862B2 publication Critical patent/JPS6149862B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/04Speed or phase control by synchronisation signals
    • H04L7/041Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/042Detectors therefor, e.g. correlators, state machines

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP56023294A 1981-02-19 1981-02-19 Synchronizing pattern generating circuit Granted JPS57138238A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56023294A JPS57138238A (en) 1981-02-19 1981-02-19 Synchronizing pattern generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56023294A JPS57138238A (en) 1981-02-19 1981-02-19 Synchronizing pattern generating circuit

Publications (2)

Publication Number Publication Date
JPS57138238A JPS57138238A (en) 1982-08-26
JPS6149862B2 true JPS6149862B2 (enrdf_load_stackoverflow) 1986-10-31

Family

ID=12106583

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56023294A Granted JPS57138238A (en) 1981-02-19 1981-02-19 Synchronizing pattern generating circuit

Country Status (1)

Country Link
JP (1) JPS57138238A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60224342A (ja) * 1984-04-23 1985-11-08 Nec Corp フレ−ム同期回路

Also Published As

Publication number Publication date
JPS57138238A (en) 1982-08-26

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