JPS6149444A - Mounting method of semiconductor element - Google Patents

Mounting method of semiconductor element

Info

Publication number
JPS6149444A
JPS6149444A JP59171076A JP17107684A JPS6149444A JP S6149444 A JPS6149444 A JP S6149444A JP 59171076 A JP59171076 A JP 59171076A JP 17107684 A JP17107684 A JP 17107684A JP S6149444 A JPS6149444 A JP S6149444A
Authority
JP
Japan
Prior art keywords
semiconductor element
substrate
circuit board
heat
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59171076A
Other languages
Japanese (ja)
Other versions
JPH0317221B2 (en
Inventor
Kenji Watanabe
謙二 渡辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP59171076A priority Critical patent/JPS6149444A/en
Publication of JPS6149444A publication Critical patent/JPS6149444A/en
Publication of JPH0317221B2 publication Critical patent/JPH0317221B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32153—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/32175—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
    • H01L2224/32188—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic the layer connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To reduce man-hours on assembly, and to extract performance original to an element by fixing a circuit substrate, to which a through-hole is bored, onto a heat-dissipating body and bonding and fastening the semiconductor element onto the surface of the heat-dissipating body exposed on the bottom of the through-hole. CONSTITUTION:A through-hole 3 is bored to a circuit substrate 1 on which a bonding circuit 2 for a conductive film is formed, and the substrate 1 is bonded with a heat-dissipating body 4. A semiconductor element 5 is bonded with the surface of the heat-dissipating body 4 exposed on the bottom of the through-hole 3 in the substrate 1, and the height of the element 5 and the height of the substrate 1 are brought to approximately the same size. Consequently, the substrate 1 need not be divided, and may be used in only one, thus attaining the reduction of man-hours on assembly. The element 5 can be connected to the conductive film in the substrate 1 and the heat-dissipating body at the shortest distance from an upper-surface electrode for the element 5, thus sufficiently extracting performance original to the element 5.

Description

【発明の詳細な説明】 イ、産業上の利用分野 本発明は、例えば、ＧａＡｓＦＥＴなどのような、高周
波用半導体素子を、放熱体をもつ回路基板に実装する方
法に関する。DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a method for mounting a high frequency semiconductor element, such as a GaAsFET, on a circuit board having a heat sink.

口、従来の技術 従来、高周波用混成集積回路において、回路基板に半導
体素子を実装する場合は、第３図（ａ）の平面図および
同図（ｂ）の断面図に示すように、アルミナ、石英、サ
ノアイヤなどの絶縁体の上に導電膜回路２が形成された
回路基板２１を、銅、コバー。BACKGROUND OF THE INVENTION Conventionally, in a high-frequency hybrid integrated circuit, when semiconductor elements are mounted on a circuit board, alumina, A circuit board 21 on which a conductive film circuit 2 is formed on an insulator such as quartz or sanoia is made of copper or copper.

鉄などの放熱体４の上に接着し、かつ、スルーホール１
３を通して基板面の接地導電＠１２と放熱体４とを接続
し、回路基板２１上に直接半導体素子５を固着していた
。また、他の例としては、第４図（ａ）の平面図、同図
（ｂ）の断面図に示すように、中間に半導体素子を固着
するための突起台８を有する放熱体１４の上面に、突起
台８を間にはさんんで両側に、上面に導電膜結合回路２
が形成された２枚の回路基板３１．３１を接着し、突起
台８の上に半導体素子５を接着固定する方法とがあった
。Glue on top of heat sink 4 such as iron, and through hole 1
The ground conductor @ 12 on the substrate surface and the heat sink 4 were connected through the circuit board 3, and the semiconductor element 5 was directly fixed onto the circuit board 21. In addition, as another example, as shown in the plan view of FIG. 4(a) and the cross-sectional view of FIG. A conductive film coupling circuit 2 is placed on the upper surface on both sides with the protruding base 8 in between.
There is a method in which two circuit boards 31 and 31 on which are formed are bonded together, and the semiconductor element 5 is bonded and fixed onto the protruding base 8.

しかし、前者の回路基板に直接半導体素子を接着する方
法では、半導体素子表面の電喚から、回路基板上の結合
回路部までの距離や接地面までの距離が長くなるため、
高周波動作における半導体素子本来の特性を引出すこと
が困難であった。また、後者の、回路基板を２枚に分離
し、その間の放熱体上に半導体素子を接着する方法は、
放熱体に接着する部品点数が増加し、それによる工数増
加も加わり、歩留り低下および価格上昇をもたらすとい
うことになる。However, in the former method of bonding the semiconductor element directly to the circuit board, the distance from the electric current on the surface of the semiconductor element to the coupling circuit section on the circuit board and the distance to the ground plane becomes long.
It has been difficult to bring out the inherent characteristics of semiconductor devices in high-frequency operation. The latter method involves separating the circuit board into two pieces and bonding the semiconductor element onto the heat sink between them.
The number of parts to be bonded to the heat sink increases, which also increases the number of man-hours, resulting in lower yields and higher prices.

ハ０発明が解決しようとする問題点 上述のように、従来の実装方法では、性能をよくしよう
とすれば、高価格になるという点に問題があり、これに
対し、本発明では高性能低価格の実装方法を得ることが
課題となる。Problems to be Solved by the Invention As mentioned above, with the conventional mounting method, if you try to improve the performance, there is a problem in that it becomes expensive. The challenge is to figure out how to implement pricing.

二８問題点を解決するだめの技術手段 上記問題点に対し、本発明では、スルーホールのあけら
れた回路基板を放熱体上に固着し、前記スルーホール底
部に露出する前記放熱体面に直接または介在物を介して
半導体素子を接着固定する。Technical Means for Solving the 28 Problems In order to solve the above problems, in the present invention, a circuit board with through holes is fixed on a heat sink, and the circuit board with through holes is directly attached to the heat sink surface exposed at the bottom of the through holes. The semiconductor element is adhesively fixed via the inclusion.

°ホ、実施例 つぎに本発明を実施例により説明する。第１図（ａ）は
本発明の一実施例を説明するための平面図、同図（ｂ）
は同図（ａ）のＡ−Ａ断面図である。第１図（ａ）。E. Examples Next, the present invention will be explained by examples. FIG. 1(a) is a plan view for explaining one embodiment of the present invention, and FIG. 1(b) is a plan view for explaining one embodiment of the present invention.
is a sectional view taken along line A-A in FIG. Figure 1(a).

（ｂ）において、導電膜の結合回路２が形成された回路
基板１にはスルーホール３があけられており、回路基板
１は放熱体４に接着されている。しかして、回路基板１
のスルーホール３の底部に露出する放熱体面には、半導
体素子５を接着し、半導体素子５の高さと、回路基板１
の厚さはほぼ同じ寸法であるので、半導体素子５の電極
と回路基板上の結合回路２とはほぼ水平に短い導線６に
よシ接続される。In (b), a through hole 3 is made in a circuit board 1 on which a conductive film coupling circuit 2 is formed, and the circuit board 1 is bonded to a heat sink 4. However, circuit board 1
The semiconductor element 5 is adhered to the heat sink surface exposed at the bottom of the through hole 3, and the height of the semiconductor element 5 and the circuit board 1 are
have substantially the same thickness, the electrodes of the semiconductor element 5 and the coupling circuit 2 on the circuit board are connected substantially horizontally by short conductive wires 6.

第２図（ａｔ　、　（ｂ）は本発明の他の実施例方法を
説明するだめの平面図と断面図である。本例においては
、放熱体４上に接着されている回路基板１１は、第１図
の例に比べ厚さが厚いことが違うだけで他は同じである
。そして、半導体素子５をスルーホール３の底部の放熱
体面に直接接着すれば、半導体素子の上面が回路基板面
より低くなり、接続導線の長さが長くなるので、放熱体
４のスルーホール３底部の露出面と半導体素子５との間
に金属介在片７をはさんで、素子５の上面と回路基板の
表面とをほぼ同じ高さにしている。2(at) and (b) are a plan view and a sectional view for explaining another embodiment of the method of the present invention. In this embodiment, the circuit board 11 bonded on the heat sink 4 is Compared to the example in Figure 1, the only difference is that the thickness is thicker, and the other things are the same.Then, if the semiconductor element 5 is directly bonded to the heat sink surface at the bottom of the through hole 3, the upper surface of the semiconductor element will be the same as the circuit board surface. Since the length of the connecting conductor becomes longer, a metal intervening piece 7 is inserted between the exposed surface of the bottom of the through hole 3 of the heat sink 4 and the semiconductor element 5, and the upper surface of the element 5 and the circuit board are connected. The height is almost the same as the surface.

へ０発明の効果 本発明によれば、回路基板を分割する必要はなく、一枚
のままで済むので、組立工数の低減および価格の低廉化
を達成することができる。また、半導体素子の上面電極
よシ最短距離で回路基板の導電膜および放電体へ接続す
ることができるため、半導体素子本来の性能を残りなく
引き出せる。Effects of the Invention According to the present invention, there is no need to divide the circuit board and only one piece is required, so that it is possible to reduce the number of assembly steps and reduce the price. Further, since the upper surface electrode of the semiconductor element can be connected to the conductive film and the discharge body of the circuit board at the shortest distance, the original performance of the semiconductor element can be brought out completely.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（ａ）は本発明の一実施例を説明するだめの平面
図、同図（ｂ）は同図（ａ）のＡ−Ａ断面図、第２図（
ａ）は本発明の杷実施例を説明するための平面図、同図
（ｂ）は同図（ａ）のＡ−Ａ断面図、第３図（ａ）　、
　（ｂ）は従来の放熱体をもつ高周波用混成集積回路の
一例の平面図と断面図、第４図（ａ）　、　（ｂ）は従
来の他の例の放熱体をもつ高周波用混成集積回路の平面
図と断面図である。 １．１１，２１．３１・・開回路基板、２・・川・結合
回路、３．１３・・・・・・スルーホール、４，１４・
・・・・・放熱体、５・・・・・・半導体素子、６・・
・・・・接続導線、７・・・・・・金属介在片、８・・
・・・・放熱体突起部、１２・・・・・・接地導電膜。 （Ｕ） （ｂ） （久２ （ｂ） 茅３Ｍ！Ｊ （ａ−ン （ｂ〕 （ａＪ （ｂ〕 隼４　図FIG. 1(a) is a plan view for explaining one embodiment of the present invention, FIG. 1(b) is a sectional view taken along line A-A in FIG.
3(a) is a plan view for explaining the Loquat embodiment of the present invention, FIG. 3(b) is a sectional view taken along line A-A in FIG.
(b) is a plan view and cross-sectional view of an example of a high-frequency hybrid integrated circuit with a conventional heat sink, and FIGS. 4(a) and (b) are high-frequency hybrid integrated circuits with other conventional heat sinks. FIG. 2 is a plan view and a sectional view of 1.11, 21.31...Open circuit board, 2...River/coupling circuit, 3.13...Through hole, 4,14...
...Heat sink, 5...Semiconductor element, 6...
...Connection conductor, 7...Metal intervening piece, 8...
. . . Heat sink protrusion, 12 . . . Ground conductive film. (U) (b) (Ku 2 (b) Kaya 3M!J (a-n (b)) (aJ (b) Hayabusa 4 Fig.

Claims (1)

【特許請求の範囲】[Claims] 表面に導体膜回路が形成された回路基板を放熱体上に固
着し、さらに、前記回路基板にあけられているスルーホ
ール底部に露出する前記放熱体面に直接または介在物を
はさんで半導体素子を、その上面が前記回路基板の表面
とほぼ同じ高さになるように接着することを特徴とする
半導体素子の実装方法。A circuit board having a conductive film circuit formed on its surface is fixed onto a heat sink, and a semiconductor element is mounted directly or with an intervening object on the surface of the heat sink exposed at the bottom of a through hole drilled in the circuit board. A method for mounting a semiconductor device, characterized in that the semiconductor device is bonded so that its upper surface is approximately at the same height as the surface of the circuit board.
JP59171076A 1984-08-17 1984-08-17 Mounting method of semiconductor element Granted JPS6149444A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59171076A JPS6149444A (en) 1984-08-17 1984-08-17 Mounting method of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59171076A JPS6149444A (en) 1984-08-17 1984-08-17 Mounting method of semiconductor element

Publications (2)

Publication Number Publication Date
JPS6149444A true JPS6149444A (en) 1986-03-11
JPH0317221B2 JPH0317221B2 (en) 1991-03-07

Family

ID=15916567

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59171076A Granted JPS6149444A (en) 1984-08-17 1984-08-17 Mounting method of semiconductor element

Country Status (1)

Country Link
JP (1) JPS6149444A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5885853A (en) * 1990-06-22 1999-03-23 Digital Equipment Corporation Hollow chip package and method of manufacture

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5885853A (en) * 1990-06-22 1999-03-23 Digital Equipment Corporation Hollow chip package and method of manufacture

Also Published As

Publication number Publication date
JPH0317221B2 (en) 1991-03-07

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