JPH0317221B2 - - Google Patents
Info
- Publication number
- JPH0317221B2 JPH0317221B2 JP59171076A JP17107684A JPH0317221B2 JP H0317221 B2 JPH0317221 B2 JP H0317221B2 JP 59171076 A JP59171076 A JP 59171076A JP 17107684 A JP17107684 A JP 17107684A JP H0317221 B2 JPH0317221 B2 JP H0317221B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- semiconductor element
- heat sink
- view
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 8
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32153—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/32175—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
- H01L2224/32188—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic the layer connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
Description
【発明の詳細な説明】
イ 産業上の利用分野
本発明は、例えば、GaAs FETなどのような、
高周波用半導体素子を、放熱体をもつ回路基板に
実装する方法に関する。[Detailed Description of the Invention] A. Field of Industrial Application The present invention is applicable to
The present invention relates to a method for mounting a high-frequency semiconductor element on a circuit board having a heat sink.
ロ 従来の技術
従来、高周波用混成集積回路において、回路基
板に半導体素子を実装する場合は、第３図ａの平
面図および同図ｂの断面図に示すように、アルミ
ナ、石英、サフアイヤなどの絶縁体の上に導電膜
回路２が形成された回路基板２１を、銅、コバ
ー、鉄などの放熱体４の上に接着し、かつ、スル
ーホール１３を通して基板面の接地導電膜１２と
放熱体４とを接続し、回路基板２１上に直接半導
体素子５を固着していた。また、他の例として
は、第４図ａの平面図、同図ｂの断面図に示すよ
うに、中間に半導体素子を固着するための突起台
８を有する放熱体１４の上面に、突起台８を間に
はさんんで両側に、上面に導電膜結合回路２が形
成された２枚の回路基板３１，３１を接着し、突
起台８の上に半導体素子５を接着固定する方法と
があつた。B. Prior Art Conventionally, when mounting semiconductor elements on a circuit board in a high-frequency hybrid integrated circuit, as shown in the plan view in Figure 3a and the cross-sectional view in Figure 3b, alumina, quartz, sapphire, etc. A circuit board 21 on which a conductive film circuit 2 is formed on an insulator is bonded onto a heat sink 4 made of copper, copper, iron, etc., and connected through a through hole 13 to the ground conductive film 12 on the board surface and the heat sink. 4, and the semiconductor element 5 was directly fixed onto the circuit board 21. In addition, as another example, as shown in the plan view of FIG. 4a and the cross-sectional view of FIG. There is a method in which two circuit boards 31, 31, each having a conductive film bonding circuit 2 formed on the upper surface thereof, are bonded on both sides with 8 in between, and the semiconductor element 5 is bonded and fixed on the protruding base 8. Ta.
しかし、前者の回路基板に直接半導体素子を接
着する方法では、半導体素子表面の電極から、回
路基板上の結合回路部までの距離や接地面までの
距離が長くなるため、高周波動作における半導体
素子本来の特性を引出すことが困難であつた。ま
た、後者の、回路基板を２枚に分離し、その間の
放熱体上に半導体素子を接着する方法は、放熱体
に接着する部品点数が増加し、それによる工数増
加も加わり、歩留り低下および価格上昇をもたら
すということになる。 However, with the former method of bonding semiconductor elements directly to the circuit board, the distance from the electrodes on the surface of the semiconductor element to the coupling circuit section on the circuit board and the distance to the ground plane becomes long, so the semiconductor element is It was difficult to bring out the characteristics of In addition, the latter method, in which the circuit board is separated into two pieces and the semiconductor element is bonded on the heat sink between them, increases the number of parts to be bonded to the heat sink, which also increases the number of man-hours, resulting in lower yields and higher costs. This will result in an increase.
ハ 発明が解決しようとする問題点
上述のように、従来の実装方法では、性能をよ
くしようとすれば、高価格になるという点に問題
があり、これに対し、本発明では高性能低価格の
実装方法を得ることが課題となる。C. Problems to be Solved by the Invention As mentioned above, with the conventional mounting method, if you try to improve the performance, the problem is that it becomes expensive. The challenge is to find an implementation method.
ニ 問題点を解決するための技術手段
上記問題点に対し、本発明では、スルーホール
のあけられた回路基板を放熱体上に固着し、前記
スルーホール底部に露出する前記放熱体面に直接
または介在物を介して半導体素子を接着固定す
る。D. Technical Means for Solving the Problems To solve the above problems, the present invention fixes a circuit board with through holes on a heat sink, and directly or interposes a circuit board with a through hole on the heat sink surface exposed at the bottom of the through hole. Adhesively fix a semiconductor element through an object.
ホ 実施例
つぎに本発明を実施例により説明する。第１図
ａは本発明の一実施例を説明するための平面図、
同図ｂは同図ａのＡ−Ａ断面図である。第１図
ａ，ｂにおいて、導電膜の結合回路２が形成され
た回路基板１にはスルーホール３があけられてお
り、回路基板１は放熱体４に接着されている。し
かして、回路基板１のスルーホール３の底部に露
出する放熱体面には、半導体素子５を接着し、半
導体素子５の高さと、回路基板１の厚さはほぼ同
じ寸法であるので、半導体素子５の電極と回路基
板上の結合回路２とはほぼ水平に短い導線６によ
り接続される。E. Examples Next, the present invention will be explained using examples. FIG. 1a is a plan view for explaining one embodiment of the present invention;
Figure b is a sectional view taken along line AA in figure a. In FIGS. 1a and 1b, a through hole 3 is made in a circuit board 1 on which a conductive film coupling circuit 2 is formed, and the circuit board 1 is bonded to a heat sink 4. As shown in FIGS. Therefore, the semiconductor element 5 is bonded to the surface of the heat sink exposed at the bottom of the through hole 3 of the circuit board 1, and since the height of the semiconductor element 5 and the thickness of the circuit board 1 are approximately the same dimension, the semiconductor element The electrode 5 and the coupling circuit 2 on the circuit board are connected almost horizontally by a short conductive wire 6.
第２図ａ，ｂは本発明の他の実施例方法を説明
するための平面図と断面図である。本例において
は、放熱体４上に接着されている回路基板１１
は、第１図の例に比べ厚さが厚いことが違うだけ
で他は同じである。そして、半導体素子５をスル
ーホール３の底部の放熱体面に直接接着すれば、
半導体素子の上面が回路基板面より低くなり、接
続導線の長さが長くなるので、放熱体４のスルー
ホール３底部の露出面と半導体素子５との間に金
属介在片７をはさんで、素子５の上面と回路基板
の表面とをほぼ同じ高さにしている。 FIGS. 2a and 2b are a plan view and a sectional view for explaining another embodiment of the method of the present invention. In this example, a circuit board 11 glued onto a heat sink 4 is used.
is the same as the example shown in FIG. 1 except that it is thicker. Then, if the semiconductor element 5 is directly bonded to the heat sink surface at the bottom of the through hole 3,
Since the top surface of the semiconductor element is lower than the circuit board surface and the length of the connecting wire becomes longer, a metal intervening piece 7 is inserted between the exposed surface at the bottom of the through hole 3 of the heat sink 4 and the semiconductor element 5. The upper surface of the element 5 and the surface of the circuit board are approximately at the same height.
ヘ 発明の効果
本発明によれば、回路基板を分割する必要はな
く、一枚のままで済むので、組立工数の低減およ
び価格の低廉化を達成することができる。また、
半導体素子の上面電極より最短距離で回路基板の
導電膜および放電体へ接続することができるた
め、半導体素子本来の性能を残りなく引き出せ
る。F. Effects of the Invention According to the present invention, there is no need to divide the circuit board, and only one circuit board is required, so that it is possible to reduce the number of assembly steps and reduce the price. Also,
Since it is possible to connect to the conductive film and the discharge body of the circuit board over the shortest distance from the top electrode of the semiconductor element, the original performance of the semiconductor element can be brought out completely.
第１図ａは本発明の一実施例を説明するための
平面図、同図ｂは同図ａのＡ−Ａ断面図、第２図
ａは本発明の他実施例を説明するための平面図、
同図ｂは同図ａのＡ−Ａ断面図、第３図ａ，ｂは
従来の放熱体をもつ高周波用混成集積回路の一例
の平面図と断面図、第４図ａ，ｂは従来の他の例
の放熱体をもつ高周波用混成集積回路の平面図と
断面図である。
１，１１，２１，３１……回路基板、２……結
合回路、３，１３……スルーホール、４，１４…
…放熱体、５……半導体素子、６……接続導線、
７……金属介在片、８……放熱体突起部、１２…
…接地導電膜。
Fig. 1a is a plan view for explaining one embodiment of the present invention, Fig. 1b is a sectional view taken along line A-A in Fig. figure,
Figure b is a cross-sectional view taken along line A-A in figure a, Figures 3 a and b are a plan view and cross-sectional view of an example of a high frequency hybrid integrated circuit with a conventional heat sink, and Figures 4 a and b are cross-sectional views of a conventional high frequency hybrid integrated circuit. FIG. 7 is a plan view and a cross-sectional view of a high-frequency hybrid integrated circuit having another example of a heat sink. 1, 11, 21, 31...Circuit board, 2...Coupling circuit, 3,13...Through hole, 4,14...
...Heat sink, 5...Semiconductor element, 6...Connection conductor,
7... Metal intervening piece, 8... Heat sink protrusion, 12...
...Ground conductive membrane.
Claims (1)
熱体上に固着し、さらに、前記回路基板にあけら
れているスルーホール底部に露出する前記放熱体
面に直接または介在物をはさんで半導体素子を、
その上面が前記回路基板の表面とほぼ同じ高さに
なるように接着することを特徴とする半導体素子
の実装方法。1. A circuit board with a conductive film circuit formed on its surface is fixed onto a heat sink, and a semiconductor element is further attached directly or with an intervening object on the surface of the heat sink exposed at the bottom of a through hole drilled in the circuit board. of,
A method for mounting a semiconductor element, characterized in that the semiconductor element is bonded so that its upper surface is approximately at the same height as the surface of the circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59171076A JPS6149444A (en) | 1984-08-17 | 1984-08-17 | Mounting method of semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59171076A JPS6149444A (en) | 1984-08-17 | 1984-08-17 | Mounting method of semiconductor element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6149444A JPS6149444A (en) | 1986-03-11 |
| JPH0317221B2 true JPH0317221B2 (en) | 1991-03-07 |
Family
ID=15916567
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59171076A Granted JPS6149444A (en) | 1984-08-17 | 1984-08-17 | Mounting method of semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6149444A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0463758A1 (en) * | 1990-06-22 | 1992-01-02 | Digital Equipment Corporation | Hollow chip package and method of manufacture |
-
1984
- 1984-08-17 JP JP59171076A patent/JPS6149444A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6149444A (en) | 1986-03-11 |
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