JPH0714949A - Semiconductor module - Google Patents
Semiconductor moduleInfo
- Publication number
- JPH0714949A JPH0714949A JP5147164A JP14716493A JPH0714949A JP H0714949 A JPH0714949 A JP H0714949A JP 5147164 A JP5147164 A JP 5147164A JP 14716493 A JP14716493 A JP 14716493A JP H0714949 A JPH0714949 A JP H0714949A
- Authority
- JP
- Japan
- Prior art keywords
- ceramic substrate
- semiconductor module
- heat dissipation
- transistor
- dissipation plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は半導体モジュールに関
し、特に無線機器等に使用される高周波増幅モジュール
等の半導体モジュールに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor module, and more particularly to a semiconductor module such as a high frequency amplifier module used in radio equipment and the like.
【０００２】[0002]
【従来の技術】図２(a) は従来の半導体モジュールを示
す断面図、図２(b) はその斜視図であり、図において、
１は放熱板、２は回路パターンを形成するセラミック基
板、３はトランジスタ、４はセラミック基板２と放熱板
１とを接続するはんだ材、５はトランジスタ３をセラミ
ック基板２上の回路パターン２０に接続するはんだ材、
６はトランジスタ３とセラミック基板２上の他の回路パ
ターン２１とを電気的に接続するためのワイヤである。2. Description of the Related Art FIG. 2 (a) is a sectional view showing a conventional semiconductor module, and FIG. 2 (b) is a perspective view thereof.
1 is a heat sink, 2 is a ceramic substrate forming a circuit pattern, 3 is a transistor, 4 is a solder material for connecting the ceramic substrate 2 and the heat sink 1, and 5 is a transistor 3 connected to a circuit pattern 20 on the ceramic substrate 2. Solder material,
Reference numeral 6 is a wire for electrically connecting the transistor 3 and another circuit pattern 21 on the ceramic substrate 2.
【０００３】図２の半導体モジュールにおいて、トラン
ジスタ３はセラミック基板２上の回路パターン２０には
んだ材５によって接合された後、セラミック基板２上の
他の回路パターン２１に電気的接続のためにワイヤ６で
接合される。その後、上記トランジスタ３以外の回路を
構成する部分（図２には図示せず）が、セラミック基板
２上にハンダ付けされる。このようにして回路が形成さ
れたセラミック基板２は、放熱板１にはんだ材４で接合
される。In the semiconductor module of FIG. 2, the transistor 3 is bonded to the circuit pattern 20 on the ceramic substrate 2 by the solder material 5, and then the wire 6 is electrically connected to another circuit pattern 21 on the ceramic substrate 2. Joined by. After that, a portion (not shown in FIG. 2) constituting a circuit other than the transistor 3 is soldered onto the ceramic substrate 2. The ceramic substrate 2 on which the circuit is formed in this manner is joined to the heat dissipation plate 1 with the solder material 4.
【０００４】[0004]
【発明が解決しようとする課題】従来の半導体モジュー
ルは以上のように構成されているが、トランジスタ３の
発熱は、セラミック基板２を介して放熱板１より放熱さ
れるため、上記の構造では、放熱効果が悪いといった問
題点があった。Although the conventional semiconductor module is constructed as described above, since the heat generated by the transistor 3 is radiated from the heat radiating plate 1 through the ceramic substrate 2, the above-mentioned structure is adopted. There was a problem that the heat dissipation effect was poor.
【０００５】また、セラミック基板２と放熱板１との放
熱効果を確保するためには、はんだ材４を使用しなけれ
ばならず、このため熱によるセラミック基板の割れが生
ずる等の問題があった。Further, in order to secure the heat radiation effect between the ceramic substrate 2 and the heat radiation plate 1, the solder material 4 must be used, which causes a problem that the ceramic substrate is cracked by heat. .
【０００６】この発明は上記のような問題点を解消する
ためになされたもので、高い放熱効果を容易に得ること
のできる、また、安価なセラミック基板を割れの無い状
態で使用することのできる半導体モジュールを提供する
ことを目的としている。The present invention has been made in order to solve the above-mentioned problems, and a high heat dissipation effect can be easily obtained, and an inexpensive ceramic substrate can be used without cracks. It is intended to provide a semiconductor module.
【０００７】[0007]
【課題を解決するための手段】この発明に係る半導体モ
ジュールは、セラミック基板の，発熱量の大きな高周波
トランジスタ等の半導体素子を実装すべき部分に貫通穴
をあけ、放熱板の該高周波トランジスタ等の半導体素子
を実装すべき位置に、突起部を放熱板の打ち抜き時に同
時に形成する等により形成し、上記半導体素子を、上記
放熱板の突起部に、上記セラミック基板の貫通穴を通し
て直接ボンディングしてなるものである。In a semiconductor module according to the present invention, a through hole is formed in a portion of a ceramic substrate where a semiconductor element such as a high frequency transistor, which generates a large amount of heat, is to be mounted, and a high temperature transistor such as a high frequency transistor of a heat sink is formed. A protrusion is formed at the position where the semiconductor element is to be mounted by forming it at the same time when the heat sink is punched, and the semiconductor element is directly bonded to the protrusion of the heat sink through the through hole of the ceramic substrate. It is a thing.
【０００８】またこの発明は、上記放熱板の突起部の表
面のみに、金メッキ等の表面処理を行ってなる構造とし
たものである。Further, the present invention has a structure in which only the surface of the projection of the heat dissipation plate is subjected to a surface treatment such as gold plating.
【０００９】またこの発明は、上記セラミック基板を、
エポキシ系の導電性接着剤で放熱板に接着した構造とし
たものである。The present invention also provides the above ceramic substrate,
The structure is such that it is bonded to the heat dissipation plate with an epoxy-based conductive adhesive.
【００１０】[0010]
【作用】この発明においては、放熱板はその打ち抜き形
成時に同時に形成した凸部を持ち、その部分にセラミッ
ク基板の貫通穴を通して直接発熱量の大きなトランジス
タを取り付けることのできる構造としたから、放熱効果
を高めることが可能となる。According to the present invention, the heat dissipation plate has a convex portion formed at the same time as punching, and a transistor having a large heat generation amount can be directly attached to the convex portion through the through hole of the ceramic substrate. It becomes possible to raise.
【００１１】また、上記放熱板の凸部のみに金メッキを
設けることが可能であり、安価に金メッキを行うことが
できる。Further, since it is possible to provide gold plating only on the convex portion of the heat dissipation plate, it is possible to inexpensively perform gold plating.
【００１２】また、発熱体がセラミック基板には設けら
れないため、放熱板とセラミック基板との接着にエポキ
シ等の導電性接着剤を用いることができ、ストレスが緩
和されるため、セラミック基板の割れを防ぐことができ
る。Further, since the heating element is not provided on the ceramic substrate, a conductive adhesive such as epoxy can be used to bond the heat dissipation plate and the ceramic substrate, and stress is relieved, so that the ceramic substrate is cracked. Can be prevented.
【００１３】[0013]
【実施例】実施例１．以下、この発明の一実施例を図に
ついて説明する。図１(a) ，(b) はこの発明の一実施例
による半導体モジュールを示し、両図において、１は放
熱板、２はセラミック基板、１０はセラミック基板２に
設けられた貫通穴、３はセラミック基板２に設けられた
貫通穴１０を通して放熱板１上に設けられた高周波トラ
ンジスタ、４はセラミック基板２と放熱板１を接続する
エポキシ系等の導電性接着剤、５はトランジスタ３を放
熱板１上に直接接続するはんだ材、６はトランジスタ３
と回路パターン２１間の電気的接続のためのワイヤであ
る。EXAMPLES Example 1. An embodiment of the present invention will be described below with reference to the drawings. 1 (a) and 1 (b) show a semiconductor module according to an embodiment of the present invention. In both figures, 1 is a heat sink, 2 is a ceramic substrate, 10 is a through hole formed in the ceramic substrate 2, and 3 is a through hole. A high frequency transistor provided on the heat sink 1 through the through hole 10 provided on the ceramic substrate 2, 4 is an electrically conductive adhesive such as an epoxy adhesive that connects the ceramic substrate 2 and the heat sink 1, and 5 is a heat sink for the transistor 3. Solder material directly connected on 1, 6 is transistor 3
And a wire for electrical connection between the circuit pattern 21 and the circuit pattern 21.
【００１４】次に作用について説明する。本半導体モジ
ュールにおいては、放熱板１の打ち抜き形成時に該放熱
板１に同時に形成した突起部（凸部）１ａに、セラミッ
ク基板２の貫通穴１０を通して、発熱量の大きな高周波
トランジスタ３を直接接続することにより、トランジス
タ３の発熱に対しても大きな放熱効果を得ることができ
る。またトランジスタ３を電気的に接地する必要がある
場合、直接放熱板１にワイヤ（図示せず）を接続するこ
とが可能なため、良好な高周波特性を得ることができ
る。その際、上記放熱板１に凸部１ａがあることによっ
てその部分のみに金メッキを容易に付けることができ、
安価に製造することができる。また、本構造では、セラ
ミック基板１の熱が放熱板２に熱伝導することを気にか
ける必要が全くないため、エポキシ系等の導電性の接着
剤４でセラミック基板１と放熱板２とを接着することが
可能となり、セラミック基板１と放熱板２間のストレス
が緩和され、セラミック基板１の割れが無くなり、品質
を向上することができる。Next, the operation will be described. In this semiconductor module, the high frequency transistor 3 having a large amount of heat generation is directly connected to the protrusion (projection) 1a formed at the same time on the heat dissipation plate 1 when punching out the heat dissipation plate 1 through the through hole 10 of the ceramic substrate 2. As a result, a large heat radiation effect can be obtained even with respect to the heat generation of the transistor 3. Further, when the transistor 3 needs to be electrically grounded, a wire (not shown) can be directly connected to the heat dissipation plate 1, so that good high frequency characteristics can be obtained. At this time, since the heat dissipation plate 1 has the convex portion 1a, gold plating can be easily applied only to that portion,
It can be manufactured at low cost. Further, in this structure, there is no need to worry that the heat of the ceramic substrate 1 is thermally conducted to the heat sink 2, and therefore the ceramic substrate 1 and the heat sink 2 are separated from each other by the conductive adhesive 4 such as epoxy. Bonding becomes possible, stress between the ceramic substrate 1 and the heat dissipation plate 2 is relieved, cracks in the ceramic substrate 1 are eliminated, and quality can be improved.
【００１５】このように本実施例の半導体モジュールで
は、放熱板にその打ち抜き形成時に同時に凸部を形成
し、その凸部にセラミック基板の貫通穴を通して直接発
熱量の大きなトランジスタを取り付ける構造としたの
で、放熱効果を高めることができ、かつ上記放熱板の凸
部のみに金メッキを設けることが可能であり、安価に金
メッキを行うことができ、また、発熱体がセラミック基
板には設けられないため、放熱板とセラミック基板との
接着にエポキシ等の導電性接着剤を用いることができ、
ストレスが緩和されるため、セラミック基板の割れを防
ぐことができる等の種々の効果が得られる。As described above, in the semiconductor module of the present embodiment, the convex portion is formed at the same time when the heat sink is punched, and the transistor having large heat generation is directly attached to the convex portion through the through hole of the ceramic substrate. The heat radiation effect can be enhanced, and gold plating can be provided only on the convex portions of the heat radiation plate, gold plating can be performed at low cost, and since the heating element is not provided on the ceramic substrate, A conductive adhesive such as epoxy can be used for bonding the heat sink and the ceramic substrate,
Since the stress is relieved, various effects such as cracking of the ceramic substrate can be obtained.
【００１６】[0016]
【発明の効果】以上のように、この発明にかかる半導体
モジュールによれば、放熱板に凸部を設け、これにセラ
ミック基板の貫通穴を通して直接トランジスタを取り付
けるようにしたので、トランジスタの放熱効果が良くな
り、品質を向上することができる効果がある。As described above, according to the semiconductor module of the present invention, since the heat dissipation plate is provided with the convex portion and the transistor is directly mounted through the through hole of the ceramic substrate, the heat dissipation effect of the transistor is improved. It has the effect of improving the quality and improving the quality.
【００１７】また、このようにトランジスタを設けるよ
うにした放熱板の凸部のみに金メッキを付けることがで
き、容易に、かつ安価に半導体モジュールを製造するこ
とができる効果がある。Further, gold plating can be applied only to the convex portion of the heat dissipation plate having the transistor as described above, and the semiconductor module can be easily manufactured at low cost.
【００１８】また、セラミック基板と放熱板をエポキシ
系等の導電性接着剤で接着することができ、セラミック
の割れを防ぎ、品質を向上することができる効果があ
る。Further, the ceramic substrate and the heat dissipation plate can be adhered to each other with a conductive adhesive such as an epoxy, which has the effect of preventing the ceramic from cracking and improving the quality.
【図１】図１(a) はこの発明の第１の実施例による半導
体モジュールの断面図、図１(b) はその斜視図である。1A is a sectional view of a semiconductor module according to a first embodiment of the present invention, and FIG. 1B is a perspective view thereof.
【図２】図２(a) は従来の半導体モジュールの断面図、
図２(b) は従来の半導体モジュールモジュールの斜視図
である。FIG. 2 (a) is a cross-sectional view of a conventional semiconductor module,
FIG. 2B is a perspective view of a conventional semiconductor module module.
１ 放熱板 １ａ 突起部（凸部） ２ セラミック基板 ３ トランジスタ ４ はんだ材 ５ トランジスタ用はんだ材 ６ ワイヤ １０ セラミック基板の貫通穴 ２０ 回路パターン ２１ 回路パターン DESCRIPTION OF SYMBOLS 1 Heat sink 1a Projection (projection) 2 Ceramic substrate 3 Transistor 4 Solder material 5 Transistor solder material 6 Wire 10 Ceramic substrate through hole 20 Circuit pattern 21 Circuit pattern
Claims (4)
辺の回路をセラミック基板上に形成し、該セラミック基
板を放熱板にはんだ付けしてなる構造の半導体モジュー
ルにおいて、 上記セラミック基板は、発熱量の大きな上記高周波トラ
ンジスタ等の半導体素子を実装すべき部分に貫通穴を有
し、 上記放熱板は、該放熱板の上記半導体素子を実装すべき
部分に対応する位置に、突起部を有し、 上記高周波トランジスタ等の半導体素子は、該放熱板の
突起部に、上記セラミック基板の貫通穴を通して直接ボ
ンディングされてなることを特徴とする半導体モジュー
ル。1. A semiconductor module having a structure in which a circuit around a semiconductor element such as a high-frequency transistor is formed on a ceramic substrate and the ceramic substrate is soldered to a heat radiating plate, wherein the ceramic substrate generates a large amount of heat. A through hole is formed in a portion where a semiconductor element such as the high-frequency transistor is to be mounted, and the heat dissipation plate has a protrusion at a position corresponding to a portion where the semiconductor element is to be mounted in the heat dissipation plate; A semiconductor module, wherein a semiconductor element such as a transistor is directly bonded to a protrusion of the heat dissipation plate through a through hole of the ceramic substrate.
て、 上記放熱板の突起部は、該放熱板の上記半導体素子を実
装すべき部分に対応する位置に、上記放熱板の打ち抜き
形成時に同時に形成したものであることを特徴とする半
導体モジュール。2. The semiconductor module according to claim 1, wherein the protrusion of the heat dissipation plate is formed at a position corresponding to a portion of the heat dissipation plate where the semiconductor element is to be mounted, at the same time when the heat dissipation plate is punched. A semiconductor module characterized by being a thing.
ールにおいて、 上記放熱板の突起部のみに、金メッキの表面処理を行っ
てなり、ここに上記高周波トランジスタ等の半導体素子
がボンディングされてなることを特徴とする半導体モジ
ュール。3. The semiconductor module according to claim 1, wherein a surface treatment of gold plating is performed only on the protruding portion of the heat dissipation plate, and the semiconductor element such as the high frequency transistor is bonded thereto. A semiconductor module characterized by.
導体モジュールにおいて、 上記放熱板と上記セラミック基板との接着を、エポキシ
系の接着剤で行ってなることを特徴とする半導体モジュ
ール。4. The semiconductor module according to claim 1, wherein the heat dissipation plate and the ceramic substrate are adhered with an epoxy adhesive.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5147164A JPH0714949A (en) | 1993-06-18 | 1993-06-18 | Semiconductor module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5147164A JPH0714949A (en) | 1993-06-18 | 1993-06-18 | Semiconductor module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0714949A true JPH0714949A (en) | 1995-01-17 |
Family
ID=15424038
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5147164A Pending JPH0714949A (en) | 1993-06-18 | 1993-06-18 | Semiconductor module |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0714949A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2063455A2 (en) | 2007-11-12 | 2009-05-27 | NEC Corporation | Device mounting structure and device mounting method |
| JP2010232403A (en) * | 2009-03-27 | 2010-10-14 | Kyushu Institute Of Technology | Heatsink integrated package and method for manufacturing the same |
-
1993
- 1993-06-18 JP JP5147164A patent/JPH0714949A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2063455A2 (en) | 2007-11-12 | 2009-05-27 | NEC Corporation | Device mounting structure and device mounting method |
| US7929312B2 (en) | 2007-11-12 | 2011-04-19 | Nec Corporation | Device mounting structure and device mounting method |
| JP2010232403A (en) * | 2009-03-27 | 2010-10-14 | Kyushu Institute Of Technology | Heatsink integrated package and method for manufacturing the same |
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