JP3348581B2 - Ball grid array package type semiconductor device - Google Patents
Ball grid array package type semiconductor deviceInfo
- Publication number
- JP3348581B2 JP3348581B2 JP32977295A JP32977295A JP3348581B2 JP 3348581 B2 JP3348581 B2 JP 3348581B2 JP 32977295 A JP32977295 A JP 32977295A JP 32977295 A JP32977295 A JP 32977295A JP 3348581 B2 JP3348581 B2 JP 3348581B2
- Authority
- JP
- Japan
- Prior art keywords
- grid array
- type semiconductor
- semiconductor device
- ball grid
- package type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【０００１】[0001]
【発明の属する技術分野】本発明は、ボールグリッドア
レイパッケージ型半導体装置、特に放熱板により半導体
素子を放熱できるタイプのボールグリッドアレイパッケ
ージ型半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ball grid array package type semiconductor device, and more particularly, to a ball grid array package type semiconductor device capable of dissipating heat from a semiconductor element by a heat sink.
【０００２】[0002]
【従来の技術】図４は半導体素子で発生した熱を放熱す
る放熱板を備えたボールグリッドアレイパッケージ型半
導体装置の従来例を示す断面図である。１は３層構造の
パッケージ基板で、中央部に下にゆくほど階段状に大き
くなるデバイスホール２を有し、該デバイスホール２の
下向き段部２ａ、２ａには後述するボール電極と接続さ
れた配線膜の端部が露出している。３、３、・・・はパ
ッケージ基板１の下面に配設されたボール電極である。2. Description of the Related Art FIG. 4 is a sectional view showing a conventional example of a ball grid array package type semiconductor device provided with a heat radiating plate for radiating heat generated by a semiconductor element. Reference numeral 1 denotes a package substrate having a three-layer structure, which has a device hole 2 in the center portion, which becomes larger in a stepwise manner as it goes down, and the lower step portions 2a and 2a of the device hole 2 are connected to ball electrodes described later. The end of the wiring film is exposed. Reference numerals 3, 3, ... denote ball electrodes provided on the lower surface of the package substrate 1.
【０００３】４は例えば銅からなる放熱板で、その一方
の主面（下面）の中央部に半導体素子５が例えばエポキ
シ樹脂等からなる接着剤１０を介して接着されており、
そして、該放熱板４の半導体素子５の外側の部分がパッ
ケージ基板１の上面のデバイスホール２の周りの部分に
接着材剤１１を介して接着されてる。従って、半導体素
子５はデバイスホール２内に納まる。７、７、・・・は
半導体素子５の電極とパッケージ基板１の配線の内端と
の間を接続するコネクトワイヤ、８は半導体素子５を封
止する樹脂、９、９、・・・はパッケージ基板１の上面
に実装された電子部品、例えば受動部品であるチップコ
ンデンサあるいはチップ抵抗であり、パッケージ基板１
上面に接合材料を介して搭載されている。これは電気的
特性の向上を図るために設けられる。Reference numeral 4 denotes a radiator plate made of, for example, copper. A semiconductor element 5 is bonded to the center of one main surface (lower surface) of the radiator plate via an adhesive 10 made of, for example, epoxy resin.
A portion of the heat sink 4 outside the semiconductor element 5 is bonded to a portion around the device hole 2 on the upper surface of the package substrate 1 via an adhesive 11. Therefore, the semiconductor element 5 is accommodated in the device hole 2. , 7, ... are connect wires connecting between the electrodes of the semiconductor element 5 and the inner ends of the wiring of the package substrate 1, 8 is a resin for sealing the semiconductor element 5, and 9, 9, 9, ... are An electronic component mounted on the upper surface of the package substrate 1, for example, a chip capacitor or a chip resistor that is a passive component.
It is mounted on the upper surface via a bonding material. This is provided to improve the electrical characteristics.
【０００４】図４に示したボールグリッドアレイパッケ
ージ型半導体装置は、半導体素子５から熱が発生したと
きその熱は放熱板５を通して外部（上側）へ放熱され
る。従って、放熱性を高くすることができるという利点
がある。In the ball grid array package type semiconductor device shown in FIG. 4, when heat is generated from the semiconductor element 5, the heat is radiated to the outside (upper side) through the heat radiating plate 5. Therefore, there is an advantage that heat dissipation can be increased.
【０００５】[0005]
【発明が解決しようとする課題】ところで、上記従来の
ボールグリッドアレイパッケージ型半導体装置には、放
熱板４がパッケージ基板１の上面から突出しているの
で、パッケージ基板１の上面に電子部品９、９、・・・
を搭載するための接合材料を例えばスクリーン印刷によ
り形成することができず、そのために、作業者の手によ
りマニュアル的に形成せざるを得なかった。そのため、
生産性が悪く、コスト増を招き、好ましくなかった。そ
こで、受動部品等の搭載をさける場合が少なくなかっ
た。しかし、これでは望む電気的特性を充分に得ること
ができない場合があった。In the above-mentioned conventional ball grid array package type semiconductor device, since the heat radiating plate 4 protrudes from the upper surface of the package substrate 1, the electronic components 9, 9 are provided on the upper surface of the package substrate 1. ...
Cannot be formed by, for example, screen printing, and therefore, it has to be manually formed by an operator. for that reason,
The productivity was poor, and the cost was increased, which was not preferable. Therefore, there are many cases in which mounting of passive components and the like is avoided. However, in some cases, the desired electrical characteristics cannot be sufficiently obtained.
【０００６】本発明はこのような問題点を解決すべく為
されたものであり、ボールグリッドアレイパッケージ型
半導体装置において、パッケージ基板の反ボール電極側
の面への電子部品搭載用結合材料をスクリーン印刷等に
より自動的に形成することができるようにすることを目
的とする。The present invention has been made to solve such a problem. In a ball grid array package type semiconductor device, a bonding material for mounting electronic components on a surface of a package substrate on a side opposite to a ball electrode is screened. It is an object of the present invention to enable automatic formation by printing or the like.
【０００７】[0007]
【課題を解決するための手段】本発明ボールグリッドア
レイパッケージ型半導体装置は、パッケージ基板のデバ
イスホールの反ボール電極側に、放熱板保持段部を設
け、該放熱板保持段部に、これの深さ以下の厚さを有す
る、半導体素子がチップボンディングされた放熱板を固
着してなる。In the ball grid array package type semiconductor device of the present invention, a heat sink holding step is provided on the device hole of the package substrate on the side opposite to the ball electrode, and the heat sink holding step is provided on the heat sink holding step. A semiconductor element having a thickness equal to or less than the depth is fixed to a heat-dissipating plate chip-bonded.
【０００８】従って、本発明ボールグリッドアレイパッ
ケージ型半導体装置によれば、放熱板がその厚さ以上の
深さの放熱板保持段部に周辺部にて接着されるので、放
熱板表面がパッケージ基板の反ボール電極側の面から突
出しない。依って、パッケージ基板の反ボール電極側の
表面に電子部品搭載用結合材料を例えばスクリーン印刷
により形成することができ、作業者が手でマニュアル的
に形成する必要がない。従って、電子部品搭載のための
結合材料の形成に要するコストを低減することができ
る。Therefore, according to the ball grid array package type semiconductor device of the present invention, the radiator plate is bonded to the radiator plate holding step portion having a depth greater than the thickness of the radiator plate at the peripheral portion, so that the surface of the radiator plate is attached to the package substrate. Does not protrude from the surface on the side opposite to the ball electrode. Accordingly, the bonding material for mounting electronic components can be formed on the surface of the package substrate on the side opposite to the ball electrode by, for example, screen printing, and it is not necessary for an operator to manually form the bonding material by hand. Therefore, it is possible to reduce the cost required for forming the bonding material for mounting the electronic component.
【０００９】[0009]
【発明の実施の形態】以下、本発明を図示実施の形態に
従って詳細に説明する。図１（Ａ）乃至（Ｃ）は本発明
の第１の実施の形態を示し、（Ａ）は断面図，（Ｂ）は
平面図、（Ｃ）は底面図である。図面において、１は４
層構造のパッケージ基板で、中央部に下にゆくほど階段
状に大きくなるデバイスホール２を有し、該デバイスホ
ール２の下向き段部２ａ、２ａには後述するボール電極
と接続された配線膜の端部が露出している。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments. 1A to 1C show a first embodiment of the present invention, wherein FIG. 1A is a sectional view, FIG. 1B is a plan view, and FIG. 1C is a bottom view. In the drawing, 1 is 4
A package substrate having a layered structure, which has a device hole 2 in the center portion, which is increased stepwise as it goes down, and the stepped portions 2a, 2a of the device hole 2 are provided with a wiring film connected to a ball electrode described later. The end is exposed.
【００１０】そして、該パッケージ基板１のデバイスホ
ール２の上部には上向きの段部２ｂが形成されており、
該パッケージ基板１の図４に示す従来のボールグリッド
アレイパッケージ型半導体装置のパッケージ基板１との
大きな違いは斯かる上向きの段部２ｂを有することであ
る。３、３、・・・はパッケージ基板１の下面に配設さ
れたボール電極である。An upward step 2b is formed above the device hole 2 of the package substrate 1.
A major difference between the package substrate 1 and the package substrate 1 of the conventional ball grid array package type semiconductor device shown in FIG. 4 is that the package substrate 1 has the upward stepped portion 2b. Reference numerals 3, 3, ... denote ball electrodes provided on the lower surface of the package substrate 1.
【００１１】４は例えば銅からなる放熱板で、その厚さ
は上記段部２ｂの深さ以下にされている。そして、該放
熱板４の一方の主面（下面）の中央部に半導体素子５が
例えばエポキシ樹脂からなる接着剤１０を介して接着さ
れており、そして、該放熱板４の半導体素子５接着部分
の外側がパッケージ基板１の上面のデバイスホール２の
周りの部分に接着されており、１１はその接着剤であ
る。そして、半導体素子５はデバイスホール２内に納ま
り、また、放熱板４はパッケージ基板１の上面から食み
出さない。このように、放熱板４がパッケージ基板１の
上面から食み出さないようにされている点で、本ボール
グリッドアレイパッケージ型半導体装置は図４に示した
従来のボールグリッドアレイパッケージ型半導体装置と
大きく異なっている。Reference numeral 4 denotes a radiator plate made of, for example, copper, the thickness of which is less than the depth of the step 2b. The semiconductor element 5 is bonded to the center of one main surface (lower surface) of the heat sink 4 via an adhesive 10 made of, for example, an epoxy resin. Is adhered to a portion around the device hole 2 on the upper surface of the package substrate 1, and 11 is an adhesive. Then, the semiconductor element 5 is accommodated in the device hole 2, and the heat sink 4 does not protrude from the upper surface of the package substrate 1. In this way, the ball grid array package type semiconductor device is different from the conventional ball grid array package type semiconductor device shown in FIG. 4 in that the heat sink 4 does not protrude from the upper surface of the package substrate 1. It is very different.
【００１２】７、７、・・・は半導体素子５の電極とパ
ッケージ基板１の配線の内端との間を接続するコネクト
ワイヤ、８は半導体素子５を封止する樹脂である。９、
９、・・・は半導体素子５取付後にパッケージ基板１の
上面に実装された電子部品、例えば受動部品であるチッ
プコンデンサあるいはチップ抵抗であり、パッケージ基
板１上面に接合材料を介して搭載されている。これは電
気的特性の向上を図るために設けられる。Are connected wires for connecting the electrodes of the semiconductor element 5 to the inner ends of the wiring of the package substrate 1, and 8 is a resin for sealing the semiconductor element 5. 9,
Reference numerals 9,... Denote electronic components mounted on the upper surface of the package substrate 1 after the semiconductor element 5 is mounted, for example, chip capacitors or chip resistors as passive components, which are mounted on the upper surface of the package substrate 1 via a bonding material. . This is provided to improve the electrical characteristics.
【００１３】そして、受動部品９、９、・・・を取り付
けるための接合材料は半導体素子５取付より後の段階に
おいてスクリーン印刷により形成されたものであり、従
来においては作業者が手でマニュアルにより形成せざる
を得なかったが、本ボールグリッドアレイパッケージ型
半導体装置によれば、スクリーン印刷による形成が可能
になったのである。この電子部品９、９、・・・の搭載
はボールグリッドアレイパッケージ型半導体装置メーカ
ーが行っても良いが、ユーザー側が行っても良い。The joining material for attaching the passive components 9, 9,... Is formed by screen printing at a stage after the attachment of the semiconductor element 5, and conventionally, a worker manually and manually attaches the joining material. Although it had to be formed, the ball grid array package type semiconductor device could be formed by screen printing. The electronic components 9, 9,... May be mounted by a ball grid array package type semiconductor device maker, or may be mounted by a user.
【００１４】図１に示したボールグリッドアレイパッケ
ージ型半導体装置は、図４に示したボールグリッドアレ
イパッケージ型半導体装置と同様に、半導体素子５から
熱が発生したときその熱は放熱板５を通して外部（上
側）へ放熱される。従って、放熱性において従来のもの
より劣ることはない。本ボールグリッドアレイパッケー
ジ型半導体装置によれば、放熱板４がその厚さ以上の深
さの上向きの放熱板保持段部２ｂに周辺部にて接着され
るので、放熱板４表面がパッケージ基板１の反ボール電
極側の面から突出しない。従って、パッケージ基板１の
反ボール電極側の表面に電子部品搭載用結合材料を例え
ばスクリーン印刷により形成することができ、作業者が
手でマニュアル的に形成する必要がない。従って、電子
部品搭載用材料の形成に要するコストを低減することが
できるのである。In the ball grid array package type semiconductor device shown in FIG. 1, similar to the ball grid array package type semiconductor device shown in FIG. Heat is dissipated to (upper). Therefore, the heat dissipation is not inferior to the conventional one. According to the present ball grid array package type semiconductor device, since the heat sink 4 is bonded to the upwardly facing heat sink holding step 2b at a depth greater than its thickness at the peripheral portion, the surface of the heat sink 4 is Does not protrude from the surface on the side opposite to the ball electrode. Therefore, the bonding material for mounting electronic components can be formed on the surface on the side opposite to the ball electrode of the package substrate 1 by, for example, screen printing, and it is not necessary for an operator to manually form the bonding material by hand. Accordingly, the cost required for forming the electronic component mounting material can be reduced.
【００１５】従って、半導体素子５のＩ／Ｏ端子に接続
されるように電子部品搭載用結合材料をスクリーン印刷
により形成しておき、ユーザーが任意に選んだ例えばノ
イズ吸収用のコンデンサチップ等をＩ／Ｏ端子に接続す
ることができ、耐ノイズ性を高める等ユーザー側が任意
に電気的特性を向上させることのできるボールグリッド
アレイパッケージ型半導体装置を安価に提供するという
ことが本発明によって可能になるのである。Accordingly, a coupling material for mounting electronic components is formed by screen printing so as to be connected to the I / O terminal of the semiconductor element 5, and a user can arbitrarily select a noise absorbing capacitor chip or the like, for example. The present invention makes it possible to provide an inexpensive ball grid array package type semiconductor device which can be connected to the / O terminal and which can arbitrarily improve the electrical characteristics on the user side such as increasing noise resistance. It is.
【００１６】[0016]
【発明の実施の形態】図２は本発明ボールグリッドアレ
イパッケージ型半導体装置の第２の実施の形態を示すも
ので、本実施の形態は、電子部品としてコンデンサチッ
プ等の受動部品９と共に、プラスチックモールドされた
半導体デバイス１２、１２、・・・もパッケージ基板１
の上面に半田付けにより実装されており、この点で図１
のボールグリッドアレイパッケージ型半導体装置と相違
する。FIG. 2 shows a ball grid array package type semiconductor device according to a second embodiment of the present invention. In this embodiment, a plastic component is used together with a passive component 9 such as a capacitor chip as an electronic component. The molded semiconductor devices 12, 12, ... are also package substrates 1.
Is mounted on the upper surface of the device by soldering.
And a ball grid array package type semiconductor device.
【００１７】[0017]
【発明の実施の形態】図３は本発明ボールグリッドアレ
イパッケージ型半導体装置の第３の実施の形態を示すも
ので、本実施の形態は、電子部品としてコンデンサチッ
プ等の受動部品９と共に、半導体デバイス１３、１３、
・・・がチップボンディング、ワイヤボンディング、レ
ジンモールドにより実装されている。このチップボンデ
ィング、ワイヤボンディング、レジンモールドは受動部
品９の搭載後に行われる。このように、本発明は種々の
形態で実施することができる。FIG. 3 shows a third embodiment of a ball grid array package type semiconductor device according to the present invention. In this embodiment, a semiconductor device including a passive component 9 such as a capacitor chip as an electronic component is provided. Devices 13, 13,
Are mounted by chip bonding, wire bonding, and resin molding. The chip bonding, the wire bonding, and the resin molding are performed after the passive component 9 is mounted. As described above, the present invention can be implemented in various modes.
【００１８】[0018]
【発明の効果】以上に述べたように、本発明ボールグリ
ッドアレイパッケージ型半導体装置によれば、放熱板が
その厚さ以上の深さの放熱板保持段部に周辺部にて接着
されるので、放熱板表面がパッケージ基板の反ボール電
極側の面から突出しない。従って、パッケージ基板の反
ボール電極側の表面に電子部品搭載用結合材料を例えば
スクリーン印刷により形成することができ、作業者が手
でマニュアル的に形成する必要がない。従って、電子部
品搭載に要するコストを低減することができる。As described above, according to the ball grid array package type semiconductor device of the present invention, the heat radiating plate is bonded to the heat radiating plate holding step portion having a depth greater than its thickness at the peripheral portion. In addition, the heat sink surface does not protrude from the surface of the package substrate on the side opposite to the ball electrodes. Therefore, the bonding material for mounting electronic components can be formed on the surface of the package substrate on the side opposite to the ball electrode by, for example, screen printing, and it is not necessary for an operator to manually form the bonding material by hand. Therefore, the cost required for mounting electronic components can be reduced.
【図１】（Ａ）乃至（Ｃ）は本発明の第１の実施の形態
を示し、（Ａ）は断面図，（Ｂ）は平面図、（Ｃ）は底
面図である。1A to 1C show a first embodiment of the present invention, in which FIG. 1A is a sectional view, FIG. 1B is a plan view, and FIG. 1C is a bottom view.
【図２】本発明の第２の実施の形態を示す断面図であ
る。FIG. 2 is a sectional view showing a second embodiment of the present invention.
【図３】本発明の第３の実施の形態を示す断面図であ
る。FIG. 3 is a sectional view showing a third embodiment of the present invention.
【図４】ボールグリッドアレイパッケージ型半導体装置
の従来例を示す断面図である。FIG. 4 is a sectional view showing a conventional example of a ball grid array package type semiconductor device.
１ パッケージ基板 ２ デバイスホール ２ｂ 放熱板保持段部 ３ ボール電極 ４ 放熱板 ５ 半導体素子 ９ 電子部品のうちの特に受動部品 １２ 電子部品のうちの特に能動部品 １３ 電子部品のうちの特に能動部品 DESCRIPTION OF SYMBOLS 1 Package board 2 Device hole 2b Heat sink holding step part 3 Ball electrode 4 Heat sink 5 Semiconductor element 9 Especially passive component among electronic components 12 Especially active component among electronic components 13 Especially active component among electronic components
───────────────────────────────────────────────────── フロントページの続き (72)発明者 瀬戸 啓司 東京都品川区北品川６丁目７番35号 ソ ニー株式会社内 (56)参考文献 特開 平７−202064（ＪＰ，Ａ) 特開 平３−205860（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/12 H01L 25/00 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Keiji Seto 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (56) References JP-A-7-202064 (JP, A) JP-A Heisei 3-205860 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 23/12 H01L 25/00
Claims (2)
イスホールを有するパッケージ基板の該デバイスホール
の反ボール電極側に、放熱板保持段部を設け、 上記放熱板保持段部に、これの深さ以下の厚さを有する
放熱板の周辺部を固着し、 上記放熱板のボール電極配設側の面に半導体素子をボン
ディングし、 上記パッケージ基板の反ボール電極側面に電子部品搭載
用結合材料を設けたことを特徴とするボールグリッドア
レイパッケージ型半導体装置A ball electrode is provided on one surface, and a heat sink holding step is provided on a package substrate having a device hole on a side opposite to the ball electrode of the device hole. The peripheral part of the heat sink having a thickness of not more than the depth of the heat sink is fixed, the semiconductor element is bonded to the surface of the heat sink at the side where the ball electrodes are provided, and the electronic component mounting joint is mounted on the side of the package substrate opposite the ball electrodes. Ball grid array package type semiconductor device provided with a material
受動部品搭載用であることを特徴とする請求項１記載の
ボールグリッドアレイパッケージ型半導体装置2. The ball grid array package type semiconductor device according to claim 1, wherein the bonding material for mounting an electronic component is for mounting an active component or a passive component.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32977295A JP3348581B2 (en) | 1995-11-25 | 1995-11-25 | Ball grid array package type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32977295A JP3348581B2 (en) | 1995-11-25 | 1995-11-25 | Ball grid array package type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09148486A JPH09148486A (en) | 1997-06-06 |
| JP3348581B2 true JP3348581B2 (en) | 2002-11-20 |
Family
ID=18225099
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32977295A Expired - Fee Related JP3348581B2 (en) | 1995-11-25 | 1995-11-25 | Ball grid array package type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3348581B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990050133A (en) * | 1997-12-16 | 1999-07-05 | 김영환 | Ceramic package |
-
1995
- 1995-11-25 JP JP32977295A patent/JP3348581B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH09148486A (en) | 1997-06-06 |
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