JP2002093936A - Substrate for mounting electronic component - Google Patents
Substrate for mounting electronic componentInfo
- Publication number
- JP2002093936A JP2002093936A JP2000280074A JP2000280074A JP2002093936A JP 2002093936 A JP2002093936 A JP 2002093936A JP 2000280074 A JP2000280074 A JP 2000280074A JP 2000280074 A JP2000280074 A JP 2000280074A JP 2002093936 A JP2002093936 A JP 2002093936A
- Authority
- JP
- Japan
- Prior art keywords
- mounting
- electronic component
- substrate
- mounting recess
- recess
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10157—Shape being other than a cuboid at the active surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structure Of Printed Boards (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【技術分野】本発明は，薄型チップに対応した電子部品
搭載用基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate for mounting electronic components corresponding to a thin chip.
【０００２】[0002]
【従来技術】電子部品搭載用基板としては，たとえば，
図６に示すごとく，電子部品９８を搭載するための搭載
用凹部９９を設け，その周囲にワイヤーボンディングに
より導体パターン９２と導通を行うものがある。搭載用
凹部９９には，電子部品９８が搭載される。電子部品９
８と，搭載用凹部９９の開口周縁部９５０に形成された
導体パターン９２との間は，ボンディングワイヤー９７
により接続される。搭載用凹部９９は，絶縁基板９５６
に形成した開口穴９５１と，放熱板９５７とから構成さ
れている。ボンディングワイヤー９７は，インダクタン
スを低くするため，できるだけ直線的に結ぶ必要があ
る。2. Description of the Related Art As a substrate for mounting electronic components, for example,
As shown in FIG. 6, a mounting recess 99 for mounting an electronic component 98 is provided, and the periphery thereof is electrically connected to the conductor pattern 92 by wire bonding. The electronic component 98 is mounted in the mounting recess 99. Electronic components 9
8 and the conductor pattern 92 formed on the peripheral edge portion 950 of the mounting recess 99, a bonding wire 97 is provided.
Connected by The mounting recess 99 is provided on the insulating substrate 956.
And a heat sink 957. The bonding wires 97 need to be connected as linearly as possible to reduce inductance.
【０００３】[0003]
【解決しようとする課題】しかしながら，上記従来の電
子部品搭載用基板においては，電子部品の薄型化によ
り，電子部品９８の厚みＡが，搭載用凹部９９の開口周
縁部９５０の高さＢよりも小さくなることが多い。この
場合，電子部品９８と，搭載用凹部９９の開口周縁部９
５０との間を，図６の点線９７０に示すようにボンディ
ングワイヤーにより直線的に結ぼうとすると，搭載用凹
部９９の開口周縁部９５０が両者間の直線上に位置する
ことになり，ボンディングワイヤー９７が搭載用凹部９
９に接触してしまうおそれがある。このため，ボンディ
ングワイヤー９７を直線的に延ばすことができず，イン
ダクタンスの低減化を図ることができない。However, in the above-described conventional electronic component mounting board, the thickness A of the electronic component 98 is larger than the height B of the opening peripheral portion 950 of the mounting recess 99 due to the thinning of the electronic component. Often smaller. In this case, the electronic component 98 and the opening peripheral portion 9 of the mounting concave portion 99 are formed.
If it is attempted to linearly connect the mounting recess 99 with the bonding wire 50 by a bonding wire as shown by a dotted line 970 in FIG. 6, the opening peripheral portion 950 of the mounting concave portion 99 is located on a straight line between the two. 97 is mounting recess 9
9 may come into contact. For this reason, the bonding wire 97 cannot be extended linearly, and the inductance cannot be reduced.
【０００４】本発明はかかる従来の問題点に鑑み，イン
ダクタンスを低くすることができ，薄型電子部品に対応
した搭載用凹部を有する電子部品搭載用基板を提供しよ
うとするものである。The present invention has been made in view of the above-mentioned conventional problems, and has as its object to provide an electronic component mounting substrate which can reduce inductance and has a mounting concave portion corresponding to a thin electronic component.
【０００５】[0005]
【課題の解決手段】請求項１の発明は，電子部品を搭載
するための搭載用凹部であって該搭載用凹部の開口周縁
部を上記電子部品の高さよりも高い位置に配置してなる
電子部品搭載用基板において，上記搭載用凹部の開口周
縁部には，面取り部が設けられていることを特徴とする
電子部品搭載用基板である。According to a first aspect of the present invention, there is provided an electronic component having a mounting recess for mounting an electronic component, wherein an opening peripheral portion of the mounting recess is arranged at a position higher than the height of the electronic component. An electronic component mounting board, characterized in that the component mounting board is provided with a chamfer at an opening peripheral portion of the mounting recess.
【０００６】搭載用凹部の開口周縁部は，電子部品と搭
載用凹部周囲の基板側接合部との間をボンディングワイ
ヤーにより結んだときに，ボンディングワイヤーと最も
近接する部分である。この部分に面取り部を設けること
により，ボンディングワイヤーとの接触を抑制すること
ができる。このため，ボンディングワイヤーを直線的に
延ばすことができ，インダクタンスの低減化を図ること
ができる。[0006] The peripheral edge of the opening of the mounting recess is the portion closest to the bonding wire when the electronic component and the substrate-side joint around the mounting recess are connected by a bonding wire. By providing a chamfered portion in this portion, contact with the bonding wire can be suppressed. Therefore, the bonding wire can be extended linearly, and the inductance can be reduced.
【０００７】請求項２の発明のように，上記面取り部の
仰角Ｘと，上記電子部品における部品側接合部と上記搭
載用凹部の周囲に設けられた基板側接合部との間を結ぶ
直線の仰角Ｙとの間には，Ｙ＞Ｘ＞Ｙ／２の関係が成立
していることが好ましい。面取り部の仰角Ｘが，部品側
接合部と基板側接合部との間を結ぶ直線の仰角Ｙと同じ
かまたはそれよりも大きい場合（Ｙ≦Ｘ）には，ボンデ
ィングワイヤーが搭載用凹部の開口周縁に接触してしま
うおそれがあるため，ボンディングワイヤーを直線的に
延ばすことができないおそれがある。また，面取り部の
仰角Ｘが，上記直線の仰角Ｙの半分以下である場合（Ｘ
≦Ｙ／２）には，基板側接合部を搭載用凹部の近傍に設
けることができなくなり，ボンディングワイヤーが長く
なってしまうおそれがある。According to a second aspect of the present invention, an elevation angle X of the chamfered portion and a straight line connecting the component-side joint of the electronic component and the board-side joint provided around the mounting recess. It is preferable that a relationship of Y>X> Y / 2 is established between the angle of elevation Y. If the elevation angle X of the chamfered portion is equal to or greater than the elevation angle Y of the straight line connecting the component-side joint portion and the board-side joint portion (Y ≦ X), the bonding wire opens the mounting recess. There is a possibility that the bonding wire cannot be extended linearly because of the possibility of contact with the peripheral edge. When the elevation angle X of the chamfered portion is less than half of the elevation angle Y of the straight line (X
<≦ Y / 2), the substrate-side joint cannot be provided in the vicinity of the mounting concave portion, and the bonding wire may be lengthened.
【０００８】面取り部は，搭載用凹部の周縁の全体を囲
むように形成してもよいし，またボンディングワイヤー
を接合する基板側接合部が密集している部分にのみ形成
してもよい。[0008] The chamfered portion may be formed so as to surround the entire periphery of the mounting concave portion, or may be formed only in a portion where the bonding portions on the substrate side for bonding the bonding wires are dense.
【０００９】[0009]
【発明の実施の形態】実施形態例１ 本発明の実施形態に係る電子部品搭載用基板について，
図１〜図３を用いて説明する。本例の電子部品搭載用基
板は，図１に示すごとく，電子部品８を搭載するための
搭載用凹部９を有している。搭載用凹部９の開口周縁部
９０は，電子部品８の高さＡよりも高い位置に配置して
いる。搭載用凹部９の開口周縁部９０には，搭載用凹部
９に向かって下方へゆるやかに傾斜する面取り部１が設
けられている。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 An electronic component mounting board according to an embodiment of the present invention will be described.
This will be described with reference to FIGS. As shown in FIG. 1, the electronic component mounting board of this embodiment has a mounting recess 9 for mounting an electronic component 8. The opening peripheral edge 90 of the mounting recess 9 is arranged at a position higher than the height A of the electronic component 8. A chamfered portion 1 that is gently inclined downward toward the mounting recess 9 is provided at an opening peripheral portion 90 of the mounting recess 9.
【００１０】図２に示すごとく，面取り部１は，搭載用
凹部９の全周囲を囲むように形成されている。面取り部
１の仰角Ｘは，４０°である。電子部品８における部品
側接合部８２と上記搭載用凹部９の周囲に設けられた基
板側接合部５２との間を結ぶ直線３の仰角Ｙは５０°で
ある。上記仰角Ｘ，Ｙの間には，Ｙ＞Ｘ＞Ｙ／２の関係
が成立している。As shown in FIG. 2, the chamfered portion 1 is formed so as to surround the entire periphery of the mounting recess 9. The elevation angle X of the chamfer 1 is 40 °. The elevation angle Y of the straight line 3 connecting the component-side joint 82 of the electronic component 8 and the board-side joint 52 provided around the mounting recess 9 is 50 °. The relationship of Y>X> Y / 2 is established between the elevation angles X and Y.
【００１１】面取り部２を形成するにあたっては，搭載
用凹部９の周縁をルーターなどの機械により研削加工を
する。また，絶縁基板５６の上面を，搭載用凹部９の周
縁を集中的に押圧するための突出部６１１を持つ治具６
１により押圧する方法（図３（Ａ））や，放熱板５７に
絶縁基板５６を接着材５６３を介して熱圧着するとき
に，開口周縁部９０と放熱板５７との間に接着材５６３
を設けずに空隙５６４を形成しておき，この状態で搭載
用凹部９の周縁を集中的に押圧する方法（図３（Ｂ））
により，面取り部１を形成することもできる。In forming the chamfered portion 2, the periphery of the mounting recess 9 is ground by a machine such as a router. Also, a jig 6 having a protruding portion 611 for intensively pressing the upper surface of the insulating substrate 56 against the peripheral edge of the mounting concave portion 9.
1 (FIG. 3A), or when the insulating substrate 56 is thermocompression-bonded to the heat radiating plate 57 via the adhesive 563, the adhesive 563 is provided between the opening peripheral edge 90 and the heat radiating plate 57.
A method in which a gap 564 is formed without providing a hole, and the peripheral edge of the mounting recess 9 is pressed intensively in this state (FIG. 3B).
Thereby, the chamfered portion 1 can be formed.
【００１２】電子部品８の高さＡは０．２８ｍｍであ
り，搭載用凹部９の開口周縁部９０の高さＢ（０．４ｍ
ｍ）よりも低い。図２に示すごとく，搭載用凹部９の周
縁には，搭載用凹部９を囲むように導体パターン２が形
成されている。導体パターン２は，上記基板側接合部５
２を有するボンディングパッド２０を先端とする。本例
の電子部品搭載用基板は，導体パターン２にハンダボー
ル（図示略）を接合するボールグリッドアレイ（ＢＧ
Ａ）である。The height A of the electronic component 8 is 0.28 mm, and the height B (0.4 m
m). As shown in FIG. 2, a conductor pattern 2 is formed on the periphery of the mounting recess 9 so as to surround the mounting recess 9. The conductor pattern 2 is connected to the board-side joint 5
The bonding pad 20 having the number 2 is the tip. The electronic component mounting board of this example is a ball grid array (BG) for joining solder balls (not shown) to the conductor pattern 2.
A).
【００１３】搭載用凹部９の開口周縁部９０は，電子部
品８の部品側接合部８２と搭載用凹部９周囲の基板側接
合部５２との間をボンディングワイヤー７により結んだ
ときに，ボンディングワイヤー７と最も近接する部分で
ある。本例においては，この近接部分に面取り部１を形
成しているため，近接部分がボンディングワイヤーに接
触することを抑制できる。このため，ボンディングワイ
ヤーを直線的に延ばすことができ，インダクタンスの低
減化を図ることができる。The peripheral edge 90 of the opening of the mounting recess 9 forms a bonding wire when the bonding side between the component-side bonding portion 82 of the electronic component 8 and the substrate-side bonding portion 52 around the mounting recess 9 is connected by the bonding wire 7. 7 is the part closest to the target. In this example, since the chamfered portion 1 is formed in this proximity portion, it is possible to suppress the proximity portion from contacting the bonding wire. Therefore, the bonding wire can be extended linearly, and the inductance can be reduced.
【００１４】実施形態例２ 本例は，図４（Ａ），（Ｂ）に示すごとく，搭載用凹部
９の側壁及び面取り部１に側壁パターン２１を設けてい
る点を除いては，実施形態例１と同様である。側壁パタ
ーン２１は，絶縁基板５６の裏面側に形成された導体パ
ターン２３と接続している。Embodiment 2 This embodiment is the same as the embodiment 1 except that the side wall pattern 21 is provided on the side wall of the mounting recess 9 and the chamfered portion 1 as shown in FIGS. 4 (A) and 4 (B). Same as Example 1. The side wall pattern 21 is connected to the conductor pattern 23 formed on the back side of the insulating substrate 56.
【００１５】本例においては，搭載用凹部９の開口周縁
部９０に面取り部１を形成しているため，近接部分がボ
ンディングワイヤーに接触してショートすることを抑制
できる。また，ボンディングワイヤーを直線的に延ばす
ことができ，インダクタンスの低減化を図ることができ
る。In this embodiment, since the chamfered portion 1 is formed on the peripheral edge portion 90 of the mounting concave portion 9, it is possible to suppress a short-circuit caused by the contact of the adjacent portion with the bonding wire. Further, the bonding wire can be extended linearly, and the inductance can be reduced.
【００１６】実施形態例３ 本例は，図５に示すごとく，実施形態例１の１段の搭載
用凹部９を，多段の搭載用凹部９に代えた例である。搭
載用凹部９の各段の周縁には面取り部１が形成されてい
る。本例においても，実施形態例１と同様に，ボンディ
ングワイヤーを直線的に延ばすことができ，インダクタ
ンスの低減化を図ることができる。Third Embodiment As shown in FIG. 5, this embodiment is an example in which the single-stage mounting recess 9 of the first embodiment is replaced with a multi-stage mounting recess 9. A chamfered portion 1 is formed on the periphery of each step of the mounting recess 9. Also in this example, as in the first embodiment, the bonding wire can be extended linearly, and the inductance can be reduced.
【００１７】[0017]
【発明の効果】本発明によれば，インダクタンスを低く
することができ，薄型電子部品に対応した搭載用凹部を
有する電子部品搭載用基板を提供することができる。According to the present invention, it is possible to provide an electronic component mounting board which can reduce the inductance and has a mounting recess corresponding to a thin electronic component.
【図１】実施形態例１の電子部品搭載用基板の断面説明
図。FIG. 1 is an explanatory sectional view of an electronic component mounting board according to a first embodiment;
【図２】実施形態例１の電子部品搭載用基板の平面図。FIG. 2 is a plan view of the electronic component mounting board according to the first embodiment.
【図３】実施形態例１における，面取り部の形成方法を
示す説明図（Ａ），（Ｂ）。FIGS. 3A and 3B are explanatory views showing a method of forming a chamfered portion in the first embodiment.
【図４】実施形態例２の電子部品搭載用基板の断面図
（ａ），及び平面図（Ｂ）。4A and 4B are a cross-sectional view and a plan view, respectively, of an electronic component mounting board according to a second embodiment.
【図５】実施形態例３の電子部品搭載用基板の断面図。FIG. 5 is a sectional view of an electronic component mounting board according to a third embodiment.
【図６】従来例の電子部品搭載用基板の断面説明図。FIG. 6 is an explanatory sectional view of a conventional electronic component mounting substrate.
１．．．面取り部， ２．．．導体パターン， ２０．．．ボンディングパッド， ５２．．．基板側接合部， ５６．．．絶縁基板， ５７．．．放熱板， ６１．．．治具， ７．．．ボンディングワイヤー， ８．．．電子部品， ９．．．搭載用凹部， 1. . . Chamfered part, 2. . . Conductor pattern, 20. . . Bonding pad, 52. . . Board-side joint, 56. . . Insulating substrate, 57. . . Heat sink, 61. . . Jig, 7. . . 7. bonding wire; . . Electronic components, 9. . . Mounting recess,
Claims (2)
あって該搭載用凹部の開口周縁部を上記電子部品の高さ
よりも高い位置に配置してなる電子部品搭載用基板にお
いて，上記搭載用凹部の開口周縁部には，面取り部が設
けられていることを特徴とする電子部品搭載用基板。1. An electronic component mounting substrate, comprising: a mounting recess for mounting an electronic component, wherein an opening peripheral portion of the mounting recess is arranged at a position higher than a height of the electronic component. A substrate for mounting electronic components, characterized in that a chamfered portion is provided at an edge of an opening of a concave portion for use.
Ｘと，上記電子部品における部品側接合部と上記搭載用
凹部の周囲に設けられた基板側接合部との間を結ぶ直線
の仰角Ｙとの間には，Ｙ＞Ｘ＞Ｙ／２の関係が成立して
いることを特徴とする電子部品搭載用基板。2. An elevation angle X of the chamfered portion and a straight elevation angle Y connecting a component side joint portion of the electronic component and a board side joint portion provided around the mounting concave portion. And a relationship of Y>X> Y / 2 is established between the electronic component mounting substrate and the electronic component mounting substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000280074A JP2002093936A (en) | 2000-09-14 | 2000-09-14 | Substrate for mounting electronic component |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000280074A JP2002093936A (en) | 2000-09-14 | 2000-09-14 | Substrate for mounting electronic component |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002093936A true JP2002093936A (en) | 2002-03-29 |
Family
ID=18764976
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000280074A Pending JP2002093936A (en) | 2000-09-14 | 2000-09-14 | Substrate for mounting electronic component |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002093936A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006229568A (en) * | 2005-02-17 | 2006-08-31 | Kyocera Corp | High-frequency line/waveguide converter, and electronic apparatus |
| JP2011129854A (en) * | 2009-12-16 | 2011-06-30 | Gjintops | Light-emitting diode package and manufacturing method thereof |
| JP2012134547A (en) * | 2012-03-15 | 2012-07-12 | Omron Corp | Semiconductor device and microphone |
| JP2014170893A (en) * | 2013-03-05 | 2014-09-18 | Taiyo Yuden Co Ltd | Camera module |
-
2000
- 2000-09-14 JP JP2000280074A patent/JP2002093936A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006229568A (en) * | 2005-02-17 | 2006-08-31 | Kyocera Corp | High-frequency line/waveguide converter, and electronic apparatus |
| JP4663351B2 (en) * | 2005-02-17 | 2011-04-06 | 京セラ株式会社 | Electronic equipment |
| JP2011129854A (en) * | 2009-12-16 | 2011-06-30 | Gjintops | Light-emitting diode package and manufacturing method thereof |
| JP2012134547A (en) * | 2012-03-15 | 2012-07-12 | Omron Corp | Semiconductor device and microphone |
| JP2014170893A (en) * | 2013-03-05 | 2014-09-18 | Taiyo Yuden Co Ltd | Camera module |
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