JPS6147000B2 - - Google Patents
Info
- Publication number
- JPS6147000B2 JPS6147000B2 JP53072101A JP7210178A JPS6147000B2 JP S6147000 B2 JPS6147000 B2 JP S6147000B2 JP 53072101 A JP53072101 A JP 53072101A JP 7210178 A JP7210178 A JP 7210178A JP S6147000 B2 JPS6147000 B2 JP S6147000B2
- Authority
- JP
- Japan
- Prior art keywords
- printed circuit
- prepreg
- circuit board
- multilayer printed
- molding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000465 moulding Methods 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 21
- 229920005989 resin Polymers 0.000 claims description 18
- 239000011347 resin Substances 0.000 claims description 18
- 239000011521 glass Substances 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 16
- 239000004744 fabric Substances 0.000 claims description 15
- 239000000853 adhesive Substances 0.000 claims description 14
- 230000001070 adhesive effect Effects 0.000 claims description 14
- 239000000155 melt Substances 0.000 claims description 4
- IISBACLAFKSPIT-UHFFFAOYSA-N bisphenol A Chemical class C=1C=C(O)C=CC=1C(C)(C)C1=CC=C(O)C=C1 IISBACLAFKSPIT-UHFFFAOYSA-N 0.000 claims description 3
- 239000003822 epoxy resin Substances 0.000 claims description 3
- 229920000647 polyepoxide Polymers 0.000 claims description 3
- 230000001747 exhibiting effect Effects 0.000 claims description 2
- 239000000758 substrate Substances 0.000 description 30
- 239000010410 layer Substances 0.000 description 21
- 239000002966 varnish Substances 0.000 description 15
- 238000010438 heat treatment Methods 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 239000011889 copper foil Substances 0.000 description 7
- ZWEHNKRNPOVVGH-UHFFFAOYSA-N 2-Butanone Chemical compound CCC(C)=O ZWEHNKRNPOVVGH-UHFFFAOYSA-N 0.000 description 6
- 239000004593 Epoxy Substances 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 6
- 238000000576 coating method Methods 0.000 description 6
- 230000000052 comparative effect Effects 0.000 description 6
- 238000001035 drying Methods 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- XNWFRZJHXBZDAG-UHFFFAOYSA-N 2-METHOXYETHANOL Chemical compound COCCO XNWFRZJHXBZDAG-UHFFFAOYSA-N 0.000 description 2
- ROSDSFDQCJNGOL-UHFFFAOYSA-N Dimethylamine Chemical compound CNC ROSDSFDQCJNGOL-UHFFFAOYSA-N 0.000 description 2
- QGBSISYHAICWAH-UHFFFAOYSA-N dicyandiamide Chemical compound NC(N)=NC#N QGBSISYHAICWAH-UHFFFAOYSA-N 0.000 description 2
- 230000009477 glass transition Effects 0.000 description 2
- 230000005484 gravity Effects 0.000 description 2
- 230000003993 interaction Effects 0.000 description 2
- 239000012046 mixed solvent Substances 0.000 description 2
- 238000009941 weaving Methods 0.000 description 2
- UHOVQNZJYSORNB-UHFFFAOYSA-N Benzene Chemical compound C1=CC=CC=C1 UHOVQNZJYSORNB-UHFFFAOYSA-N 0.000 description 1
- PEEHTFAAVSWFBL-UHFFFAOYSA-N Maleimide Chemical compound O=C1NC(=O)C=C1 PEEHTFAAVSWFBL-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- XLJMAIOERFSOGZ-UHFFFAOYSA-M cyanate Chemical compound [O-]C#N XLJMAIOERFSOGZ-UHFFFAOYSA-M 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- XXBDWLFCJWSEKW-UHFFFAOYSA-N dimethylbenzylamine Chemical compound CN(C)CC1=CC=CC=C1 XXBDWLFCJWSEKW-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 150000003949 imides Chemical class 0.000 description 1
- 238000000691 measurement method Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000006082 mold release agent Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- -1 temperature 135°C Substances 0.000 description 1
Landscapes
- Laminated Bodies (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
本発明は、多層印刷回路板の積層した内外層パ
ターンの位置ずれを少くする製造方法に関する。
ガラスエポキシ系銅張積層板を用いて多層印刷
回路板を製造する場合、内外層パターンの位置合
せ精度をいかに確保するかは、製造方法における
重要な課題である。特に、近頃は電子計算機の高
容量化、処理速度の高速化に伴い、用いられる印
刷回路板の高密度化が要求されている。従つてパ
ターンは格子間隔がせまくなる上に、多層化が進
められるので、各層パターンの位置ずれに対する
許容幅はますます厳しくなつてきた。位置合せ精
度の問題は、高密度化多層回路板の製造技術上の
最大の問題と言つても過言ではない。
多層印刷回路板の層間パターンの位置ずれの原
因は、数多くの製造工程で発生し得る。しかしな
がら、発明者らの検討によると、熱圧着による多
層化成形工程によつて生じる位置ずれが圧倒的に
大きく、それ以外の工程に起因する累積された位
置ずれは、多層化成形工程に起因する位置ずれの
15％以下であつた。多層化成形工程で生じる位置
ずれは、構成基板である各印刷回路板と接着用プ
リプレグの積み重ね作業上のずれと、加熱、加圧
によつて生じる基板の変形に基づくずれとが重な
り合つて現われる。積み重ね作業による単純なず
れは、ガイドピン、ガイド板を用いる等により改
良されてきたが、用いられる基板が厚さ0.1〜0.2
mmの薄物であること、プリプレグの端部はくずれ
易いことなどを考慮すると現在の精度がせい一杯
と考えられる。
一方、加熱、加圧によつて生じる基板の変形に
対する改良は、これまでに様々な方法が試みられ
たが、いずれも10層、14層と言うような高密度多
層印刷回路板に求められる精密なパターン合せ精
度を満足するまでには至つていない。
多層化成形をする前に基板をあらかじめエージ
ングして内部歪を取り除く方法が提案されてい
る。しかし、本発明者らの検討によると、エージ
ングによつて内部歪を取り除いた基板を用いて多
層化成形を行うと、その基板は再び変形してしま
い、結果的に位置ずれは解消されないことが認め
られた。基板に含浸硬化している樹脂分のガラス
転移温度以下で、長時間、加熱、冷却をくり返す
方法も提案されているが、顕著な効果は認められ
なかつた。
多層化成形による基板の変形量には異方性があ
ることは既に知られている。これは内在するガラ
スクロスの織り糸の方向に起因することから、基
板と接着用プリプレグに内在するガラスクロスの
織り糸の方向を互に直交させる方法が行われてい
るが、これだけでは多層印刷回路板のパターン精
度を充分に向上することができなかつた。
多層化成形時の温度よりも高いガラス転移点を
もつレジンの基板を用いる方法もあるが、これら
はイミド系、マレイミド系等の基板になり、エポ
キシ系に比べコストが高い。また、比較的安価な
シアネート系基板とエポキシ系プリプレグとの組
合せによる熱圧着成形では、パターン合せ精度の
向上はある程度認められたが、10層、14層等の高
密度多層印刷回路板の実用精度を満足するには至
らなかつた。
多層化成形で生じる基板の変形は、加熱による
基板の軟化、内部応力の解放、プリプレグレジン
の溶融、溶融レジンの流動による基板の索引、プ
リプレグレジンの硬化収縮等の相互作用によつて
発生し、その変形量、方向は熱、圧力の他に基板
およびプリプレグ中に内在するガラスクロスによ
つても影響を受ける。本発明者らは、これら各要
因の相互作用について種々検討した結果、熱圧着
過程でのプリプレグレジンの溶融粘度が大きな影
響力をもつことを確認し、これをコントロールす
ることによつて基板の変形量および変形量のばら
つきを少くし、多層印刷回路板のパターン合せ精
度を著しく向上させる方法を見出した。しかしな
がらプリプレグの溶融粘度をコントロールするの
みでは、層間厚さや接着強度、半田浴耐熱性等の
特性をバランスさせることが難しいことが判つ
た。
本発明は、このような事実に基づいてなされた
もので、多層化成形時のプリプレグレジンの溶融
粘度および成形圧力の双方をコントロールするこ
とによつて、実用特性のバルンスも充分に保ち、
かつパターン合せ精度を著しく向上させる高密度
多層印刷回路板の製造方法に成功した。
本発明の目的はパターン合せ精度が高い高密度
多層印刷回路板の製造方法を提供するにある。
本発明は接着シートとして、含浸されている半
硬化レジンの130℃における溶融粘度の最低値が
30〜300ポイズを示すプリプレグを用いること、
及び成形圧力を20Kg/cm2以下として熱圧着成形す
ることを特徴とする。
積層板を絶縁基板１とし、両面に銅箔３を貼つ
た銅張積層板をｂのようにエツチング処理して印
刷回路を形成させる。もしくはアデイテイブ法め
つきによつて絶縁基板１上に印刷回路を形成させ
るなどによつて得られた外層用印刷回路板４、内
層用印刷回路板５，５とは異なるパターンを有す
る内層用印刷回路板６の３積を用意する。内層用
印刷回路板には表裏を電気的に導通させるための
接続孔９を開ける場合もある。この孔は多層化成
形後、内層のブラインドホールとなる。接着シー
トとしては130℃の溶融粘度の最低値が30〜300ポ
イズを示すような半硬化レジンを含浸したプリプ
レグ２を用いる。このようなプリプレグは、プリ
プレグ製造の際、乾燥温度および時間をコントロ
ールすることによつて容易に得られる。例えばブ
ロム化ビスフエノール系エポキシレジン（エポキ
シ当量455〜500）100重量部に対してジシアンジ
アミド3.5重量部、ベンジルジメチルアミン0.2重
量部を加え、メチルエチルケトン・メチルセロソ
ルブ混合溶媒に溶解して得たワニスによつてプリ
プレグを製造する場合、ワニス比重を1.15に調整
し、たて型塗工機を用いて、温度150℃、ガラス
クロスの速度（塗工速度）1.5ｍ毎分の条件で塗
工→乾燥を行つた結果、ガラスクロスに含浸され
ている半硬化レジンの130℃の溶融粘度の最低値
が300ポイズのプリプレグを得た。また、同じワ
ニスを用いて、温度135℃、ガラスクロスの速度
1.5ｍ毎分の条件で塗工→乾燥を行つた結果、130
℃の溶融粘度の最低値が40ポイズのプリプレグを
得た。ここで用いたワニスの組成は公知であり、
上述のプリプレグの製造方法も公知である。ただ
し、ワニス比重、乾燥温度、ガラスクロスの速度
（塗工速度）の各条件は固定のものではなく、塗
工機の種類、熱風の風量、環境温度および湿度な
どによつて変動し得るものである。しかし、130
℃の溶融粘度の最低値が30〜300ポイズであるよ
うなプリプレグを製造し得る条件は、容易に得ら
れるものである。
Ｃのように外層用印刷回路板４を外側に配し、
内層用印刷回路板５および６を前記プリプレグを
介して交互に重ね合せ、任意の層数を構成した
後、ｄのように、20Kg/cm2以下の圧力によつて熱
圧着成形する。圧力が20Kg/cm2を越えると基板の
変形量が大きくなり、高密度多層印刷回路板とし
て満足し得る位置合せ精度が得られなくなる。下
限圧力はとくに限定はないが、４Kg/cm2以上が好
ましい。これより小さくなると成形後そり、ねじ
れが発生し易くなる傾向がある。
成形温度は、通常、170〜180℃で行われるが、
必要によつては、130℃付近を中心に２段階の加
熱方法を行うのも、プリプレグレジンの流動を滑
らかにする点で効果的である。次いで外層用印刷
回路板の露出している銅箔３′をエツチングして
導電回路７を形成し、必要によつては貫通穴８を
あけ、ｅで示される多層印刷回路板を得る。
本発明の特徴は、低い溶融粘度をもつプリプレ
グを接着シートとして用い、これを低い圧力によ
つて熱圧着成形することにあるので、層間厚さを
充分にコントロールしながら、溶融レジンの流動
によつて引き起される基板の変形を抑制すること
ができるので内外層パターンの位置合せ精度が著
しく向上した。
以下、実施例に基づいて具体的に説明する。
実施例 １
ブロム化ビスフエノール系エポキシレジン（エ
ポキシ当量455〜500）100重量部に対してジシア
ンジアミド3.5重量部、ベンジンジメチルアミン
0.2重量部を加え、メチルエチルケトン・メチル
セロソルブ混合溶媒に溶解してワニスとした。こ
のワニスを用いて、絶縁基材厚さ0.2mm、銅箔厚
さ35μｍのガラス・エポキシ系両面銅張積層板を
作り、片面の銅箔をエツチングして回路を形成し
た基板（基板Ａ）２枚、両面の銅箔をエツチング
して信号パターンを形成した基板（基板Ｂ）３
枚、両面の銅箔をエツチングして電源パターンを
形成した基板（基板Ｃ）２枚を構成基板とした。
一方、前記ワニスを厚さ0.1mmのガラスクロスに
塗布して150℃で７分間塗工機中で乾燥し130℃の
溶融粘度の最低値が300ポイズを示すような接着
用プリプレグを得た。次に基板Ａの回路パターン
のない側を外側にし、基板をＡ，Ｂ，Ｃ，Ｂ，
Ｃ，Ａのように重ね各基板の間に接着用プリプレ
グ各３枚ずつを介して回路パターン層が14層にな
るように構成し、室温から170℃までの昇温速度
４〜６℃毎分、170℃保持60分、圧力10Kg/cm2の条
件で熱圧着成形して高密度多層印刷回路板を得
た。
実施例 ２
実施例１と同じワニス、同じ両面銅張積層板を
用いて実施例１と同様に基板Ａ，Ｂ，Ｃをそれぞ
れ２枚、３枚、２枚作つた。このうちの基板Ｂに
はパツド部分に1.0mmφの孔を開けた。一方、実
施例１と同じワニス、同じガラスクロス、同じ方
法によつて接着用プリプレグを作製した。作製に
当つて、140℃で６分乾燥した。含浸レジンの130
℃における溶融粘度の最低値は60ポイズであつ
た。以下、実施例１と同方法で14層を構成し、温
度130℃15分＋170℃60分、圧力10Kg/cm2の条件で
熱圧着成形して高密度多層印刷回路板を得た。
実施例 ３
実施例１と同じワニス、ガラスクロスを用い、
133℃で６分乾燥して130℃における含浸レジンの
溶融粘度の最低値が35ポイズを示す接着用プリプ
レグを得た。その他は実施例２と全く同様にして
高密度多層印刷回路板を得た。
実施例 ４
実施例１と同様のワニス、ガラスクロスを用い
146℃で６分乾燥し含浸レジンの130℃における溶
融粘度の最低値が150ポイズのプリプレグを作製
した。次に基板とプリプレグの構成は実施例１と
同様にし、室温から170℃までの昇温速度４〜６
℃毎分、170℃保持60分、圧力17Kg/cm2で熱圧着成
形し、高密度多層印刷回路板を得た。
比較例 １
実施例１と同様のワニス、ガラスクロスを用い
152℃で６分乾燥し、130℃における溶融粘度の最
低値が400ポイズのプリプレグを作製した。
以下、実施例１と同じ材料構成によつて、温度
130℃15分＋170℃60分、圧力25Kg/cm2の条件で熱
圧着成形して高密度多層印刷回路板を得た。
比較例 ２
実施例１と同じワニス、ガラスクロスを用い、
143℃で６分乾燥して130℃における溶融粘度の最
低値が100ポイズのプリプレグを作製した。この
プリプレグを用い、実施例２と同じ構成によつ
て、室温から170℃までの昇温速度４〜６℃毎
分、170℃保持60分、圧力40Kg/cm2で熱圧着成形
し、高密度多層印刷回路板を得た。
比較例 ３
実施例１と同じワニス、ガラスクロスを用い、
151℃で６分乾燥して130℃における溶融粘度の最
低値が360ポイズを示すプリプレグを作製した。
このプリプレグを用い実施例２と同じ材料構成に
し比較例２と同じ成形条件によつて高密度多層印
刷回路板を得た。
以上の実施例、比較例で得られた高密度多層印
刷回路板について、成形前後の各層の伸縮率、層
間厚さ、ボイドの有無を実測し、下表に示した。
各層の伸縮率の測定法は、各層パターンに約430
mm間隔で基点マークをつけ、マーク周辺にはあら
かじめ離型剤を塗布しておいて、成形後、容易に
削り出せるようにしておき、熱圧着前後の基点マ
ーク間隔の寸法変化量から求めた。
The present invention relates to a manufacturing method for reducing misalignment of laminated inner and outer layer patterns of a multilayer printed circuit board. When manufacturing a multilayer printed circuit board using a glass epoxy copper-clad laminate, how to ensure alignment accuracy of inner and outer layer patterns is an important issue in the manufacturing method. In particular, with the recent increase in the capacity and processing speed of electronic computers, there has been a demand for higher densities in the printed circuit boards used. Therefore, as the lattice spacing of patterns becomes narrower and the number of layers increases, the tolerance for misalignment of patterns in each layer becomes increasingly strict. It is no exaggeration to say that the problem of alignment accuracy is the biggest problem in manufacturing technology for high-density multilayer circuit boards. The causes of misalignment of interlayer patterns in multilayer printed circuit boards can occur during a number of manufacturing steps. However, according to the inventors' study, the positional deviation caused by the multilayer molding process using thermocompression bonding is overwhelmingly large, and the accumulated positional deviation caused by other processes is due to the multilayer molding process. of misalignment
It was less than 15%. Misalignment that occurs during the multilayer molding process is caused by a combination of misalignment due to the stacking process of each component printed circuit board and adhesive prepreg, and misalignment due to deformation of the substrate caused by heating and pressurization. . Simple misalignment due to stacking work has been improved by using guide pins and guide plates, but the thickness of the substrate used is 0.1 to 0.2
Considering that it is a thin material (mm) and that the edges of the prepreg break easily, the current accuracy is considered to be at its best. On the other hand, various methods have been tried so far to improve the deformation of the board caused by heating and pressurization, but none of them have achieved the precision required for high-density multilayer printed circuit boards such as 10 or 14 layers. However, we have not yet reached the point where the pattern matching accuracy is satisfied. A method has been proposed in which the substrate is aged before multilayer molding to remove internal strain. However, according to studies conducted by the present inventors, if multilayer molding is performed using a substrate whose internal strain has been removed by aging, the substrate will be deformed again, and as a result, the misalignment will not be resolved. Admitted. A method of repeatedly heating and cooling for a long time at a temperature below the glass transition temperature of the resin impregnated into the substrate and hardened has been proposed, but no significant effect has been observed. It is already known that there is anisotropy in the amount of deformation of a substrate due to multilayer molding. This is due to the direction of the weaving threads of the glass cloth inherent in the board, so a method has been used in which the directions of the weaving threads of the glass cloth inherent in the substrate and the adhesive prepreg are made to be perpendicular to each other, but this alone is not enough to make multilayer printed circuit boards. It was not possible to sufficiently improve pattern accuracy. There is also a method of using a resin substrate with a glass transition point higher than the temperature during multilayer molding, but these are imide-based, maleimide-based, etc. substrates, and are higher in cost than epoxy-based substrates. In addition, in thermocompression molding using a combination of relatively inexpensive cyanate-based substrates and epoxy-based prepregs, pattern alignment accuracy was improved to some extent, but practical accuracy for high-density multilayer printed circuit boards such as 10 and 14 layers was observed. I was not satisfied with that. Deformation of the substrate that occurs during multilayer molding occurs due to interactions such as softening of the substrate due to heating, release of internal stress, melting of the prepreg resin, indexing of the substrate due to the flow of molten resin, curing shrinkage of the prepreg resin, etc. The amount and direction of deformation are affected not only by heat and pressure but also by the glass cloth present in the substrate and prepreg. As a result of various studies on the interaction of these factors, the present inventors confirmed that the melt viscosity of the prepreg resin during the thermocompression bonding process has a large influence, and by controlling this, the deformation of the substrate can be improved. We have discovered a method to significantly improve the pattern alignment accuracy of multilayer printed circuit boards by reducing the variation in the amount and deformation amount. However, it has been found that it is difficult to balance properties such as interlayer thickness, adhesive strength, and solder bath heat resistance by simply controlling the melt viscosity of the prepreg. The present invention has been made based on these facts, and by controlling both the melt viscosity and molding pressure of prepreg resin during multilayer molding, it is possible to maintain a sufficient balance of practical properties.
We also succeeded in creating a method for manufacturing high-density multilayer printed circuit boards that significantly improves pattern alignment accuracy. An object of the present invention is to provide a method for manufacturing a high-density multilayer printed circuit board with high pattern matching accuracy. The present invention is an adhesive sheet that has a minimum melt viscosity of impregnated semi-cured resin at 130℃.
using prepreg exhibiting 30 to 300 poise;
It is characterized by thermocompression molding at a molding pressure of 20 kg/cm 2 or less. A laminate is used as an insulating substrate 1, and a copper-clad laminate with copper foil 3 pasted on both sides is etched as shown in b to form a printed circuit. Or an inner layer printed circuit having a pattern different from the outer layer printed circuit board 4 and the inner layer printed circuit boards 5, 5 obtained by forming a printed circuit on the insulating substrate 1 by additive plating. Prepare three stacks of board 6. Connection holes 9 may be formed in the inner layer printed circuit board for electrical continuity between the front and back sides. This hole becomes a blind hole in the inner layer after multilayer molding. As the adhesive sheet, a prepreg 2 impregnated with a semi-cured resin having a minimum melt viscosity of 30 to 300 poise at 130° C. is used. Such a prepreg can be easily obtained by controlling the drying temperature and time during prepreg production. For example, a varnish obtained by adding 3.5 parts by weight of dicyandiamide and 0.2 parts by weight of benzyldimethylamine to 100 parts by weight of a brominated bisphenol-based epoxy resin (epoxy equivalent: 455-500) and dissolving it in a mixed solvent of methyl ethyl ketone and methyl cellosolve. When manufacturing prepreg, adjust the specific gravity of the varnish to 1.15, and use a vertical coating machine to coat and dry at a temperature of 150°C and a glass cloth speed (coating speed) of 1.5 m/min. As a result, a prepreg with a minimum melt viscosity of 300 poise at 130°C of the semi-cured resin impregnated into the glass cloth was obtained. Also, using the same varnish, temperature 135℃, glass cloth speed
As a result of coating and drying at 1.5 m/min, 130
A prepreg with a minimum melt viscosity of 40 poise at °C was obtained. The composition of the varnish used here is known;
The method for manufacturing the prepreg described above is also known. However, the conditions such as varnish specific gravity, drying temperature, and glass cloth speed (coating speed) are not fixed and may vary depending on the type of coating machine, amount of hot air, environmental temperature, humidity, etc. be. But 130
Conditions for producing a prepreg having a minimum melt viscosity of 30 to 300 poise at °C are easily obtainable. Place the outer layer printed circuit board 4 on the outside as shown in C.
After the inner layer printed circuit boards 5 and 6 are stacked alternately through the prepreg to form an arbitrary number of layers, they are thermocompression molded under a pressure of 20 kg/cm 2 or less, as shown in d. If the pressure exceeds 20 Kg/cm 2 , the amount of deformation of the board will increase, making it impossible to achieve alignment accuracy that is satisfactory for a high-density multilayer printed circuit board. The lower limit pressure is not particularly limited, but is preferably 4 kg/cm 2 or more. If it is smaller than this, warpage and twisting tend to occur more easily after molding. The molding temperature is usually 170-180℃,
If necessary, a two-step heating method centered around 130° C. may be effective in smoothing the flow of the prepreg resin. Next, the exposed copper foil 3' of the outer layer printed circuit board is etched to form a conductive circuit 7, and if necessary, a through hole 8 is made, thereby obtaining a multilayer printed circuit board indicated by e. The feature of the present invention is that a prepreg with a low melt viscosity is used as an adhesive sheet, and this is thermocompression molded under low pressure. Therefore, the interlayer thickness can be sufficiently controlled, and the flow of the molten resin can be controlled. Since the deformation of the substrate caused by this process can be suppressed, the alignment accuracy of the inner and outer layer patterns has been significantly improved. Hereinafter, a detailed description will be given based on examples. Example 1 3.5 parts by weight of dicyandiamide and benzine dimethylamine per 100 parts by weight of brominated bisphenol epoxy resin (epoxy equivalent 455-500)
0.2 parts by weight was added and dissolved in a mixed solvent of methyl ethyl ketone and methyl cellosolve to obtain a varnish. Using this varnish, a glass-epoxy double-sided copper-clad laminate with an insulating base material thickness of 0.2 mm and a copper foil thickness of 35 μm was made, and the copper foil on one side was etched to form a circuit (substrate A) 2 A board (substrate B) on which a signal pattern is formed by etching copper foil on both sides of the board (substrate B) 3
Two substrates (substrates C) on which power supply patterns were formed by etching copper foil on both sides were used as constituent substrates.
On the other hand, the varnish was applied to a glass cloth having a thickness of 0.1 mm and dried in a coating machine at 150°C for 7 minutes to obtain an adhesive prepreg having a minimum melt viscosity of 300 poise at 130°C. Next, turn the side of board A without the circuit pattern outside, and turn the boards A, B, C, B, etc.
Stack them as shown in C and A so that there are 14 circuit pattern layers with three sheets of adhesive prepreg between each board, and heat up from room temperature to 170 degrees Celsius at a heating rate of 4 to 6 degrees Celsius per minute. A high-density multilayer printed circuit board was obtained by thermocompression molding at 170° C. for 60 minutes and a pressure of 10 Kg/cm 2 . Example 2 Two, three, and two substrates A, B, and C were made in the same manner as in Example 1 using the same varnish and the same double-sided copper-clad laminates as in Example 1, respectively. A hole of 1.0 mmφ was drilled in the pad part of substrate B. On the other hand, an adhesive prepreg was produced using the same varnish, the same glass cloth, and the same method as in Example 1. During production, it was dried at 140°C for 6 minutes. Impregnated resin 130
The lowest value of melt viscosity at °C was 60 poise. Thereafter, 14 layers were constructed in the same manner as in Example 1, and thermocompression molded at a temperature of 130° C. for 15 minutes + 170° C. for 60 minutes and a pressure of 10 Kg/cm 2 to obtain a high-density multilayer printed circuit board. Example 3 Using the same varnish and glass cloth as Example 1,
After drying at 133°C for 6 minutes, an adhesive prepreg having a minimum melt viscosity of 35 poise of the impregnated resin at 130°C was obtained. Otherwise, a high-density multilayer printed circuit board was obtained in the same manner as in Example 2. Example 4 Using the same varnish and glass cloth as Example 1
The impregnated resin was dried for 6 minutes at 146°C to produce a prepreg having a minimum melt viscosity of 150 poise at 130°C. Next, the structure of the substrate and prepreg was the same as in Example 1, and the heating rate was 4 to 6 from room temperature to 170°C.
A high-density multilayer printed circuit board was obtained by thermocompression molding at a temperature of 170°C per minute and a pressure of 17Kg/cm 2 for 60 minutes. Comparative Example 1 Using the same varnish and glass cloth as Example 1
It was dried at 152°C for 6 minutes to produce a prepreg with a minimum melt viscosity of 400 poise at 130°C. Hereinafter, by using the same material composition as in Example 1, the temperature
A high-density multilayer printed circuit board was obtained by thermocompression molding under the conditions of 130°C for 15 minutes + 170°C for 60 minutes and a pressure of 25 kg/cm 2 . Comparative Example 2 Using the same varnish and glass cloth as Example 1,
A prepreg having a minimum melt viscosity of 100 poise at 130°C was produced by drying at 143°C for 6 minutes. Using this prepreg, thermocompression molding was performed using the same configuration as in Example 2 at a heating rate of 4 to 6 degrees Celsius per minute from room temperature to 170 degrees Celsius, holding at 170 degrees Celsius for 60 minutes, and a pressure of 40 kg/cm 2 to achieve high density. A multilayer printed circuit board was obtained. Comparative Example 3 Using the same varnish and glass cloth as Example 1,
A prepreg having a minimum melt viscosity of 360 poise at 130°C was produced by drying at 151°C for 6 minutes.
Using this prepreg, a high-density multilayer printed circuit board was obtained using the same material composition as in Example 2 and the same molding conditions as in Comparative Example 2. Regarding the high-density multilayer printed circuit boards obtained in the above Examples and Comparative Examples, the expansion/contraction ratio of each layer, interlayer thickness, and presence or absence of voids before and after molding were actually measured, and the results are shown in the table below.
The measurement method for the stretch rate of each layer is approximately 430% for each layer pattern.
Base point marks were placed at mm intervals, and a mold release agent was applied in advance around the marks so that they could be easily scraped out after molding, and the dimensional change in the base point mark spacing before and after thermocompression bonding was determined.
【表】
以上の比較により、実施例では平均変化率が小
さくなつたのみならず、縦、横の異方性が短縮さ
れている。さらに重要なことは変形のばらつき
（標準偏差）が小さくなつていることである。平
均変化率分をあらかじめ回路パターンマスクで補
正するとすれば、標準偏差の大、小が位置ずれ精
度を左右するものであり、実施例では、許容し得
る位置ずれを0.033％としても、99.7％の高い歩
留りで合格できることが認められた。比較例３は
縦、横の平均変化率の差も少なく、ばらつきも比
較的小さいが、ボイドが発生し、接着部分の層間
が厚い。[Table] According to the above comparison, in the examples, not only the average rate of change was reduced, but also the vertical and horizontal anisotropy was shortened. What is more important is that the variation in deformation (standard deviation) is becoming smaller. If the average rate of change is corrected in advance using a circuit pattern mask, the size of the standard deviation will affect the positional deviation accuracy. It was recognized that the test could be passed with a high yield. In Comparative Example 3, there is little difference in the average rate of change in the vertical and horizontal directions, and the variation is also relatively small, but voids occur and the interlayers in the bonded portion are thick.
図は本発明の一実施例を示す製造フロー図であ
る。
１……絶縁基板、２……接着用プリプレグ、３
……銅箔、４，５，６……エツチングによつて回
路パターンが形成された後の印刷回路基板。
The figure is a manufacturing flow diagram showing one embodiment of the present invention. 1... Insulating substrate, 2... Adhesive prepreg, 3
...Copper foil, 4,5,6...Printed circuit board after a circuit pattern has been formed by etching.
Claims (1)
圧着成形する多層印刷回路板の製造方法におい
て、接着シートとして、含浸されている半硬化レ
ジンの130℃における溶融粘度の最低値が30〜300
ポイズを示すプリプレグを用い、かつ、成形圧力
が20Kg/cm2以下の圧力範囲で熱圧着成形すること
を特徴とする多層印刷回路板の製造方法。 ２ 接着シートが半硬化レジンとガラスクロスか
ら成ることを特徴とする特許請求の範囲第１項記
載の多層印刷回路板の製造方法。 ３ 半硬化レジンがブロム化ビスフエノール系エ
ポキシレジンであることを特徴とする特許請求の
範囲第１項記載の多層印刷回路板の製造方法。[Claims] 1. In a method for manufacturing a multilayer printed circuit board in which a plurality of printed circuit boards are thermocompression molded via an adhesive sheet, the melt viscosity at 130°C of a semi-cured resin impregnated as the adhesive sheet is Minimum value is 30-300
1. A method for producing a multilayer printed circuit board, characterized by using prepreg exhibiting poise and carrying out thermocompression molding at a molding pressure of 20 kg/cm 2 or less. 2. The method for manufacturing a multilayer printed circuit board according to claim 1, wherein the adhesive sheet is made of semi-cured resin and glass cloth. 3. The method for manufacturing a multilayer printed circuit board according to claim 1, wherein the semi-cured resin is a brominated bisphenol epoxy resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7210178A JPS54163359A (en) | 1978-06-16 | 1978-06-16 | Method of producing multiilayer printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7210178A JPS54163359A (en) | 1978-06-16 | 1978-06-16 | Method of producing multiilayer printed circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS54163359A JPS54163359A (en) | 1979-12-25 |
| JPS6147000B2 true JPS6147000B2 (en) | 1986-10-16 |
Family
ID=13479670
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7210178A Granted JPS54163359A (en) | 1978-06-16 | 1978-06-16 | Method of producing multiilayer printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS54163359A (en) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5710294A (en) * | 1980-06-23 | 1982-01-19 | Furukawa Electric Co Ltd | Method of producing flexible printed circuit board |
| JPS58140193A (en) * | 1982-02-16 | 1983-08-19 | 富士通株式会社 | High density multilayer printed board |
| JPS5948996A (en) * | 1982-09-13 | 1984-03-21 | 日本電気株式会社 | Multilayer printed circuit board and method of producing same |
| JPS59187170U (en) * | 1983-05-30 | 1984-12-12 | 日本メクトロン株式会社 | multilayer circuit board |
| JPS6390897A (en) * | 1986-10-03 | 1988-04-21 | 松下電工株式会社 | Manufacture of multilayer interconnection board |
| JP2509885B2 (en) * | 1987-06-26 | 1996-06-26 | 東芝ケミカル株式会社 | Multilayer copper clad laminate |
| JPS6480524A (en) * | 1987-09-24 | 1989-03-27 | Matsushita Electric Works Ltd | Multi-layer printed wiring board |
| JPH01244849A (en) * | 1988-03-28 | 1989-09-29 | Matsushita Electric Works Ltd | Manufacture of electric laminate |
| JPH0397297A (en) * | 1989-09-11 | 1991-04-23 | Toshiba Chem Corp | Multilayered copper-plated laminated board and its manufacture |
| JP2533689B2 (en) * | 1990-12-14 | 1996-09-11 | 松下電工株式会社 | Method for manufacturing multilayer circuit board |
| JPH07109940B2 (en) * | 1990-12-14 | 1995-11-22 | 松下電工株式会社 | Method for manufacturing multilayer circuit board |
| JP2841996B2 (en) * | 1992-01-13 | 1998-12-24 | 日立化成工業株式会社 | Manufacturing method of rigid flex wiring board |
| JP2001277273A (en) * | 2000-03-29 | 2001-10-09 | Sumitomo Bakelite Co Ltd | Method for manufacturing laminated sheet |
| JP2010040592A (en) * | 2008-07-31 | 2010-02-18 | Kyocer Slc Technologies Corp | Manufacturing method of wiring board |
| EP2370773B1 (en) | 2008-12-17 | 2016-04-06 | SWEP International AB | Reinforced heat exchanger |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49125844A (en) * | 1973-04-06 | 1974-12-02 | ||
| JPS50133457A (en) * | 1974-04-15 | 1975-10-22 | ||
| JPS50145861A (en) * | 1974-05-14 | 1975-11-22 | ||
| JPS5155953A (en) * | 1974-11-11 | 1976-05-17 | Hitachi Ltd | KANTSUSETSUZOKUKONAIGA JUTEN SARETA TASOPURINTOKAIROBANTOSONO SEIHO |
| JPS5187770A (en) * | 1975-01-31 | 1976-07-31 | Matsushita Electric Works Ltd | TASOPURINTOHAISENBANNO SEIZOHO |
-
1978
- 1978-06-16 JP JP7210178A patent/JPS54163359A/en active Granted
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49125844A (en) * | 1973-04-06 | 1974-12-02 | ||
| JPS50133457A (en) * | 1974-04-15 | 1975-10-22 | ||
| JPS50145861A (en) * | 1974-05-14 | 1975-11-22 | ||
| JPS5155953A (en) * | 1974-11-11 | 1976-05-17 | Hitachi Ltd | KANTSUSETSUZOKUKONAIGA JUTEN SARETA TASOPURINTOKAIROBANTOSONO SEIHO |
| JPS5187770A (en) * | 1975-01-31 | 1976-07-31 | Matsushita Electric Works Ltd | TASOPURINTOHAISENBANNO SEIZOHO |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS54163359A (en) | 1979-12-25 |
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