JPS6144834U - 時計用回路基板の実装構造 - Google Patents

時計用回路基板の実装構造

Info

Publication number
JPS6144834U
JPS6144834U JP1984128356U JP12835684U JPS6144834U JP S6144834 U JPS6144834 U JP S6144834U JP 1984128356 U JP1984128356 U JP 1984128356U JP 12835684 U JP12835684 U JP 12835684U JP S6144834 U JPS6144834 U JP S6144834U
Authority
JP
Japan
Prior art keywords
circuit board
mounting structure
watches
watch
top layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1984128356U
Other languages
English (en)
Inventor
広重 池野
Original Assignee
セイコーインスツルメンツ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by セイコーインスツルメンツ株式会社 filed Critical セイコーインスツルメンツ株式会社
Priority to JP1984128356U priority Critical patent/JPS6144834U/ja
Publication of JPS6144834U publication Critical patent/JPS6144834U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • H10W72/07541Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07551Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/5363Shapes of wire connectors the connected ends being wedge-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Manufacturing Of Printed Wiring (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
図面は本考案の一実施例を示す断面図である。 1・・・・・・回路基板、2・・・・・・配線パタ〒ン
、3・・曲銅めつき、4・・・・・・高純度パラジウム
めっき、5・・・・・・部分金めつき、6・・・・・・
IC, 7・・・・・・ボンディングワイヤ、8・・・
・・・エポキシ樹脂封止。

Claims (1)

    【実用新案登録請求の範囲】
  1. 時計用回路基板の実装構造において、回路基板へのIC
    の実装に係る部分の最上層には金めつきがなされ、その
    他の部分はパラジウムめっきを最上層とする回路基板上
    にICをグイボンデイングし、ワイヤボンデイングにて
    回路接続を行ない、IC封止を行なったことを特徴とす
    る時計用回路基板の実装構造。
JP1984128356U 1984-08-24 1984-08-24 時計用回路基板の実装構造 Pending JPS6144834U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984128356U JPS6144834U (ja) 1984-08-24 1984-08-24 時計用回路基板の実装構造

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984128356U JPS6144834U (ja) 1984-08-24 1984-08-24 時計用回路基板の実装構造

Publications (1)

Publication Number Publication Date
JPS6144834U true JPS6144834U (ja) 1986-03-25

Family

ID=30686986

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984128356U Pending JPS6144834U (ja) 1984-08-24 1984-08-24 時計用回路基板の実装構造

Country Status (1)

Country Link
JP (1) JPS6144834U (ja)

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