JPS6134179B2 - - Google Patents
Info
- Publication number
- JPS6134179B2 JPS6134179B2 JP2067281A JP2067281A JPS6134179B2 JP S6134179 B2 JPS6134179 B2 JP S6134179B2 JP 2067281 A JP2067281 A JP 2067281A JP 2067281 A JP2067281 A JP 2067281A JP S6134179 B2 JPS6134179 B2 JP S6134179B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- rom
- data
- output
- parity check
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000010586 diagram Methods 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 3
- 230000007257 malfunction Effects 0.000 description 3
- 101150065817 ROM2 gene Proteins 0.000 description 2
- 101100524639 Toxoplasma gondii ROM3 gene Proteins 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- FFBHFFJDDLITSX-UHFFFAOYSA-N benzyl N-[2-hydroxy-4-(3-oxomorpholin-4-yl)phenyl]carbamate Chemical compound OC1=C(NC(=O)OCC2=CC=CC=C2)C=CC(=C1)N1CCOCC1=O FFBHFFJDDLITSX-UHFFFAOYSA-N 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/74—Masking faults in memories by using spares or by reconfiguring using duplex memories, i.e. using dual copies
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- Hardware Redundancy (AREA)
- Read Only Memory (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Detection And Correction Of Errors (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2067281A JPS57135496A (en) | 1981-02-14 | 1981-02-14 | P-rom compensating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2067281A JPS57135496A (en) | 1981-02-14 | 1981-02-14 | P-rom compensating circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57135496A JPS57135496A (en) | 1982-08-21 |
| JPS6134179B2 true JPS6134179B2 (enrdf_load_html_response) | 1986-08-06 |
Family
ID=12033684
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2067281A Granted JPS57135496A (en) | 1981-02-14 | 1981-02-14 | P-rom compensating circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57135496A (enrdf_load_html_response) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4962060B2 (ja) * | 2007-03-14 | 2012-06-27 | 富士通セミコンダクター株式会社 | パリティエラー復旧回路 |
| JP5641566B2 (ja) * | 2010-11-25 | 2014-12-17 | Ｎｅｃプラットフォームズ株式会社 | 半導体集積回路装置、制御記憶装置の制御方法及びプログラム |
-
1981
- 1981-02-14 JP JP2067281A patent/JPS57135496A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57135496A (en) | 1982-08-21 |
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