JPS61290757A - Semiconductor device - Google Patents

Abstract

PURPOSE:To adjust a resistance value finely without increasing the areas of patterns by forming the pattern for a second resistor using a conductor layer having low sheet resistance onto the pattern for a first resistor shaped by employing a first conductor layer through an insulating layer. CONSTITUTION:A second resistor 2 formed by a second conductor layer is shaped onto a pattern for a first resistor 1 formed by a first conductor layer through an inter-layer insulating layer consisting of an silicon oxide film not shown. A layer having small sheet resistance is used as the second conductor layer, and the area of a pattern for the second conductor layer is made approximately the same as or smaller than that of the pattern for the first resistor 1. The first resistor 1 is connected to a wiring A through a contact hole 3 and the second resistor 2 to a wiring C through a contact hole 4. Both resistors 1, 2 are connected by a wiring B through contact holes 5, 6. When utilizing a semiconductor device as a resistor, the wiring A and the wiring B or C are connected to the outside.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device, and particularly to a technique for adjusting the resistance value of a semiconductor device without increasing the pattern area.

[Background technology]

Multilayer conductor layers are generally used in integrated circuits of semiconductor devices and the like. For example, Guinamik RAM (
In D-RAM), the electrode of the storage capacitor of the memory cell is formed from a polysilicon layer which is the first conductor layer, and the gate electrode is formed from the polysilicon layer which is the second conductor layer. Here, the second polysilicon layer is usually made of silicide, which has a relatively lower sheet resistance than the first polysilicon layer. (For example, see VLSI Device Handbook, Part I, Chapter 1, 1), 291-p., 305.) By the way, it is conceivable to form the resistor required in the circuit from the first layer of polysilicon. for example,
In the D-RAM, the sense amplifier drive signal is passed through the delay stage using the resistor to the column data line I10+11.
It is conceivable to obtain a connection signal. Data on the data line is sensed during a sensing period determined by the timing of the sense amplifier drive signal and the timing of the column data line/I10 line connection signal. This sensing period is determined by a delay stage, and the first layer of polysilicon is used as a delay resistor of this delay stage.

Data on the data line is sensed during the sense period, but
If this period is too short, read errors may occur. For this reason, there may be cases where it is desired to lengthen this sense period by adjusting the resistance, but it is difficult to adjust the resistance.

[Purpose of the invention]

The present invention provides a semiconductor device that allows fine adjustment of resistance without increasing the pattern area.

The above and other objects and novel features of the present invention include:
It will be clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, it has a first conductor layer and a second conductor layer having a relatively lower sheet resistance than the first conductor layer, and is placed on the first resistance pattern formed using the first conductor layer with an insulating layer interposed therebetween. A second resistor is formed using the second conductor layer. Then, the resistance value of the first resistor is changed using the second resistor. Since the sheet resistance of the second resistor is relatively small, by connecting this second resistor in series with the first resistor, the resistance value can be finely adjusted, and the pattern area of the resistor can also be increased. do not have.

〔Example〕

An embodiment of the semiconductor device of the present invention will be described below with reference to FIGS. 1 and 2.
This will be explained with reference to the figures.

This embodiment uses column data l10I! from the D-RAM sense amplifier drive signal. ! ! This is an example of application to a delay resistor in a delay stage that delays a connection signal. And this D-R
AM uses a first conductor layer, which is a first layer of polysilicon, as an electrode for the storage capacitor of a memory cell, and a second conductor layer, which is a second layer of polysilicon, as a gate electrode. .

The sheet resistance of the first conductor layer is about 40Ω, and the sheet resistance of the second conductor layer is about several Ω because a low resistance material such as silicide is used.

What is indicated by a pointed edge in FIG. 1 is a first resistor 1 formed of a first conductor layer. - The first resistance l formed by this first conductor layer is a pattern having a width of, for example, about 5 μm in order to prevent disconnection and the like.

Since the width is relatively wide, the idea of the present invention is to effectively utilize this pattern.

On the pattern of the first resistor 1, a second resistor 2 made of a second conductor layer indicated by a dashed line is formed via an interlayer insulating layer of silicon oxide film (not shown). The pattern area of this second resistor 2 is approximately equal to or smaller than the pattern area of the first resistor 1. Therefore, the pattern area of the entire device is not increased.

One end of the first resistor 1 is connected to an aluminum wire via a contact hole 3, and one end of the second resistor 2 is connected to an aluminum wire C via a contact hole 4. Further, the other end of the first resistor l and the other end of the second resistor 2 are commonly connected by an aluminum wiring B through contact holes 5 and 6, respectively.

FIG. 2 shows the connection state of the first resistor 1 and the second resistor 2 shown in FIG. 1, and the same reference numerals are given to the elements corresponding to those in FIG. 1.

For example, if initially only the first resistor 1 between A and 8 was used, in order to increase the resistance value of this first resistor l, the
It is sufficient to use the first and second resistors 1 and 2 between them. Further, fine adjustment can be easily achieved by providing a large number of aluminum lead-out points from the second resistor 2. This is particularly effective for circuit-critical matters such as the aforementioned sense period adjustment.

In this way, the required resistance value can be finely adjusted just by patterning the K and aluminum wiring, and moreover, the resistor pattern area is not increased.

Furthermore, in order to simply obtain a resistance value in a small area, the first resistor 1 is patterned on the diffusion layer resistor, and by connecting both of these resistors in series, a resistance value approximately twice as large can be obtained. If the second resistor 2 having a small sheet resistance is formed on the first resistor 1 as described above, fine adjustment can be made in the same way.

〔effect〕

A first resistor is formed using a first conductor layer, and a second resistor is formed on the first resistor by a second conductor layer having a relatively low sheet resistance. The pattern area of the second resistor is approximately equal to or smaller than the pattern area of the first resistor. In this way, since the second resistor having a smaller resistance value is formed on the first resistor, there is an effect that fine adjustment of the resistance value can be achieved without increasing the pattern area.

Although the invention made by the present inventor has been specifically explained above based on examples, it is to be understood that the present invention is not limited to the above-mentioned examples and can be modified as much as possible without departing from the gist thereof. Not even. For example, it is clear that a case where the sheet resistance of the first conductor layer is relatively lower than that of the second conductor layer also falls within the scope of the present invention.

[Application field]

It can be used when obtaining a larger resistance value with a small pattern area or when fine adjustment of this resistance value is required. Especially D-R
Can be used for AM delay resistance.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the pattern of the first and second resistors of the semiconductor device of the present invention, and FIG. 2 is a diagram showing the connection state of the first and second resistors shown in FIG. 1. . 1... First resistance by the first conductor layer, 2... Second resistance by the second conductor layer, 3, 4, 5.6... Contact hole, A, B, C... Aluminum wiring .

Claims (1)

[Claims] 1. A first conductor layer and a second conductor layer having a relatively lower sheet resistance than the first conductor layer, forming a first resistor using the first conductor layer, and forming a pattern of the first resistor. A second resistor using the second conductor layer having a pattern area approximately equal to or smaller than the pattern area of the first resistor is formed on the upper part via an insulating layer, and the second resistor is A semiconductor device characterized in that the resistance value of the first resistor is finely adjusted by: