JPH0834286B2 - Integrated circuit device - Google Patents
Integrated circuit deviceInfo
- Publication number
- JPH0834286B2 JPH0834286B2 JP61234947A JP23494786A JPH0834286B2 JP H0834286 B2 JPH0834286 B2 JP H0834286B2 JP 61234947 A JP61234947 A JP 61234947A JP 23494786 A JP23494786 A JP 23494786A JP H0834286 B2 JPH0834286 B2 JP H0834286B2
- Authority
- JP
- Japan
- Prior art keywords
- concentration
- region
- integrated circuit
- low
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 239000003990 capacitor Substances 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 8
- 239000004020 conductor Substances 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 239000002699 waste material Substances 0.000 description 2
- 230000002860 competitive effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0744—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common without components of the field effect type
- H01L27/0788—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common without components of the field effect type comprising combinations of diodes or capacitors or resistors
- H01L27/0794—Combinations of capacitors and resistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はMOS集積回路装置、特に負荷抵抗と負荷容量
により構成される遅延素子回路を有するMOS集積回路装
置に関する。The present invention relates to a MOS integrated circuit device, and more particularly to a MOS integrated circuit device having a delay element circuit composed of a load resistance and a load capacitance.
一般にMOS集積回路装置における遅延素子回路は、素
子間を接続する信号ラインの中で、他の信号ラインとの
時間的な競争関係から、意図的にある一つの信号ライン
を遅らせたい場合に使われ、常にある一定の遅延時間を
信号ラインに持たせることを要求され、負荷抵抗と負荷
容量により構成される。従来のMOS集積回路装置の遅延
素子回路の一例として、その構造平面図を第３図に、又
Ｃ−Ｄ線での構造断面図を第４図に示す。Generally, a delay element circuit in a MOS integrated circuit device is used for intentionally delaying one signal line among the signal lines connecting the elements, due to a time competitive relationship with other signal lines. The signal line is always required to have a certain delay time, and is composed of a load resistance and a load capacitance. As an example of a delay element circuit of a conventional MOS integrated circuit device, its structural plan view is shown in FIG. 3 and its structural sectional view taken along the line CD is shown in FIG.
第４図において、負荷抵抗は半導体基板107に高濃度
拡散層108を設け、そこに金属導体との電極部111を作っ
て形成する。又、負荷容量は同じく前記半導体基板107
に低濃度イオン注入層を設け、絶縁膜113をはさむよう
に多結晶シリコン110を設けて形成する。その時、金属
導体との電極部として高濃度拡散層108の上には電極部1
14を、さらに多結晶シリコン110の上には電極部112を設
ける。以上述べたような構成からなる負荷抵抗と負荷容
量の電極部111と112を接続し、組合わせることで遅延素
子回路が形成できる。In FIG. 4, the load resistor is formed by providing the semiconductor substrate 107 with the high-concentration diffusion layer 108 and forming the electrode portion 111 with the metal conductor therein. Also, the load capacitance is the same as the semiconductor substrate 107.
A low-concentration ion-implanted layer is provided on the substrate and polycrystalline silicon 110 is provided so as to sandwich the insulating film 113. At that time, the electrode portion 1 is formed on the high-concentration diffusion layer 108 as an electrode portion with the metal conductor.
14 and an electrode portion 112 on the polycrystalline silicon 110. A delay element circuit can be formed by connecting and combining the electrode portions 111 and 112 of the load resistance and the load capacitance configured as described above.
従来のMOS集積回路装置における遅延素子回路におい
て、前述したように負荷抵抗と負荷容量の構造が異な
り、又設けられる位置も離れてしまうために面積の無駄
が多い。したがって、遅延素子回路を複数個有する場合
は、MOS集積回路装置全体の面積に対する影響は大き
く、チップサイズ縮小化の障害となり大きな欠点であ
る。In the delay element circuit in the conventional MOS integrated circuit device, the structures of the load resistance and the load capacitance are different as described above, and the positions where they are provided are also separated, so that the area is wasted. Therefore, when a plurality of delay element circuits are provided, the effect on the area of the entire MOS integrated circuit device is large, which is an obstacle to reducing the chip size, which is a major drawback.
そこで本発明の目的は、以上の欠点を解決し面積に無
駄のないコンパクトな遅延素子回路を有するMOS集積回
路装置を提供することにある。SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a MOS integrated circuit device having a compact delay element circuit which eliminates the above drawbacks and has a small area.
本発明のMOS集積回路装置は、半導体基板上に低濃度
イオン注入層と高濃度拡散層と多結晶シリコンとを備
え、その組合せとしてまず高濃度拡散層により金属導体
との電極部を作り、さらに絶縁膜をはさむように低濃度
イオン注入層と多結晶シリコンを設けて負荷容量を形成
する。この時に、前記低濃度イオン注入層か多結晶シリ
コンのどちらかの形状を、ある一定の抵抗値が得られる
ように任意に作ることで、負荷抵抗と負荷容量を同時
に、そして同一場所に配置した構造となる。このように
することにより、面積に無駄のないコンパクトな遅延素
子回路が得られる。The MOS integrated circuit device of the present invention comprises a low-concentration ion implantation layer, a high-concentration diffusion layer, and polycrystalline silicon on a semiconductor substrate, and as a combination thereof, first, an electrode portion with a metal conductor is formed by the high-concentration diffusion layer, and further, A low-concentration ion implantation layer and polycrystalline silicon are provided so as to sandwich the insulating film to form a load capacitance. At this time, the shape of either the low-concentration ion-implanted layer or the polycrystalline silicon is arbitrarily made so that a certain resistance value can be obtained, so that the load resistance and the load capacitance are arranged at the same place at the same time. It becomes a structure. By doing so, a compact delay element circuit with no waste of area can be obtained.
以下本発明の詳細を、その実施例につき図面を参照し
て説明する。第１図は、本発明の一実施例のMOS集積回
路装置における遅延素子回路を示す構造平面図である。
第２図は、第１図のＡ−Ｂ線での構造断面図である。第
２図において、半導体基板６に低濃度イオン注入層７を
設け、次に高濃度拡散層11を設けて、負荷容量の金属導
体との電極部12を作る。ここで、従来負荷抵抗は前記高
濃度拡散層11を使っていたが、その変わりとして多結晶
シリコンを使うことにより絶縁濃10をはさむように低濃
度イオン注入層７の上に多結晶シリコン８を設ける。こ
の時、第１図のように多結晶シリコン８は、任意幅で蛇
行させて設ける。このようにすると、負荷抵抗と負荷容
量は、同時に、又同一場所に重ねて配置し、形成するこ
とができ、面積の無駄がなくなる。第１図の素子面積
（Ｘ×Ｙ）と第３図の素子面積（Ｗ×Ｚ）を比較する
と、確実に４割から５割程度の縮小ができる。ここでの
説明では、負荷抵抗として多結晶シリコンを任意の幅及
び形状にしているが、低濃度イオン注入層でも可能であ
る。Hereinafter, the details of the present invention will be described with reference to the drawings with respect to its embodiments. FIG. 1 is a structural plan view showing a delay element circuit in a MOS integrated circuit device according to an embodiment of the present invention.
FIG. 2 is a structural sectional view taken along the line AB of FIG. In FIG. 2, a low-concentration ion implantation layer 7 is provided on a semiconductor substrate 6, and then a high-concentration diffusion layer 11 is provided to form an electrode portion 12 with a metal conductor having a load capacitance. Here, the high-concentration diffusion layer 11 is used for the conventional load resistor, but instead of the high-concentration diffusion layer 11, the polycrystalline silicon 8 is placed on the low-concentration ion implantation layer 7 so as to sandwich the insulating concentration 10. Set up. At this time, as shown in FIG. 1, the polycrystalline silicon 8 is provided so as to meander in an arbitrary width. By doing so, the load resistance and the load capacitance can be arranged and formed at the same time or in the same place, and the area is not wasted. Comparing the element area (X × Y) in FIG. 1 with the element area (W × Z) in FIG. 3, it is possible to surely reduce the size by 40% to 50%. In the description here, polycrystalline silicon has an arbitrary width and shape as the load resistance, but a low concentration ion-implanted layer is also possible.
又、遅延素子回路として限定しているが、実際には負
荷抵抗と負荷容量を組合れた回路ならば、本実施例のよ
うな構造にできる。Further, although the delay element circuit is limited, in actuality, a circuit in which a load resistance and a load capacitance are combined can have a structure as in this embodiment.
以上説明したように本発明は、負荷抵抗と負荷容量を
同時に、又、同一場所に重ねて配置する構造により、面
積の無駄をなくし、コンパクトな遅延素子回路を形成す
ることができるという点で、その効果は非常に大きい。As described above, according to the present invention, the structure in which the load resistance and the load capacitance are arranged at the same time or in the same place so as to overlap each other can eliminate a waste of area and form a compact delay element circuit. The effect is very large.
第１図は本発明のMOS集積回路装置における遅延素子回
路の構造平面図で、第２図は、第１図のＡ−Ｂ線での構
造断面図である。 第３図は、従来の構造平面図で、第４図は、第３図のＣ
−Ｄ線での構造断面図である。 6,107……半導体基板、1,11,101,108……高濃度拡散
層、2,7,102,109……低濃度イオン注入層、3,8,103,110
……多結晶シリコン、10,113……絶縁膜、4,5,9,12,10
4,105,106,111,112,114……金属導体との電極部。1 is a structural plan view of a delay element circuit in a MOS integrated circuit device of the present invention, and FIG. 2 is a structural sectional view taken along the line AB of FIG. FIG. 3 is a plan view of a conventional structure, and FIG. 4 is a C of FIG.
It is a structure sectional view in the -D line. 6,107 …… Semiconductor substrate, 1,11,101,108 …… High concentration diffusion layer, 2,7,102,109 …… Low concentration ion implantation layer, 3,8,103,110
...... Polycrystalline silicon, 10,113 …… Insulation film, 4,5,9,12,10
4,105,106,111,112,114 …… Metal conductor and electrode part.
フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 27/06 Ｈ０１Ｌ 27/06 １０２ Ａ Continuation of the front page (51) Int.Cl. 6 Identification number Reference number within the agency FI Technical display area H01L 27/06 H01L 27/06 102 A
Claims (1)
度領域と、この低濃度領域上に絶縁膜を介して形成され
た抵抗領域とを有し、前記低濃度領域の一辺およびこれ
と対抗する辺にそって容量部の電極取り出しとなる高濃
度領域が形成され、前記抵抗領域の一端側に接続される
第１の端子と他端側に接続される第２の端子とを前記低
濃度領域の前記一辺および前記対抗する辺によってはさ
まれた辺と同一方向に取り出されるように配置し、対抗
する２つの前記高濃度領域を前記第１の端子および第２
の端子とが取り出される側の辺とは反対なる辺にそって
導電層で接続した事を特徴とする半導体装置。1. A low-concentration region formed in a predetermined region of a semiconductor substrate, and a resistance region formed on the low-concentration region with an insulating film interposed therebetween. A high-concentration region for taking out the electrode of the capacitor portion is formed along the opposing side, and a first terminal connected to one end side of the resistance region and a second terminal connected to the other end side of the resistance region are connected to the low-concentration region. The two high-concentration regions facing each other are arranged so as to be taken out in the same direction as the side sandwiched by the one side of the concentration region and the opposing side, and the two high-concentration regions opposing each other are provided in the first terminal and the second terminal.
A semiconductor device characterized in that it is connected by a conductive layer along a side opposite to a side on which the terminal of and is taken out.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61234947A JPH0834286B2 (en) | 1986-10-01 | 1986-10-01 | Integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61234947A JPH0834286B2 (en) | 1986-10-01 | 1986-10-01 | Integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6388855A JPS6388855A (en) | 1988-04-19 |
| JPH0834286B2 true JPH0834286B2 (en) | 1996-03-29 |
Family
ID=16978753
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61234947A Expired - Fee Related JPH0834286B2 (en) | 1986-10-01 | 1986-10-01 | Integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0834286B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5514612A (en) * | 1993-03-03 | 1996-05-07 | California Micro Devices, Inc. | Method of making a semiconductor device with integrated RC network and schottky diode |
| US5801065A (en) * | 1994-02-03 | 1998-09-01 | Universal Semiconductor, Inc. | Structure and fabrication of semiconductor device having merged resistive/capacitive plate and/or surface layer that provides ESD protection |
| JP2874550B2 (en) * | 1994-04-21 | 1999-03-24 | 日本電気株式会社 | Semiconductor integrated circuit device |
| KR20010059450A (en) * | 1999-12-30 | 2001-07-06 | 박종섭 | Layout delay of semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5329792B2 (en) * | 1972-08-24 | 1978-08-23 | ||
| JPS5924545B2 (en) * | 1974-09-10 | 1984-06-09 | 日本電気株式会社 | semiconductor equipment |
-
1986
- 1986-10-01 JP JP61234947A patent/JPH0834286B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6388855A (en) | 1988-04-19 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |