JPH01185966A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce capacitance in a digit line and eliminate any delay of the digit line at a remote end of the same by forming a word line as short as possible and wiring no digit line on a gate electrode of a driving MOS transistor, and making shorter the digit line than the word line. CONSTITUTION:There are arranged a plurality of memory cell 1 regions, which are connected to each other through a word line 2 and digit lines 3, 4, 3', 4'. That is, gate electrodes 6 of transfer MOS transistors T1, T2 are connected to the word line 2 at a contact 11 and respective diffusion layers of transfer MOS transistors T2, T4 are connected to the digit lines 3, 4 at contacts 12, 13, respectively, In one memory cell 1, the digit lines 3, 4 are formed shorter than the length of the word line 2, and are prevented from passing the gate electrodes 7, 8 of the driving transistors T3, T4. Hereby, capacitance between the digit lines 3, 3' are reduced, thus eliminating any delay of a signal at a remote end of the digit lines which might be caused by the capacitance and large-sized driving transistors T3, T4.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device having a static type memory cell.

[Conventional technology]

Generally, in a static type memory device, transfer MOS transistors T+, Tz
A memory cell 31 is constituted by the drive MOS transistors T3 and T4, and load resistors R and R. The gates of the transfer MO3I-transistors T+ and Tz are connected to the word line 32, and one of the sources and drains is connected to the digit lines 33.about.34.

FIG. 4 shows the layout pattern, and the same parts as in FIG. 3 are given the same reference numerals.

Note that here, the word line 32 is made of polycrystalline silicon integrally with the gate electrodes of the transfer MOS transistors T, , T, and the digit lines 33 and 34 are made of aluminum wiring.

In the figure, 35 is the boundary between the field oxide film and the diffusion layer region, and 37 and 38 are the driving MOs made of polycrystalline silicon.
S transistor T s , gate electrode of T 4, 3
9.40 is the transfer MOS transistor T z , T
A contact 41.42 connects the diffusion layer of 1 to the gate electrode 38.37, and a contact 41.42 connects the diffusion layer of the transfer MOS transistor T, :T to the digit line 33.34. Although the load resistor R in FIG. 3 is omitted in FIG. 4, polycrystalline silicon for the load resistor is usually formed and patterned after contacts 39 and 40 are opened.

[Problem to be solved by the invention]

In the conventional semiconductor memory device described above, the word line 32 is made of polycrystalline silicon and the digit lines 33 and 34 are made of aluminum, as shown in FIG. For this reason, the resistance of the word line 32 increases as it reaches the far end, causing a considerable signal delay. For this reason, the conventional standard is to design memory cells so that the word lines are short.However, Nikkei Electronics (19833, 9,
As reported in [26], if the memory cell word division method shown in Figure 5 is used, the length of the activated word line can be shortened, and the problem of word line delay can be solved. has been done.

On the other hand, since the digit lines 33 and 34 are made of aluminum, the influence of delay due to wiring resistance is small, but with the recent increase in memory capacity, the number of memory cells connected to one digit line has increased from 512 to When the number of digit lines increases to 1024, the capacitance in the wiring increases, and a delay at the far end of the digit line due to this capacitance becomes a problem. In particular, as can be seen from the layout pattern in FIG. 4, in the past, the digit lines 34 and 33 were extended over the respective gate electrodes 37 and 38 of the drive MOS transistors T s and T a; As shown in a), this includes factors that make the digit line capacity relatively large.

Furthermore, this increase in capacitance requires a large-sized transistor for driving, resulting in an increase in chip size.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device that reduces capacitance in a digit line, eliminates delays at the far end, and enables miniaturization of driving transistors.

[Means to solve the problem]

In the semiconductor memory device of the present invention, the word line connected to the static type memory cell is formed as short as possible, and the digit line connected to the memory cell is similarly connected to the driving M
It is not disposed on the gate electrode of the OS transistor and is made shorter than the length of the word line.

[Function] In the semiconductor memory device having the above configuration, the digit line is short and is not disposed on the gate electrode of the driving MOS transistor, so that the capacitance in the digit line is reduced and the capacitance at the far end is reduced. This eliminates the delay in time and the increase in the size of the drive transistor.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a layout pattern diagram of a first embodiment of the present invention. In the figure, reference numeral 1 indicates one unit area of memory cells, and a plurality of memory cell areas are arranged, and these are connected to word lines 2. The configuration is such that they are connected by digit lines 3°4 (3', 4').

Here, an example is shown in which the word line 2 is shared by two memory cells.

Here, transfer MOS) transistors T, , T.

The driving MOS transistors T, T4 are shown by the boundary 5 between the diffusion layer and the field oxide film, and the gate electrode 6 of the transferred MOS transistor and each driving MOS transistor
Gate electrodes 7 and 8 of the OS transistors are each made of polycrystalline silicon.

A load resistor R (not shown) is connected to the connection contact 10.9 between the gate electrode 7.8 of the driving MOS transistors T, , T and the diffusion layer of the transfer MOS transistor T, , T. I'm letting you do it.

Further, the word line 2 is formed of low resistance wiring such as tungsten silicide or aluminum, and the digit line 3
．． 4 (3', 4') are similarly formed of aluminum wiring. Then, at the contact 11, a transfer MOS transistor TI is connected.

The gate electrode 6 of T2 and the word line 2 are connected, and the digit line 3.4 and the transfer MOS are connected at the contact 12.13.
) connects each diffusion layer of transistors T, , T,.

As shown in the figure, it does not pass over the driving MOS transistor.

According to this layout pattern, the digit line 3.4 is formed shorter than the length of the word line 2 in one memory cell, and the digit line 3.4 is formed shorter than the length of the driving transistor T1. It does not pass over the gate electrode 7.8 of T. Therefore, its cross-sectional structure becomes as shown in FIG. 6(b), and it is clear that the capacitance in the digit line is reduced in this structure compared to the conventional structure shown in FIG. 6(a).

In FIG. 6, 21 is a semiconductor substrate, 22 is a field oxide film, 23 is a glabellar insulating film, and 24 is a gate oxide film.

FIG. 2 is a layout pattern diagram of a second embodiment of the present invention. In the figure, 2.2' is a low resistance word line made of tungsten silicide or aluminum.
is the Nth word line, 2' indicates the N+1th word line.

Here, digit lines 3.4
This is an example of common use.

This layout pattern also allows digit lines 3.
4 is a driving MOS transistor T3. T.

The digit lines are not extended over the gate electrodes 7.8, and the capacitance in the digit lines can be reduced.

[Effects of the Invention] As explained above, the present invention makes the word line as short as possible, does not dispose the digit line on the gate electrode of the driving MoS transistor, and makes the word line shorter than the length of the word line. The short length reduces the capacitance in the digit line, eliminates delays at the far end of the digit line, and reduces the chip size by eliminating the need for large transistors to drive large capacitance. .

[Brief explanation of the drawing]

FIG. 1 is a layout pattern diagram of the first embodiment of the present invention;
FIG. 2 is a layout pattern diagram of a second embodiment of the present invention.
Figure 3 is a circuit diagram of a static type memory cell, Figure 4 is a conventional layout pattern diagram, Figure 5 is a partial circuit diagram of the word division method, and Figure 6 (a) is a cross section of a memory cell in the conventional structure. FIG. 6(b) is a sectional view of a memory cell in the structure of the present invention. 1.31...Storage cell, 2.2', 32...Word line, 3.3', 4.4', 33.34...Digital line, 5.35...Diffusion layer boundary , 6... MO for transfer
Gate electrode of S transistor, 7, 8, 37, 38...
・Gate electrode of driving MOS transistor, 9, 10° 11.12, 39, 40, 41. 42... Contact, 21... Semiconductor substrate, 22... Field oxide film, 23... Interlayer insulation Film, 24... Gate oxide film, T
,. T2... MO3I-transistor for transfer, T,, T,...
...Drive transistor. Figure 3 Figure 4

Claims (1)

[Claims] 1. Two drive MOS transistors, transfer MO
In a semiconductor memory device in which a static type memory cell is constituted by an S transistor and a load resistor, and these are connected by a word line and a digit line, the word line is formed as short as possible, and the digit line is connected to a driving MO.
A semiconductor memory device characterized in that the word line is not disposed on the gate electrode of the S transistor and is shorter than the length of the word line.