JPH09129753A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a complete CMOS SRAM, whose soft-error resistance is enhanced, by increasing the electric capacitance between a local wiring layer and a gate-electrode wiring layer. SOLUTION: Connecting wiring layers LL1 and LL2, which connect the respective impurity diffused regions of an NMOS driver transistor constituting one inverter and a PMOS load transistor, and gate-electrode wiring layers GL1 and GL2, which connect the gate electrode of the NMOS driver transistor and the gate electrode of the PMOS load transistor, are arranged approximately in parallel. Furthermore, the connecting wiring layer is formed in the wide width, and the gate electrode wiring layer is covered by an insulating layer in this constitution.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to four N-type field effect transistors (hereinafter referred to as NMOS) in one memory cell.
And two P-type field effect transistors (hereinafter, P
Complementar CMOS (complementar) having
y MOS) type SRAM (Static Randam Access Memory)
The present invention relates to a semiconductor device.

[0002]

2. Description of the Related Art A complete CMOS type SRAM has four NMOS transistors and two PMOS transistors in one cell, and the input and output of inverters composed of load transistors and driver transistors are connected to each other. For example, a plane pattern diagram as shown in FIG. 4 is known. An equivalent circuit diagram of this SRAM is shown in FIG.

This SRAM has a PT of a load transistor.
r2 and PTr4 are P-type transistors, and the other four transistors are N-type. Word line WL
, Which form the gate electrodes of the switching transistors STr1 and STr6, and are orthogonal to the bit lines (not shown). The driver transistor DTr3 and the load transistor PTr2 form one inverter, and their gate electrodes are connected by the gate electrode wiring layer GL1. The gate electrode wiring layer GL1 is also connected to the impurity diffusion region DA of the load transistor PTr4 that constitutes the other inverter. Similarly, the driver transistor DTr5 and the load transistor PTr4 form the other inverter, and their gate electrodes are connected by the gate electrode wiring layer GL2.
The gate electrode wiring layer GL2 is also connected to the impurity diffusion region DA of the driver transistor DTr3 forming one inverter.

Further, the impurity diffusion regions of the driver transistor DTr3 and the load transistor PTr2 forming one of the inverters are mutually connected in a local wiring layer (connection wiring layer).
The impurity diffusion regions of the driver transistor DTr5 and the load transistor PTr4, which are connected by LL1 and constitute the other inverter, are connected by the local wiring layer LL2. These local wiring layers LL1 and LL2 are
They are provided substantially parallel to the corresponding gate electrode wiring layers GL1 and GL2.

FIG. 5 is a sectional view taken along line B1-B2 of FIG.
Shown in In this sectional view, the substrate 10 has a PMOS and an NMOS.
A field oxide film 21 for isolating the above is formed, and a conductive layer 31 which is a gate electrode wiring layer GL2 is wired on the field oxide film. An offset insulating film 22 is stacked on the conductive layer, and a side wall 23 is formed on a side portion of a laminated body of the conductive layer 31 and the offset insulating film 22. An interlayer insulating film 25 is formed so as to cover a block composed of these laminated bodies and sidewalls. A contact hole CH reaching the impurity diffusion region of the driver transistor DTr5 is provided in the interlayer insulating film 25, and the contact hole CH is formed in the adhesion layer 32.
It is embedded by, for example, a tungsten burying electrode 33. A wiring layer 34 made of a metal such as aluminum is deposited and connected to the embedded electrode 33, and the embedded electrode 33 and the wiring layer 34 form a local wiring layer LL2. .

[0006]

However, the above S
In the RAM, since the overlap between the local wiring layers LL1 and LL2 and the gate electrode wiring layers GL1 and GL2 is small, the electric capacity between the storage nodes is relatively small, and therefore the soft error resistance is insufficient. . In order to add this electric capacitance, a wiring layer for a capacitance electrode is separately formed on the local wiring layer via a thin insulating film, so that the capacitance between the storage nodes can be added, but the number of wirings is reduced. The increase causes problems such as an increase in processing difficulty and an increase in the number of steps.

The present invention has been made in view of the above circumstances, and provides a semiconductor device having a complete CMOS type SRAM with improved soft error resistance by increasing the electric capacitance between the local wiring layer and the gate electrode wiring layer. The purpose is to do.

[0008]

In order to achieve the above object, the present invention provides the following semiconductor device. (1) Each memory cell has four N-type field effect transistors and two P-type field effect transistors, and the input and output terminals of the inverters each including a load transistor and a driver transistor are connected to each other. In a semiconductor device, a connection wiring layer that connects impurity diffusion regions of an N-type field effect driver transistor and a P-type field effect load transistor that form one inverter, a gate electrode of the N-type field effect driver transistor, and A gate electrode wiring layer connecting to a gate electrode of a P-type field effect load transistor is wired substantially in parallel, and these connection wiring layer and gate electrode wiring layer overlap each other with an insulating layer interposed therebetween. Semiconductor device. (2) The semiconductor device according to (1), wherein the connection wiring layer is formed wide so as to cover the gate electrode wiring layer. (3) The semiconductor device according to (1), wherein the insulating layer separating the connection wiring layer and the gate electrode wiring layer has a thickness of 10 to 100 nm. (4) The semiconductor device according to (1), wherein the gate electrode wiring layer is connected to an impurity diffusion region of a transistor forming the other inverter.

In the semiconductor device of the present invention, the local wiring layer (connection wiring layer) and the gate electrode wiring layer are wired substantially parallel to each other, and the local wiring layer and the gate electrode wiring layer are preferably overlapped with each other through the insulating layer. It has a structure in which the layer is formed wide to cover the gate electrode wiring layer.

As a result, the overlapping area between the local wiring layer and the gate electrode wiring layer can be increased, the electric capacitance between the storage nodes can be increased, and the soft error resistance can be improved. In addition, in terms of cross section, it is preferable to make the insulating layer separating the local wiring layer and the gate electrode wiring layer as thin as possible. Specifically, the insulating layer is set to the above thickness.
As a result, the electric capacity can be further increased, and the soft error resistance is further improved.

In order to realize these structures, it is not necessary to increase the number of wiring layers, so that problems such as increase in processing difficulty and increase in the number of steps do not occur.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be specifically described below. FIG. 1 shows a complete C according to the present invention.
It is a plane pattern diagram showing an example of a MOS type SRAM,
A sectional view taken along the line A1-A2 is shown in FIG. Also,
An equivalent circuit diagram of this SRAM is shown in FIG.

This SRAM has a load transistor PT
r2 and PTr4 are P-type transistors, and the other four transistors are N-type. Word line WL
, Which form the gate electrodes of the switching transistors STr1 and STr6, and are orthogonal to the bit lines (not shown). The driver transistor DTr3 and the load transistor PTr2 form one inverter, and their gate electrodes are connected by the gate electrode wiring layer GL1. The gate electrode wiring layer GL1 is also connected to the impurity diffusion region DA of the load transistor PTr4 that constitutes the other inverter. Similarly, the driver transistor DTr5 and the load transistor PTr4 form the other inverter, and their gate electrodes are connected by the gate electrode wiring layer GL2.
The gate electrode wiring layer GL2 is also connected to the impurity diffusion region DA of the driver transistor DTr3 forming one inverter.

Further, the impurity diffusion regions of the driver transistor DTr3 and the load transistor PTr2 forming one inverter are connected to each other by the local wiring layer LL1, and the impurity diffusion regions of the driver transistor DTr5 and the load transistor PTr4 forming the other inverter are connected. The local interconnection layers LL2 are connected to each other. These local wiring layers LL1 and LL2 are provided substantially parallel to the corresponding gate electrode wiring layers GL1 and GL2.

In the present invention, as shown in FIG. 1, the local wiring layers LL1 and LL2 are formed wide so as to cover the gate electrode wiring layers GL1 and GL2, and the gate electrode wiring layers GL1 and GL2 and the local wirings are formed. Layers LL1, L
The structure is such that the overlapping area of L2 is maximized. This makes it possible to increase the electrical capacitance between the local wiring layer and the gate electrode wiring layer and improve the soft error resistance.

FIG. 3 shows the improvement of this soft error resistance.
One of the inverters in the equivalent circuit diagram will be described. With such an overlap, the gate electrode wiring layer GL1
An electrical capacitance C1 (capacitor) is connected between the and the local wiring layer LL1. When the node n1 is irradiated with α rays when the potential of the node n1 is high, the potential of the node n1 sharply decreases, but the electric charge accumulated in the electric capacitance C1 is discharged and the potential is maintained. To do.
This makes soft errors less likely to occur.

Further, in the above structure, the patterning of the conventional local wiring layer (second conductive layer) may be changed,
It is not necessary to provide another process. Therefore, this structure is
There are no problems such as an increase in the degree of processing difficulty due to an increase in the number of wiring layers and an increase in the number of steps as seen in the prior art.

FIG. 2 is a sectional view taken along line A1-A2 of FIG.
Shown in In this sectional view, the substrate 10 has a PMOS and an NMOS.
A field oxide film 21 for isolating the above is formed, and a conductive layer 31 which is a gate electrode wiring layer GL2 is wired on the field oxide film 21.

An offset insulating film 22 is stacked on the conductive layer 31. In the present invention, the offset insulating film 22 is, for example, the silicon oxide film 22a.
And a silicon nitride film 22b formed thereon. This silicon nitride film 22b functions as an etching stopper layer as described later. It is preferable that the thickness of the offset insulating film 22 composed of these is as thin as possible, and specifically, it is about 10 to 100 nm, preferably about 20 to 50 nm. The offset insulating film 22 can also be formed of, for example, a single layer of silicon nitride film.

These conductive layer 31 and offset insulating film 2
A side wall 23 is formed on the side portion of the laminated body with 2. Further, in the conventional structure, the interlayer insulating film is formed so as to cover the block composed of the conductive layer 31, the offset insulating film 22, and the sidewall 23, but in this structure, not only the connection hole CH but also at least the gate electrode wiring is formed. Layer 31
A tungsten burying electrode 33, for example, is also provided on the top of the adhesive layer 32 made of Ti or its nitride. A wide wiring layer 34 of metal or the like is formed on the embedded electrode 33, and the embedded electrode 33 and the embedded electrode 34 form a local wiring layer LL2. In addition,
It is also possible to configure the local wiring layer LL2 only with the embedded electrode 33 and omit the wiring layer 34.

With such a structure, the distance between the gate electrode wiring layer 31 and the local wiring layer 33 can be reduced as much as possible, and the electric capacity can be increased. Resistance is further improved.
As a step for forming the above structure, at the time of forming the connection hole CH of the local wiring layer, etching is performed by using the silicon nitride film 22b of the offset insulating film 22 formed on the gate electrode wiring 31 layer as an etch stopper, and at least the gate electrode wiring is formed. The portion overlapping the layer 31 is also opened at the same time. Then, after forming the adhesion layer 32, it is possible to adopt a step of filling the connection hole CH and at the same time filling the opening on the gate electrode wiring layer 31 with tungsten.

[0022]

Since the semiconductor device of the present invention has the electric capacitance between the local wiring layer and the gate electrode wiring layer increased as compared with the conventional structure, the soft error resistance is improved.

[Brief description of the drawings]

FIG. 1 is a plan pattern diagram showing an embodiment of a complete CMOS SRAM according to the present invention.

FIG. 2 is a cross-sectional view taken along the line A1-A2 of FIG.

FIG. 3 is an equivalent circuit diagram of the SRAM of FIG.

FIG. 4 is a plan view of a conventional complete CMOS SRAM.

5 is a cross-sectional view taken along line B1-B2 of FIG.

FIG. 6 is a circuit diagram of a complete CMOS SRAM.

[Explanation of symbols]

STr1, STr6 switching transistor DTr3, DTr5 driver transistor PTr2, PTr4 load transistor GL1, GL2 gate electrode wiring layer LL1, LL2 local wiring layer (connection wiring layer) n1, n2 node C1, C2 electrical capacitance (capacitor) DA diffusion layer WL Word line 10 Substrate 21 Field oxide film 31 Gate electrode wiring layer 22 Offset insulating film 33 Buried electrode 34 Wiring layer

Claims (4)

[Claims] 1. A memory cell has four N-type field effect transistors and two P-type field effect transistors, and the input and output of inverters composed of a load transistor and a driver transistor are connected to each other. And a connection wiring layer connecting impurity diffusion regions of an N-type field effect driver transistor and a P-type field effect load transistor that form one inverter, and a gate electrode of the N-type field effect driver transistor. And a gate electrode wiring layer connecting the gate electrode of the P-type field effect load transistor are wired substantially in parallel, and the connection wiring layer and the gate electrode wiring layer overlap each other with an insulating layer interposed therebetween. A semiconductor device characterized by: 2. The semiconductor device according to claim 1, wherein the connection wiring layer is formed wide so as to cover the gate electrode wiring layer. 3. The semiconductor device according to claim 1, wherein the insulating layer separating the connection wiring layer and the gate electrode wiring layer has a thickness of 10 to 100 nm. 4. The semiconductor device according to claim 1, wherein the gate electrode wiring layer is connected to an impurity diffusion region of a transistor forming the other inverter.