JPS61296757A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve the reliability of connecting a semiconductor region to wiring by a method wherein a semiconductor region and the first wiring layer on it, the first wiring layer and the second wiring layer on it are provided, and they are connected through plural connection holes so that the connection holes are not overlapped. CONSTITUTION:A connection hole 13 and a connection hole 15 are arranged substantialy on one line and provided one after another. Thus, the width of a conductive layer 11 at the upper part of a semiconductor region 6 is reduced, improving the degree of integrity of a semiconductor integrated circuit device, Moreover, the conductive layers 11 and 15 are connected electrically favorable, with improved electrical reliability of a semiconductor integrated circuit device.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor integrated circuit device, and in particular to a technique that is effective when applied to a semiconductor integrated circuit device equipped with an MI S FET.

[Background Art] The sheet resistance of the source and drain regions of an MI S FET is as large as about 40 to 50 [Ω/gate]. On the other hand, an aluminum layer having a low sheet resistance of about 75 [mΩ/hole] is used for the wiring of semiconductor integrated circuit devices. Therefore, the present inventor investigated a technique for shunting the source and drain regions using an aluminum layer to reduce their resistance. As a result, the following problems were discovered. In other words, when connecting a second aluminum layer to a semiconductor region shunted by the first aluminum layer, a contact hole is used to connect the semiconductor region shunted with the first aluminum layer.
cannot be formed with high density, which hinders the improvement of the degree of integration.

When connecting holes are formed in a high density, the reliability of the connection between them decreases.

Regarding the technology related to MISFET.

For example, Science Forum, Inc., Very LSI Handbook, November 28, 1980, pages 38-40.
It is described in.

[Object of the Invention] An object of the present invention is to provide a technique for improving the reliability of connection between a semiconductor region and wiring.

Another object of the present invention is to provide a technique that can improve the degree of integration of a semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] A brief outline of one typical invention disclosed in this application is as follows.

That is, a semiconductor region and a first wiring layer thereon are provided, and a first wiring layer and a second wiring layer thereon are provided, and these are connected through a plurality of connection holes, respectively. At this time, the connection holes are made not to overlap each other.

Hereinafter, the configuration of the present invention will be explained along with examples.

In addition, in all the times for explaining the example.

Components having the same function are given the same reference numerals, and repeated explanations will be omitted.

[Example] This example describes an example in which the present invention is applied to a DRAM.

FIG. 1 is a plan view of a MISFET that constitutes a peripheral circuit 1 of a DRAM, for example, a cover sofa.

Region X in FIG. 2 is a cross-sectional view taken along the line ■-■ in FIG. 1, region Y in FIG. 2 is a cross-sectional view of a DRAM memory cell, and FIG. 3 is a cross-sectional view taken along the line ■-■ in FIG. It is a diagram. Note that in FIG. 1, in order to make the configuration of the MISFET easier to see, an insulating film provided between conductive layers is not shown.

As shown in FIGS. 1 to 3, the DRAM of this embodiment is constructed on a semiconductor substrate 1 made of P-type single crystal silicon. Semiconductor elements provided on a semiconductor substrate 1 are electrically isolated by a field insulating film (SiO2 film) 2 and a P+ type channel stopper region 3. The MISFET constituting the output buffer is composed of a gate electrode 4, a gate insulating film 5, and an n+ type semiconductor region 6 as a source and drain region, as shown in region X in FIG. 2 or in FIG. . The gate insulating film 5 is made of a silicon oxide film formed by oxidizing the surface of the semiconductor substrate l.

As shown in region Y of FIG. 2, the MISFET constituting the memory cell has a gate electrode 4. It is composed of a gate insulating film (Si02 film) 5 and n+ type semiconductor regions 6 which are source and drain regions. A capacitive element of a memory cell is composed of an insulating film 7 used as a dielectric, a conductive layer 8 made of polycrystalline silicon used as one electrode, and a semiconductor substrate 1. The gate electrode 4 of the MISFET constituting the memory cell extends within the memory cell array and connects to the word line WL.
becomes.

In this embodiment, the gate electrode 4 is constructed using a polycrystalline silicon layer formed by CVD technology. The gate electrode 4 is made of molybdenum (MO), tungsten (W), titanium (Ti
), or a compound (silicide layer) of the high melting point metal and silicon. Furthermore, the high melting point metal layer or its silicide layer may be provided on the polycrystalline silicon layer.

The insulator [7] serving as the dielectric of the capacitive element is composed of a silicon oxide film formed by oxidizing the surface of the semiconductor substrate 1 and a silicon nitride film formed thereon by CVD. Therefore, although the insulating film 7 and the gate insulating film 5 are formed in a separate process, they are shown as one unit. A polycrystalline silicon layer formed by CVD or the like is used for the conductive layer 8 serving as the electrode of the capacitive element. This conductive layer 8 is covered with an insulating film (SiO2 film) 9 formed by oxidizing its surface.

This is to insulate the upper part from the extending word line WL. Reference numeral 10 denotes an insulating film, which is provided to cover the gate electrode 4.

The first conductive layer 11 shown in region X in FIG. 2 is mainly for reducing the resistance of the semiconductor region 6. The conductive layer 11 is made of an aluminum layer and is connected to the semiconductor region 6 through a connection hole 13 formed in the insulating film 10. The conductive layer 11 is for the data line DL and the MISF of the peripheral circuit.
It is formed in the same process as the signal wiring (not shown) extending in one direction that connects the ETs.

The MISFET shown in FIG. 1 has a plurality of MISFETs connected in parallel in order to increase current capacity and drive capability. This equivalently increases the gate width. lMIS without requiring large area
In order to connect the FETs in parallel, a plurality of gate electrodes 4 are arranged in parallel, and a semiconductor region 6 is formed between them.

The same signal is applied to the gate electrode 4 by the wiring 11 through the connection hole 16 . The two drain (or source) regions 6 are shorted together by the conductive layer 11, and variations in potential within the regions 6 are made negligible (shunted). That is, the large sheet resistance of the drain region 6 can be ignored. The three source (drain) regions 6 are short-circuited to each other by the conductive layer 11, and variations in potential within the regions 6 are made negligible (shunted). As a result, the MISFET shown in FIG.
It can work as

Since the first layer of aluminum wiring is used for effective operation of the MISFET, the second layer of aluminum wiring forms the power supply wiring for the MISFET. That is, the second conductive layer 12 is.

It is made of an aluminum layer and is connected to the conductive layer 11 through a connection hole 15 formed in the insulating film 14. Conductive layer 1
2 is the power supply potential Vcc (for example, 5[:V]) or the circuit ground potential Vss (for example, O[V]) for the MISFET.
]). The conductive layer 12 is used in a peripheral circuit as a signal wiring extending in a direction intersecting the signal wiring made of the conductive layer 11, and is also used as a power supply wiring. Further, the five conductive layers 12 are used in the memory cell array region to reduce the resistance of the word line to increase the speed of writing and reading. Therefore, although not shown, the conductive layer 12 in the memory cell array region is connected to the word line WL through a connection hole. Specifically, the word line WWL is divided into a plurality of lines, and the divided word lines WL are connected by a conductive layer 12 and inputted to a decoder. The conductive layer 11 and the conductive layer 12 are insulated by an insulating film 14.

As shown in FIG. 1, in this embodiment, connection holes 13 and 15
are arranged alternately. This is due to the following reason.

First, for the insulating films 10 and 14, a silicon oxide film, a phosphosilicate glass (PSG) film, or the like is used to capture unnecessary ions such as sodium. Such an insulating film is formed by CVD, sputtering, or the like. However, the insulating film 10 tends to be thickly formed in the recessed portion of the semiconductor substrate 1 between the parallel gate electrodes 4 and the like. The same is true for the insulating film 14. Therefore, the combined thickness of the insulating films 10 and 14 is about 1.4 [μm]. 1
At 0, the film thickness becomes even thicker in the recessed portion of the semiconductor substrate 1.

On the other hand, the aluminum layer has poor adhesion at stepped portions such as the connection hole 13 or 15.

Therefore, if the connection holes 13 and 15 are formed so as to overlap, and if an attempt is made to directly connect the conductive layer 12 to the semiconductor region 6 without burying the connection hole 13 with the conductive layer 11, the conductive layer 12 will be disconnected. Resulting in.

However, in this embodiment, since the connection hole 13 is filled with the conductive layer 11, the only connection hole to be filled with the conductive layer 12 is the connection hole 15. Therefore, the reliability of the electrical connection between the conductive layer 12 and the semiconductor region 6 can be improved.

Second, in the connection hole 13, the aluminum layer becomes concave as shown in FIG. Therefore, if the connection hole 15 is formed to overlap the connection hole 13.

Even after etching for forming the contact hole 15, the insulating film 13 remains in the recessed portion of the conductive layer 11 within the contact hole l3. The insulating film 13 remaining in this recess reduces the reliability of the electrical connection between the conductive layer 11 and the conductive layer 15. Therefore, the connection hole 15 is provided offset from the connection hole 13. By doing so, the insulating film 14 is not interposed between the conductive layers 13 and 15, so that the reliability of the electrical connection between the conductive layers 13 and 15 can be improved.

Note that even if the connection holes 13 and 15 are arranged in parallel, the same effect as in this embodiment can be obtained. However, in this case,
The width of the conductive layer 11 must be increased.

The layout area increases.

In this embodiment, as shown in FIG. 1, the connection holes 13 and the connection holes 15 are arranged substantially on the same straight line and are provided alternately. As a result, the width of the conductive layer 11 in the upper part of the semiconductor region 6 is reduced, so that the degree of integration of the semiconductor integrated circuit device can be improved. Further, since the conductive layers 11 and 15 are electrically well connected, the electrical reliability of the semiconductor integrated circuit device can be improved.

Note that it is also possible to form only a desired number of connection holes 15 in a concentrated manner directly below the conductive layer 12, and to form as many connection holes 13 as possible in the portion of the conductive layer 11 where the conductive layer 12 is not provided above. Conceivable.

However, with this arrangement, the current flowing through the semiconductor region 6 directly under the conductive layer 12 must take a detour to the part where the conductive layer 11 is connected. Therefore, the substantial resistance between semiconductor region 6 and conductive layer 12 increases. Therefore, as described above, the connection holes 13 and 15 are arranged alternately to reduce the connection resistance between the semiconductor region 6 and the conductive layer 12.

[Effects] According to the new technology disclosed by the present application, the following effects can be obtained.

(1) By providing a first conductive layer on the semiconductor region of the MISFET and connecting the second conductive layer further above to the semiconductor region of the MISFET through this first conductive layer, the semiconductor region of the MISFET is Since the resistance can be substantially ignored, the MISFET can operate satisfactorily.

(2) According to (1) above, it is possible to increase the operating speed of the peripheral circuit.

(3) Due to (1) above, MI 5 with a large gate width
The FET can operate satisfactorily. Furthermore, even if MISFETs with large gate widths, interconnections therefor, contact holes, etc. are arranged with a high degree of integration, their operation will not be impaired.

(4) Second connection holes for connecting the first conductive layer and the second conductive layer and first connection holes for connecting the second conductive layer and the semiconductor region of the MI S FET are arranged alternately. As a result, no insulating film remains in the first connection hole, so that the electrical connection between the first conductive layer and the second conductive layer and the electrical connection between the second conductive layer and the semiconductor region are improved. Reliability can be improved.

(5) According to (4) above, the width required for the second conductive layer is reduced and the area occupied by the MISFET forming the peripheral circuit on the semiconductor substrate is reduced, so the degree of integration of the semiconductor integrated circuit device can be improved. can.

Although the invention made by the present inventor has been specifically explained above using examples, the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Needless to say.

For example, the present invention can also be applied to a semiconductor integrated circuit device configured on a semi-insulating substrate made of a compound of gallium (Ga) and arsenic (As).

Furthermore, in the embodiment described above, a semiconductor memory device of a type in which word lines WL formed by dividing into a plurality of parts are connected by a second conductive layer has been described. However, the present invention is also effective when applied to a semiconductor device that does not have the second conductive layer in other regions.

Also, instead of N-channel MISFET, P-channel M
Complementary MTS consisting of TSFET or both
The present invention can be applied to FET circuits.

Although the present invention is most effective when applied to a MISFET having a shape like that of the fifth embodiment, it is not particularly limited by the shape of the MISFET.

The first and second conductive layers need not be aluminum layers. The semiconductor region (source, drain region) may be another region 1, such as a gate electrode.

In the present invention, the first conductive layer on the underlying conductive layer is
It can be applied to all cases where a conductive layer and an upper second conductive layer are connected.

[Brief explanation of the drawing]

FIG. 1 shows an MI that constitutes peripheral circuits such as a DRAM decoder and an input/output buffer according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Field insulating film, 3...
. . . Channel stopper region, 4 . . . Gate electrode, 5.
7.9.10.14... Insulating film, 6... Semiconductor region, 8.11.12... Conductive layer, 13.15.16...
・Connection hole. 1/P-2 Figure 1

Claims (1)

[Claims] 1. A semiconductor region provided on a semiconductor substrate, a first wiring layer provided above the semiconductor region extending in the same direction as the extending direction of the semiconductor region, and a first wiring layer provided on the semiconductor substrate; the second provided above
a wiring layer; a plurality of first connection holes for connecting the semiconductor region and the first wiring layer; and a plurality of connection holes for connecting the first wiring layer and the second wiring layer; A semiconductor integrated circuit device in which a first connection hole and a second connection hole are provided so that they do not overlap. 2. The semiconductor integrated circuit device according to claim 1, wherein the first connection hole and the second connection hole are provided alternately on one or more lines. 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein the second connection hole is formed on the semiconductor region. 4. The semiconductor integrated circuit device according to claim 2, wherein the semiconductor region is a part of a MISFET constituting a peripheral circuit of a dynamic random access memory.