JPS61280655A - Semiconductor integrated circuit with incorporated photosensor - Google Patents
Semiconductor integrated circuit with incorporated photosensorInfo
- Publication number
- JPS61280655A JPS61280655A JP60102073A JP10207385A JPS61280655A JP S61280655 A JPS61280655 A JP S61280655A JP 60102073 A JP60102073 A JP 60102073A JP 10207385 A JP10207385 A JP 10207385A JP S61280655 A JPS61280655 A JP S61280655A
- Authority
- JP
- Japan
- Prior art keywords
- photosensor
- impurity concentration
- layer
- substrate
- junction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【発明の詳細な説明】
ビ) 産業上の利用分野
本発明はフォトセンサを内蔵する半導体集積回路、特に
複数の島領域を有する半導体集積回路に内蔵されるフォ
トセンサの改良に関する。DETAILED DESCRIPTION OF THE INVENTION B) Industrial Application Field The present invention relates to a semiconductor integrated circuit incorporating a photosensor, and particularly to an improvement of a photosensor incorporated in a semiconductor integrated circuit having a plurality of island regions.
(ロ) 従来の技術
従来の7オトセンサを内蔵する半導体集積回路は例えば
特開昭59−96765号公報(I(01L27./1
4)に示され℃いる。(b) Conventional technology A semiconductor integrated circuit incorporating a conventional 7-point sensor is disclosed, for example, in Japanese Patent Application Laid-Open No. 59-96765 (I(01L27./1
4) is shown at ℃.
第4図に於いて、0υはP型半導体基板、(社)は基板
シリ上に成長されたN−型のエピタキシャル層、(ハ)
はP 型の分離領域、(財)はエピタキシャル層器表面
に拡散されたP型のアノード領域、(ホ)はN+型のカ
ソード領域であり、アノード領域(財)とカソード領域
(ハ)間のPN接合をフォトダイオードとして利用し℃
いた。In Figure 4, 0υ is a P-type semiconductor substrate, 0υ is an N-type epitaxial layer grown on a silicon substrate, and (c)
is a P-type isolation region, (F) is a P-type anode region diffused on the surface of the epitaxial layer, (E) is an N+-type cathode region, and the area between the anode region (F) and cathode region (C) is Using the PN junction as a photodiode
there was.
P→ 発明が解決しようとする問題点
フォトダイオード、特に赤外線検出用フォトダイオード
は低不純物濃度のPN接合で形成する方が空乏層が拡が
り易く検出出力レベルを大きく取れる。P→ Problems to be Solved by the Invention When a photodiode, especially an infrared detection photodiode, is formed from a PN junction with a low impurity concentration, the depletion layer can expand more easily and the detection output level can be increased.
しかし斯るフォトダイオードは、アノード領域124)
をNPN)ランジスタのペース拡散で形成し、カソード
領域(ハ)をエミッタ拡散で形成しているので、フォト
ダイオードを形成するPN接合は高不純物濃度となる。However, such a photodiode has an anode region 124)
Since the (NPN) transistor is formed by pace diffusion and the cathode region (c) is formed by emitter diffusion, the PN junction forming the photodiode has a high impurity concentration.
このため半導体集積回路に組み込まれるフォトダイオー
ドはその検出出力レベルを大きくできない欠点があった
。For this reason, the photodiode incorporated in the semiconductor integrated circuit has the disadvantage that its detection output level cannot be increased.
に) 問題点を解決するだめの手段
本発明は斯る欠点に鑑み℃なされ、半導体基板(1)表
面に低不純物濃度のイオン注入層(5)を設け℃従来の
欠点を大巾に改善したフォトセンサを内蔵する半導体集
積回路を実現するものである。2) Means to Solve the Problems The present invention has been made in view of these drawbacks, and has greatly improved the drawbacks of the conventional method by providing an ion-implanted layer (5) with a low impurity concentration on the surface of the semiconductor substrate (1). This realizes a semiconductor integrated circuit with a built-in photosensor.
(ホ)作用
本発明に依れば、イオン注入層(5)によりフォトセン
サを構成するPN接合の不純物濃度を低減できるので、
空乏層を広がり易くできフォトセンサの検出出力レベル
を大きくできる。(E) Effect According to the present invention, since the impurity concentration of the PN junction constituting the photosensor can be reduced by the ion implantation layer (5),
The depletion layer can be easily expanded, and the detection output level of the photosensor can be increased.
(へ)実施例
本発明によるフォトセンサを内蔵する半導体集積回路の
一実施例を第1図乃至第3図を参照し℃詳述する。(F) Embodiment An embodiment of a semiconductor integrated circuit incorporating a photosensor according to the present invention will be described in detail with reference to FIGS. 1 to 3.
本発明による半導体集積回路は第1図に示す如く、P型
のシリコン半導体基板(1)と、基板+11上に成長さ
れたN−型のエピタキシャル層(2)と、P+型の分離
領域(3)と、基板(1)と分離領域(3)とで囲まれ
た島領域(4)と、島領域(4)底面の基板(1)表面
に形成されたN″″型のイオン注入層(5)と、基板(
1)で形成されるアノード領域(6)と、イオン注入層
(5)および島領域(4)で形成されるカソード領域(
7)と、島領域(4)表面に設けたN 型のカソードコ
ンタクト領域(8)とで構成され℃いる。As shown in FIG. 1, the semiconductor integrated circuit according to the present invention includes a P type silicon semiconductor substrate (1), an N- type epitaxial layer (2) grown on a substrate +11, and a P+ type isolation region (3). ), an island region (4) surrounded by the substrate (1) and the isolation region (3), and an N''" type ion implantation layer ( 5) and the board (
1), and a cathode region (6) formed by the ion implantation layer (5) and the island region (4).
7) and an N-type cathode contact region (8) provided on the surface of the island region (4).
斯るフォトセンサはイオン注入層(5)および基板(1
)とで形成されるPN接合で形成される。イオン注入層
(5)の不純物濃度は1011−IscrIL′ffi
と半導体基板(1)と同程度に設定され、半導体基板(
1)の不純物濃度も構造上低不純物であるので、不純物
濃度の低いP−I−N構造に近い接合を得られる。Such a photosensor consists of an ion-implanted layer (5) and a substrate (1).
) is formed by a PN junction. The impurity concentration of the ion implantation layer (5) is 1011-IscrIL'ffi
is set to the same level as the semiconductor substrate (1), and the semiconductor substrate (
Since the impurity concentration in 1) is structurally low, a junction close to a P-I-N structure with a low impurity concentration can be obtained.
このフォトセンサはカソードコンタクト領域(8)と基
板(1)間に検出用の抵抗(9)と直流電源α1を接続
し℃使用し、第2図に示す等価回路図を構成する。This photosensor is used with a detection resistor (9) and a DC power supply α1 connected between the cathode contact region (8) and the substrate (1), and is used at 0.degree. C., and an equivalent circuit diagram shown in FIG. 2 is constructed.
フォトセンサに赤外線が照射されると、フォトセンサに
発生結合電流が生じ℃抵抗(9)に電圧降下を生じる。When the photosensor is irradiated with infrared rays, a coupling current is generated in the photosensor, causing a voltage drop across the °C resistor (9).
この電圧降下をアンプaυで増巾して出力信号を得てい
る。This voltage drop is amplified by an amplifier aυ to obtain an output signal.
次に本発明に依る半導体集積回路の製造方法を第3図A
乃至第3図りを参照して詳述する。Next, FIG. 3A shows a method for manufacturing a semiconductor integrated circuit according to the present invention.
This will be explained in detail with reference to the third diagram.
先ず第3図AK示す如く、フォトダイオードな形成する
予定の半導体基板(1)表面にリンをイオン注入して半
導体基板11)と同じ不純物濃度を有するイオン注入層
(5)を形成する。このイオン注入は加速電圧50〜2
00 KeV、)”−スi 10 ”〜10 ”α−2
で行う。First, as shown in FIG. 3A, phosphorus is ion-implanted into the surface of a semiconductor substrate (1) on which a photodiode is to be formed, to form an ion-implanted layer (5) having the same impurity concentration as the semiconductor substrate (11). This ion implantation is carried out at an accelerating voltage of 50~2
00 KeV, )"-su 10"~10"α-2
Do it with
次に第3図Bに示す如く、他の島領域(13となる半導
体基板(1)表面にはN 型の埋め込み層aつを拡散し
、分離領域(3)となる半導体基板11)表面にはP+
型の分離領域(3)の下拡散を行う。Next, as shown in FIG. 3B, one N-type buried layer is diffused on the surface of the semiconductor substrate (1) that will become the other island region (13), and on the surface of the semiconductor substrate 11 that will become the isolation region (3). is P+
Diffusion is performed under the separation area (3) of the mold.
次に第3図Cに示す如く、半導体基板(1)表面にN型
のエピタキシャル層(2)を成長させ、エピタキシャル
層(2)中にも埋め込み層C121と分離領域(3)と
を拡散させる。Next, as shown in FIG. 3C, an N-type epitaxial layer (2) is grown on the surface of the semiconductor substrate (1), and the buried layer C121 and isolation region (3) are diffused into the epitaxial layer (2) as well. .
更に第3図りに示す如く、エピタキシャル層(2)表面
からP 型の分離領域(3)の上拡散をした後、他の島
領域CI3にはペース領域(14)とエミッタ領域a9
とを二重拡散し、フォトダイオードを形成する島領域(
4)にはエミッタ拡散時にカソードコンタクト領域(8
)を拡散する。Further, as shown in the third diagram, after diffusion is performed from the surface of the epitaxial layer (2) onto the P type isolation region (3), a pace region (14) and an emitter region a9 are formed in the other island region CI3.
and the island region forming the photodiode (
4) The cathode contact region (8
) to spread.
以上に詳述した如く、通常の半導体集積回路の製造工程
中に本発明の7オトセンサの製造工程を挿入でき、極め
℃高出力の7オトセンサを得ることができる。As described above in detail, the manufacturing process of the 7-oto sensor of the present invention can be inserted into the manufacturing process of a normal semiconductor integrated circuit, and the 7-oto sensor with an extremely high output can be obtained.
(ト) 発明の効果
本発明に依れば、通常の半導体集積回路内に低不純物濃
度のPN接合を形成してフォトセンサを内蔵するので、
空乏層が拡がり易い出力レベルの大きいフォトセンサを
容易に得られる利点を有する。(G) Effects of the Invention According to the present invention, a photosensor is built in by forming a PN junction with a low impurity concentration in a normal semiconductor integrated circuit.
This has the advantage that a photosensor with a high output level in which the depletion layer can easily expand can be easily obtained.
また本発明では半導体基板t1)およびエピタキシャル
層(2)の不純物濃度を変更しないので、他のトランジ
スタ等の回路素子の特性は全く変らないままで高性能の
フォトセンサを内蔵できる利点を有する。Further, in the present invention, since the impurity concentrations of the semiconductor substrate t1) and the epitaxial layer (2) are not changed, there is an advantage that a high-performance photosensor can be built in while the characteristics of other circuit elements such as transistors remain unchanged.
更に本発明ではフォトセンサを形成するPN接合を半導
体基板(1)表面と深く形成するので、赤外線のみに反
応し極めてSN比が向上する利点を有する。Furthermore, in the present invention, since the PN junction forming the photosensor is formed deep into the surface of the semiconductor substrate (1), it has the advantage that it reacts only to infrared rays and the S/N ratio is extremely improved.
最後に現在の半導体集積回路の製造工程に容易に導入で
き、フォトセンサ内蔵の半導体集積回路を量産できる利
点を有する。Finally, it has the advantage that it can be easily introduced into the current manufacturing process of semiconductor integrated circuits, and that semiconductor integrated circuits with built-in photosensors can be mass-produced.
第1図は本発明に依るフォトセンサを内蔵する半導体集
積回路を説明する断面図、第2図は本発明の等価回路図
、第3図A乃至第3図りは本発明の半導体集積回路の製
造方法を説明する断面図、第4図は従来のフォトセンナ
を説明する断面図である。
主な図番の説明
+11は半導体基板、 (2)はエピタキシャル層、(
3)は分離領域、 (4)は島領域、 (5)はイオン
注入層、 (6)はアノード領域、(7)はカンード領
域である。
出願人 三洋電機株式会社 外1名
代理人 弁理士 佐 野 静 夫
!J 1 図
#12図
第3図C
第3図り
第4図FIG. 1 is a sectional view illustrating a semiconductor integrated circuit incorporating a photosensor according to the present invention, FIG. 2 is an equivalent circuit diagram of the present invention, and FIGS. 3A to 3 are manufacturing of a semiconductor integrated circuit according to the present invention. A sectional view explaining the method, and FIG. 4 is a sectional view illustrating a conventional photosenser. Explanation of main figure numbers +11 is the semiconductor substrate, (2) is the epitaxial layer, (
3) is an isolation region, (4) is an island region, (5) is an ion implantation layer, (6) is an anode region, and (7) is a cando region. Applicant: Sanyo Electric Co., Ltd. and 1 other agent: Shizuo Sano, patent attorney! J 1 Figure #12 Figure 3 Figure C Figure 3 Figure 4
Claims (1)
型のエピタキシャル層と該エピタキシャル層を分離して
形成した複数の島領域とを具備し、1つの該島領域の半
導体基板表面に逆導電型で低不純物濃度のイオン注入層
を設け、該イオン注入層と前記基板とで形成される低不
純物濃度のPN接合をフォトセンサとして用いることを
特徴とするフォトセンサを内蔵する半導体集積回路。(1) A semiconductor substrate comprising a semiconductor substrate of one conductivity type, an epitaxial layer of an opposite conductivity type provided on the substrate, and a plurality of island regions formed by separating the epitaxial layers, and a surface of the semiconductor substrate of one of the island regions. A semiconductor integrated device having a built-in photosensor, characterized in that an ion-implanted layer of opposite conductivity type and with a low impurity concentration is provided in the substrate, and a PN junction with a low impurity concentration formed between the ion-implanted layer and the substrate is used as a photosensor. circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60102073A JPS61280655A (en) | 1985-05-14 | 1985-05-14 | Semiconductor integrated circuit with incorporated photosensor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60102073A JPS61280655A (en) | 1985-05-14 | 1985-05-14 | Semiconductor integrated circuit with incorporated photosensor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61280655A true JPS61280655A (en) | 1986-12-11 |
Family
ID=14317590
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60102073A Pending JPS61280655A (en) | 1985-05-14 | 1985-05-14 | Semiconductor integrated circuit with incorporated photosensor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61280655A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6170750A (en) * | 1984-09-14 | 1986-04-11 | Toshiba Corp | Manufacture of integrated circuit |
-
1985
- 1985-05-14 JP JP60102073A patent/JPS61280655A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6170750A (en) * | 1984-09-14 | 1986-04-11 | Toshiba Corp | Manufacture of integrated circuit |
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