JPS6170750A - Manufacture of integrated circuit - Google Patents
Manufacture of integrated circuitInfo
- Publication number
- JPS6170750A JPS6170750A JP59191800A JP19180084A JPS6170750A JP S6170750 A JPS6170750 A JP S6170750A JP 59191800 A JP59191800 A JP 59191800A JP 19180084 A JP19180084 A JP 19180084A JP S6170750 A JPS6170750 A JP S6170750A
- Authority
- JP
- Japan
- Prior art keywords
- region
- epitaxial layer
- receiving element
- concentration
- impurity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000012535 impurity Substances 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 239000004065 semiconductor Substances 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 16
- 238000002955 isolation Methods 0.000 claims abstract description 10
- 230000004044 response Effects 0.000 claims abstract description 10
- 238000005192 partition Methods 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 abstract description 5
- 230000008569 process Effects 0.000 abstract description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 3
- 239000011574 phosphorus Substances 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 230000004043 responsiveness Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000035945 sensitivity Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 241000272201 Columbiformes Species 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/1443—Devices controlled by radiation with at least one potential jump or surface barrier
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Light Receiving Elements (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は受光素子を有する集積回路の製造方法に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing an integrated circuit having a light receiving element.
第２図に従来のフォトダイオードを有する集積回路の一
例を示す、Ｐ型半導体基板１上にＮ型エピタキシャル層
２が形成されている。そしてこのＮ型エピタキシャル層
２はＰ型アイツレジョン領域３により個々の機能素子ご
とく分離されている。FIG. 2 shows an example of a conventional integrated circuit having a photodiode, in which an N-type epitaxial layer 2 is formed on a P-type semiconductor substrate 1. The N-type epitaxial layer 2 is separated into individual functional elements by a P-type epitaxial region 3.
その分離されたＮ型エピタキシャル層２ａと、基板１と
の間のＰＮ接合を利用したフォトダイオード１０が形成
されている。このフォトダイオード１０Ｋａカソード電
極５ａ、及びアノード電極５ｂが接続されている。A photodiode 10 is formed using a PN junction between the separated N-type epitaxial layer 2a and the substrate 1. This photodiode 10Ka cathode electrode 5a and anode electrode 5b are connected.
そしてこのフォトダイオード１０に隣接するＮ型エピタ
キシャル層２ｂ内にバイポーラトランジスタが形成され
ておシ、このエピタキシャル層２ｂはコレクタとして利
用される。ここで６はペース、エミッタ７及びコレクタ
２ｂに夫々接続された電極である。なおＮ型エピタキシ
ャル層２の電極形成部を除く表面は絶縁膜４で被覆され
ている。A bipolar transistor is formed in the N-type epitaxial layer 2b adjacent to this photodiode 10, and this epitaxial layer 2b is used as a collector. Here, 6 is an electrode connected to the pace, emitter 7, and collector 2b, respectively. Note that the surface of the N-type epitaxial layer 2 except for the electrode forming portion is covered with an insulating film 4.
このような従来の集積回路におけるフォトダイオード１
０の応答性（動作速度）は十分なものではなく、この応
答性の改善（呻作速度の向上）が望まれている。この応
答性はＮ型エピタキシャル層２ａとＰ型半導体基板１と
の接合面における接合容量に依存している。このため応
答性を改善するためには、この接合容ｆ１＆：小さくす
る必要がある。Photodiode 1 in such a conventional integrated circuit
The responsiveness (operating speed) of 0 is not sufficient, and improvement of this responsiveness (improvement of the motion speed) is desired. This responsiveness depends on the junction capacitance at the junction surface between the N-type epitaxial layer 2a and the P-type semiconductor substrate 1. Therefore, in order to improve responsiveness, it is necessary to reduce this junction capacity f1&:.
この接合容ｉｔ小さくする方法として、次の２つの方法
が考えられる。The following two methods can be considered to reduce this junction capacitance.
（１）Ｐ型半導体基板１．！−Ｎ型エピタキシャル層２
ａとの接合面積を小さくする。(1) P-type semiconductor substrate 1. ! -N type epitaxial layer 2
Reduce the bonding area with a.
（２）Ｐ型半導体基板１とＮ型エピタキシャル層２ａの
両方か、またはどちらか一方の不純物濃度を低くする。(2) Lowering the impurity concentration of either or both of the P-type semiconductor substrate 1 and the N-type epitaxial layer 2a.
しかし、前記（１）の方法の場合、このフォトダイオー
ドの受光面積が小さくなり受光感度を減少することにな
り好ましくない。However, in the case of method (1), the light-receiving area of the photodiode becomes smaller, which reduces the light-receiving sensitivity, which is not preferable.
また、ＰＮＮ接合アイソレージノンよる集積回路では半
導体基板を通じての漏れ電流は完全には防止できない九
め、前記（２）の方法の鳩舎、Ｐ型半導体基板１の不純
物濃度を下げるとこの基板１の抵抗値が大きくなシ漏れ
電流による内部電圧降下が大きくなる。従って漏れ電流
の生じた部分における基板内部電位が不必要に高くなシ
近くの素子へ不所望なバイアスを与えその素子を誤動作
させるなどの悪影響を与える。Furthermore, in integrated circuits based on PNN junction isolation, leakage current through the semiconductor substrate cannot be completely prevented. If the resistance value is large, the internal voltage drop due to leakage current will be large. Therefore, the internal potential of the substrate at the portion where the leakage current occurs is unnecessarily high, and an undesired bias is applied to a nearby element, causing an adverse effect such as causing the element to malfunction.
またエピタキシャル層２ａ及び２ｂはその製造過″穆に
おいて共通のＮ型エピタキシャル層２の形成によって得
られるものであり、エピタキシャル！＠２ａの不純物濃
度ギ下げるためにはＮ型エビタ卓シャル層２全体の濃度
を下げなければなちない。In addition, the epitaxial layers 2a and 2b are obtained by forming a common N-type epitaxial layer 2 during their manufacturing process, and in order to lower the impurity concentration of the epitaxial layer 2a, the entire N-type epitaxial layer 2 must be concentration must be reduced.
従ってこのようにすると、集積回路上の他の機能素子１
例えば第２図中のトランジスタのコレクタとなるエピタ
キシャル／Ｐｉ２ｂの抵抗値が大きくなる。そのためエ
ミッタ７−コレクタ２ｂ間の飽和電圧Ｖａｖ、（ＳＥＴ
）が大きくなり増幅率が低下するといった性能悪化が生
じる。Therefore, by doing this, other functional elements 1 on the integrated circuit
For example, the resistance value of the epitaxial layer /Pi2b serving as the collector of the transistor in FIG. 2 increases. Therefore, the saturation voltage Vav between emitter 7 and collector 2b, (SET
) increases, resulting in performance deterioration such as a decrease in amplification factor.
また個別受光素子では、第３図に示すようなＰＩＮフォ
トダイオードがある。Further, as an individual light receiving element, there is a PIN photodiode as shown in FIG.
これはＶＧウェファ１３、つまり高１７Ｊ１１１−Ｎ
基板に低濃度Ｎ’Ｊをエピタキシャル法（気相成長法
）により形成したウェファを用いて、その低濃度Ｎ一層
の上に２層１４を形成したＰＩＮ接合型のフォトダイオ
ードである。しかし、 このようなりＧウェファを集積
回路の製造に適用することは一般に不可能であシ、これ
までにこのようなＰＩＮ接合型のフォトダイオードを内
蔵した集積回路は実現していない。This is VG wafer 13, that is, height 17J111-N
This is a PIN junction type photodiode in which a wafer in which a low concentration N'J is formed on a substrate by an epitaxial method (vapor phase growth method) is used, and two layers 14 are formed on one layer of the low concentration N. However, it is generally impossible to apply such a G wafer to the manufacture of integrated circuits, and no integrated circuit incorporating such a PIN junction type photodiode has been realized to date.
本発明は上記従来の問題点を解決し、フォトダイオード
の受光感度を減少すること々く、かつ他の素子部の特性
が悪化することなく、フォトダイオードの応答性（動作
速Ｖ）を向上させる集積回路の展進方法を提供すること
を目的とする。The present invention solves the above conventional problems and improves the responsiveness (operating speed V) of the photodiode without reducing the light receiving sensitivity of the photodiode and without deteriorating the characteristics of other element parts. The purpose is to provide a method for advancing integrated circuits.
本発明は上記目的を達成するための、第１導電型半導体
基板の受光素子形成予定領域に、低濃度不純物領域を形
成する工程と、前記予定領域を含む半導体基板表面に第
２４電型エピタキシヤル層を形成する工程と、前記予定
領域を囲んで前記低１度不純物領域に到達して前記エピ
タキシャル層のうち受光素子用の第１エピタキシャル層
を区画する第１アイソレージ百ン領域及び、前記基板に
到達して他の機能素子用の第２エピタキシャル層を区画
する＠２アイソレーシッン領域を形成する工程とを具備
し、前記第１エピタキシャル層と前記低濃度不純物領域
との間のＰＮ接合を用いて形成される受光素子がこの不
純物領域の不純物濃度に依存してその応答速度がコント
ロールされていることを特徴とする集積回路の製造方法
である。In order to achieve the above object, the present invention includes a step of forming a low concentration impurity region in a region of a first conductivity type semiconductor substrate where a light receiving element is to be formed, and a step of forming a 24th conductivity type epitaxial layer on the surface of the semiconductor substrate including the said region. a first isolation region that surrounds the predetermined region and reaches the low-degree impurity region to define a first epitaxial layer for a light-receiving element in the epitaxial layer; forming an @2 isolating region that reaches and defines a second epitaxial layer for another functional element, using a PN junction between the first epitaxial layer and the low concentration impurity region. This method of manufacturing an integrated circuit is characterized in that the response speed of the light-receiving element is controlled depending on the impurity concentration of the impurity region.
本発明の一実施例ｔ−第１図を用いて説明する。 An embodiment of the present invention will be described with reference to FIG.
：ｇ１工穆、Ｐ型半導体基板（第１導を型半導体基板）
ｌの受光素子形成予定領域にＮ型不純物（リン）を、こ
の基板の不純物濃度より低ｅ４度にイオ、 ン注入し
Ｐ−ＩＮ （低濃度不純物領域）９を形成する。:g1 process, P type semiconductor substrate (first conductor type semiconductor substrate)
An N-type impurity (phosphorus) is ion-implanted into the region where the light receiving element is to be formed at a temperature lower than the impurity concentration of this substrate by 4 degrees to form a P-IN (low concentration impurity region) 9.
（第１図ａ参照）
第２工穆、該基板ｌの他の機能素子形成予定領域にＮ型
不純物（リン）を拡散させＮ＋埋込層１１をよ＃）Ｎ型
エピタキシャル層２を形成する。（第１図す参照）
第３工程、Ｎ型エピタキシャル層２にＳｉＯ□絶縁膜４
ｔ−マスクとして用い、Ｐ型不純物の熱選択拡散により
アイソレージ冒ン領域３を形成し、このＮ型エピタキシ
ャル層２を島状のエピタキシャル層成されている。この
分離されたＮ型エピタキシャル層２ａと該Ｆ″層９とで
受光素子のＰＮ接合が形 −成される。ここで受光素子
１０を囲むアイソレーシヲン領域３ｅを第１アイソレー
シヨン領域とし他の機能素子を区画する領域３ｆを第２
フイソレーシ・・領域とする。（第ｉ図？参照）第４工
程、分離され７ｊＮ型工ピタキシヤル層２ｂに他の機能
素子を形成する５本実施例ではエピタキシャル層２ａに
は受光素子（フォトダイオード）１０が形成され、エピ
タキシャル層２ ｂ Ｋ ハト５ンジスタ１５が形成さ
れる。このトランジスタ１５はエピタキシャルＱ２ｂ’
（５コレクタ用として用い、このＩＦｉ ２ ｂに順次
ペース拡散及びエミッタ歴数を始して２層（ペース領域
）６．Ｎ層（エミッタ領域）７を形成することにより得
られる。その後各り子に対する電極が形成される。そし
て５ａ及び５ｂは受光素子（フォトダイオード）１０１
５ダ
のカソード電入及びアノード電極であり、Ｙ亘トランジ
スタのエミッタ、ペース、コレクタ電極、４はＳ ｉ
０２絶縁膜全それぞれ示している。（第１図ｄ珍胆）
このよう（でして製造された受光素子内蔵集積回路に、
Ｈ−いてＩ寸ズ極５ ａ、５ ｂ間に逆電圧を印加する
とＮ ＱエピタキシャルＩ？４２ａとＰ−［９とのＰＮ
接合面付近で空乏層が発生する。そしてＰ−Ｐ２ＯがＰ
型半導体共析に叱し低γζｉ度のため、この空乏層は従
来より浄く形成される。このため受光素子ｌ。(See FIG. 1a) Second step: Diffuse N-type impurity (phosphorus) into the region where other functional elements are to be formed in the substrate 1 to form an N-type epitaxial layer 2 (to remove the N+ buried layer 11). . (See Figure 1) Third step: SiO□ insulating film 4 on N-type epitaxial layer 2.
Using it as a t-mask, an isolation exposed region 3 is formed by thermally selective diffusion of P-type impurities, and this N-type epitaxial layer 2 is formed into an island-shaped epitaxial layer. A PN junction of the light receiving element is formed by the separated N type epitaxial layer 2a and the F'' layer 9. Here, the isolation region 3e surrounding the light receiving element 10 is used as a first isolation region and is used for other functions. The region 3f that partitions the element is the second
Fisoresis...area. (Refer to Fig. i?) In the fourth step, other functional elements are formed in the separated 7jN-type epitaxial layer 2b.In this embodiment, a light receiving element (photodiode) 10 is formed in the epitaxial layer 2a, 2 b K pigeon 5 register 15 is formed. This transistor 15 is an epitaxial Q2b'
(Used for 5 collectors, it is obtained by sequentially forming 2 layers (pace region) 6 and N layers (emitter region) 7 on this IFi 2 b starting with pace diffusion and emitter history. After that, each layer is 5a and 5b are light receiving elements (photodiodes) 101.
5 is the cathode electrode and anode electrode, and 4 is the emitter, pace, and collector electrode of the Y-transistor, and 4 is the Si
All of the 02 insulating films are shown. (Fig. 1 d) In an integrated circuit with a built-in photodetector manufactured in this way,
When a reverse voltage is applied between the I-sized poles 5a and 5b while the NQ epitaxial I? PN between 42a and P-[9
A depletion layer occurs near the junction surface. And P-P2O is P
Due to the low γζi degree of the type semiconductor eutectoid, this depletion layer is formed more cleanly than in the past. For this reason, the light receiving element l.
の接合容量は低減する。そしてこの受光素子１０へ光を
入射すると、光の強弱に比例した強さの逆電流が出力さ
れろ、このときの応答法ｉｔｒは以下の式で表すこ七が
できる。The junction capacitance of is reduced. When light is incident on the light receiving element 10, a reverse current with an intensity proportional to the intensity of the light is outputted.The response method itr at this time can be expressed by the following equation.
Ｃｊ： 受光素子（フォトダイオード）の接合容量Ｒ５
： 受光素子の内部直列抵抗
几Ｌ： 負荷抵抗
よってこの式からもわかるように接合容量Ｃｊが低減す
ると応答速度ｔｒは速くなる。Cj: Junction capacitance R5 of light receiving element (photodiode)
: Internal series resistance L of the light-receiving element: As can be seen from this equation, the response speed tr increases as the junction capacitance Cj decreases due to the load resistance.
また、このような集積回路の製造工程において、半導体
基板１表面の受光素子形成予定領域に、予め半導体基板
と同一導電型でこの基板よりも低濃度の不純物領域９を
形成する工程を取り入れているために１この不純物領域
９の濃度コントロールにより受光素子１０の応答速度を
適宜定めることができる。従って受光素子１０のこの不
純物領域９との間でＰＮ接合を形成するための隣接層即
ちエピタキシャルｊ？・７２ ａの形成に格別な制約が
ないため、トランジスタ１５の動作特性要求に応じてそ
のコレクタとなるエピタキシャル層２ｂに要求された条
件従って形成されたエピタキシャル層２が各層２ａ及び
２ｂＫ共通に利用できる。また前記不純物領域９により
受光素子の応答速度が定められ得るから、受光素子面積
を大きくしてその応答速度を速くでき、受光感度を向上
できる。更に、応答速度を速ぐするために半導体基板１
やエピタキシャルＭ２の不＃ｇ物濃度を低くする必要が
なｈので、刈れ〜電流による基板内での不所望な高電位
分布が・防止でき受光素子以外の他の機能素子の誤動作
が防止できる。ま恵受光素子以外の機能素子１例えばト
ランジスタのコレクタ抵抗を不所望に大きくすることが
なく例えば、 ＶＣｘ（ｓａｔ）を小さく保ソる。そし
てとのよう罠受光素子及びその他の機能素子の電気的特
性を維持した状與で集積回路・の溶易な製造が行なわれ
るなどの種々の効果がある。In addition, in the manufacturing process of such an integrated circuit, a step is introduced in advance to form an impurity region 9 of the same conductivity type as the semiconductor substrate and at a lower concentration than that of the substrate in the area where the light receiving element is to be formed on the surface of the semiconductor substrate 1. Therefore, by controlling the concentration of impurity region 9, the response speed of light receiving element 10 can be appropriately determined. Therefore, the adjacent layer, that is, the epitaxial layer j?, for forming a PN junction with this impurity region 9 of the light receiving element 10 is formed.・Since there are no particular restrictions on the formation of 72a, the epitaxial layer 2 formed according to the conditions required for the epitaxial layer 2b serving as the collector in accordance with the operational characteristics requirements of the transistor 15 can be commonly used for each layer 2a and 2bK. . Further, since the response speed of the light receiving element can be determined by the impurity region 9, the area of the light receiving element can be increased to increase its response speed, and the light receiving sensitivity can be improved. Furthermore, in order to speed up the response speed, the semiconductor substrate 1
Since it is not necessary to lower the concentration of impurities in the epitaxial layer M2, it is possible to prevent undesired high potential distribution within the substrate due to current, and to prevent malfunctions of functional elements other than the light-receiving element. For example, VCx (sat) can be kept small without undesirably increasing the collector resistance of functional elements 1, such as transistors, other than the light receiving element. In addition, there are various effects such as easy manufacture of integrated circuits while maintaining the electrical characteristics of the trap light-receiving element and other functional elements.
上記実施例ではＰ−Ｊ低濃度不純物領域９をイオン注入
によって形成する場合のみ述べ九が、熱拡散法で形成し
ても同様の効果が得られる。まな、このｒ層９は、写真
蝕刻法により基板１に穴を形成しその中にエピタキシャ
ル法によりＰ一層９を成長させて形成してもよい。In the above embodiment, only the case where the P-J low concentration impurity region 9 is formed by ion implantation is described; however, the same effect can be obtained even if it is formed by a thermal diffusion method. Alternatively, the r layer 9 may be formed by forming a hole in the substrate 1 by photolithography and growing the P layer 9 in the hole by epitaxial method.
ま念、この低濃度不純物領域９はｒ層に代えてＮ型エピ
タキシャル−より低濃度のＮ−型層であってもよく％Ｎ
’７Ｆは該２厘基板１にＮ型不紳物をとのＰ型基板の不
純物１度より高濃度に、イオン注入するか、又は上記の
ような熱拡散するかして形成する。なお、この場合の高
濃度とは、このＮ−１ｆＱの不純物濃度がＮ型エビタキ
７ヤル層の不純物濃度を越えないまでの程度を言う。By the way, this low concentration impurity region 9 may be an N-type layer with a lower concentration than an N-type epitaxial layer instead of the r layer.
'7F is formed by ion implantation of N-type impurities into the two-layer substrate 1 at a concentration higher than that of the P-type substrate, or by thermal diffusion as described above. Note that the high concentration in this case refers to the degree to which the impurity concentration of N-1fQ does not exceed the impurity concentration of the N-type epitaxy layer.
また、受光素子１０以外の鳴能素子として、バイポーラ
トランジスタ１５全図示して、述べたが、その他複数の
世態素子が他の領域に形成されてあシ、それらの礪能階
子の電気的特性も維持できることは言うまでもない。In addition, although the bipolar transistor 15 has been fully illustrated and described as a functional element other than the light-receiving element 10, a plurality of other electrical elements may be formed in other regions, and the electrical characteristics of those functional elements may be Needless to say, it can also be maintained.
本発明によると、半導体基板上の受光素子形成予定領域
のみ、Ｉ！Ｐ夜率姿ｆＩ亭、ザｌ趨府〃承りす低一度の
領域を形成する工８を取り入れているため受光素子以外
の素子の特性を維持した状、・裏で受光素子の応答速度
を向上させることができると共にその満造が容易である
という効果がある。According to the present invention, only the region on the semiconductor substrate where the light receiving element is to be formed is I! P-night view fI-tei, Zarufu〃Since it incorporates the process 8 to form a low-level area, the characteristics of elements other than the light-receiving element are maintained, and the response speed of the light-receiving element is improved on the back side. It has the advantage that it can be easily manufactured and completed.
第１図は本発明方法の一実施例を示す工程図であり、べ
き稍回路の受光素子付近の断面図、第２図は従来の不積
回路の受光素子付近の断面図、第３図は個別受光素子（
ＰＩＮ ７オトダイオード）の断面図である。
１・・・Ｐ型半導体基板（第１４電型半導体基板）２・
・・Ｎ型エピタキシャル層（第２導電型エピタキシャル
層）３・・・アイソレーション領域（３ｅ、２に１アイ
ンレーション領域代理人 弁理士 則近ン１佑（ほか１
名）第１図FIG. 1 is a process diagram showing an embodiment of the method of the present invention, and FIG. 2 is a cross-sectional view of the vicinity of the light-receiving element of a powerless circuit, FIG. Individual photodetector (
PIN 7 Otodiode). 1... P-type semiconductor substrate (14th electric type semiconductor substrate) 2.
...N-type epitaxial layer (second conductivity type epitaxial layer) 3...Isolation region (3e, 2 to 1 isolation region agent Patent attorney Norichika 1yu (and 1 others)
name) Figure 1
Claims (5)
低濃度不純物領域を形成する工程と、前記予定領域を含
む半導体基板表面に第２導電型エピタキシャル層を形成
する工程と、前記予定領域を囲んで前記低濃度不純物領
域に到達して前記エピタキシャル層のうち受光素子用の
第１エピタキシャル層を区画する第１アイソレーシヨン
領域及び、前記基板に到達して他の機能素子用の第２エ
ピタキシャル層を区画する第２アイソレーシヨン領域を
形成する工程とを具備し、前記第１エピタキシャル層と
前記低濃度不純物領域との間のＰＮ接合を用いて形成さ
れる受光素子がこの低濃度不純物領域の不純物濃度に依
存してその応答速度がコントロールされていることを特
徴とする集積回路の製造方法。(1) A step of forming a low concentration impurity region in a region of a first conductivity type semiconductor substrate where a light receiving element is to be formed, a step of forming a second conductivity type epitaxial layer on a surface of the semiconductor substrate including the said planned region, and a step of forming a second conductivity type epitaxial layer in said planned region. a first isolation region surrounding the substrate and reaching the low concentration impurity region to define a first epitaxial layer for a light-receiving element in the epitaxial layer; forming a second isolation region that partitions an epitaxial layer, and a light receiving element formed using a PN junction between the first epitaxial layer and the low concentration impurity region is formed using the low concentration impurity region. A method for manufacturing an integrated circuit, characterized in that its response speed is controlled depending on the impurity concentration of the region.
記基板よりも低濃度であることを特徴とする特許請求の
範囲第１項記載の集積回路の製造方法。(2) The method for manufacturing an integrated circuit according to claim 1, wherein the low concentration impurity region is of a first conductivity type and has a lower concentration than the substrate.
エピタキシャル層よりも低濃度であることを特徴とする
特許請求の範囲第１項記載の集積回路の製造方法。(3) The method of manufacturing an integrated circuit according to claim 1, wherein the low concentration impurity region is of a second conductivity type and has a lower concentration than the epitaxial layer.
記基板の不純物濃度より低濃度にイオン注入することに
より形成することを特徴とする特許請求の範囲第２項記
載の集積回路の製造方法。(4) Manufacturing the integrated circuit according to claim 2, wherein the low concentration impurity region is formed by ion-implanting a second conductivity type impurity at a concentration lower than the impurity concentration of the substrate. Method.
よりも低濃度な第１導電型となる程度に第２導電型不純
物を前記基板の不純物濃度より高濃度にイオン注入する
ことにより形成することを特徴とする特許請求の範囲第
３項記載の集積回路の製造方法。(5) The low concentration impurity region is formed by ion-implanting a second conductivity type impurity at a higher concentration than the impurity concentration of the substrate so as to have a first conductivity type lower in concentration than the epitaxial layer. A method for manufacturing an integrated circuit according to claim 3, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59191800A JPH0644617B2 (en) | 1984-09-14 | 1984-09-14 | Method of manufacturing integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59191800A JPH0644617B2 (en) | 1984-09-14 | 1984-09-14 | Method of manufacturing integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6170750A true JPS6170750A (en) | 1986-04-11 |
| JPH0644617B2 JPH0644617B2 (en) | 1994-06-08 |
Family
ID=16280743
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59191800A Expired - Lifetime JPH0644617B2 (en) | 1984-09-14 | 1984-09-14 | Method of manufacturing integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0644617B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61280655A (en) * | 1985-05-14 | 1986-12-11 | Sanyo Electric Co Ltd | Semiconductor integrated circuit with incorporated photosensor |
| JPS6372151A (en) * | 1986-09-13 | 1988-04-01 | Semiconductor Res Found | Solid-state image sensing device and its manufacture |
| JPH03262167A (en) * | 1990-03-12 | 1991-11-21 | Sharp Corp | Photodetector with built-in circuit |
-
1984
- 1984-09-14 JP JP59191800A patent/JPH0644617B2/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61280655A (en) * | 1985-05-14 | 1986-12-11 | Sanyo Electric Co Ltd | Semiconductor integrated circuit with incorporated photosensor |
| JPS6372151A (en) * | 1986-09-13 | 1988-04-01 | Semiconductor Res Found | Solid-state image sensing device and its manufacture |
| JPH03262167A (en) * | 1990-03-12 | 1991-11-21 | Sharp Corp | Photodetector with built-in circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0644617B2 (en) | 1994-06-08 |
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