KR0175368B1 - Method of fabricating high voltage and low voltage transistor instantaneously - Google Patents

Abstract

A complementary bipolar process for integrating devices with different breakdown voltages of transistors is implemented on a semiconductor substrate. By using a double epitaxial layer and selectively using ion sources with different diffusivities in the buried layer, it is possible to simultaneously manufacture high voltage and low voltage NPN transistors and vertical PNP transistors. That is, devices having the same size but different breakdown voltages can be manufactured together.

Description

Semiconductor manufacturing method for simultaneously forming high voltage and low voltage transistor

1 is a cross-sectional view of a transistor structure manufactured according to the prior art.

(A)-(c) of FIG. 2 are cross-sectional views of a transistor structure manufactured according to the present invention.

(A)-(c) of FIG. 3 is sectional drawing which shows the process sequence of the transistor manufactured by this invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing method for simultaneously forming a high voltage and a low voltage transistor. More specifically, the present invention relates to a complementary bipolar that can form a high, medium, and low voltage transistor in a single wafer substrate according to a range. A semiconductor manufacturing method.

In general, bipolar transistors that perform switching or amplification functions in a circuit are composed of a PN junction made of electrical connections between emitter, base, and collector regions. The manufacturing method of the present invention is to form a high concentration of the N + buried layer (Puried layer) on a P conductivity type substrate, a low concentration of the epitaxial layer of the N- conductivity type (Layer) and then to the base region, emitter (collector) It consists of a basic structure that forms an area. An epitaxial-based vertical PNP transistor and an NPN transistor having this structure are shown in FIG.

However, such a conventional technology has a disadvantage in that process parameters cannot be matched when various products having a breakdown voltage (BVceo) of a transistor are designed on a single wafer substrate. In addition, the VPNP transistor has a problem that the current flows out to the substrate depending on the degree of breakdown voltage.

Accordingly, an object of the present invention is to solve the problems of the prior art as described above, complementary bipolar semiconductor capable of simultaneously manufacturing a variety of devices with a high breakdown voltage, that is, a high, medium, low voltage transistor on one semiconductor substrate It is to provide a manufacturing method.

Another object of the present invention is to provide a method of manufacturing a complementary bipolar semiconductor capable of preventing leakage current from a VPNP transistor to a substrate by using a double epitaxial process.

In order to achieve the above object, the present invention, as the masking oxide (Masking oxide) on the P-conductive substrate, growing an initial oxide layer of 7,000-8,000 Å and forming a pattern as the first mask, and then implanted NNBL ion implanted and buried A first step of performing layer diffusion,

In the second step of removing the entire oxide film and growing the first epitaxial layer, a high buried layer N + BL pattern is formed and ion implanted into arsenic,

A third step of forming a high concentration P + conductive bottom (P + BTM) pattern, implanting boron and then simultaneously diffusing;

A fourth process of growing a second epitaxial layer,

A fifth step of forming a high concentration of N + sink, a high concentration of P + isolation (ISO), and a low concentration of N-tub (N-TUB) pattern and diffusing these three regions simultaneously after ion implantation;

And a sixth step of forming a P- intrinsic base region, a P + extrinsic base region, and then forming an N + emitter region according to a general bipolar process sequence. It provides a semiconductor manufacturing method to be formed.

DETAILED DESCRIPTION Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily practice the present invention.

2 is a cross sectional view of a transistor structure fabricated in accordance with the present invention. FIG. 2 (a) is a structure formed when arsenic is used in the NNBL region of FIG. 3 (a), where 20 is a low voltage NPN transistor, 21 is a high voltage NPN transistor, and 22 is a vertical PNP transistor. Each structure is shown. FIG. 2 (b) shows a structure formed by double ion implantation of arsenic (indicated by a solid line) or phosphorus (indicated by a dotted line) in the NNBL region. In addition, FIG. 2C shows a structure formed when a process is performed by ion implanting only phosphorus into the NNBL region.

As described above, an appropriate NPN transistor can be selected according to a user's desired application on one semiconductor substrate by using a different diffusion rate of Arsenic and Phosphorus. That is, the diffusivity of phosphorus is considerably larger than that of arsenic. From the process point of view, the difference in the degree of out-diffusion to the base region when the base layer is formed after diffusion of the buried layer is used.

A method of manufacturing a transistor having the above structure will be described in detail with reference to FIG.

First, as shown in FIG. 3 (a), an initial oxide layer of 7,000-8,000 kPa is grown as a masking oxide on the P-conductive substrate 30, and a pattern is formed as the first mask, followed by NNBL 31. Ion implantation is performed, and buried layer diffusion is performed. Here, the solid line shows the case where arsenic (As) is used as a source of ion implantation, and the dotted line shows the profile when phosphorus (P) is used as a source. After forming the NNBL layer, as shown in FIG. 3 (b), the entire oxide layer is removed and the primary epitaxial layer 32 is grown.

Then, as shown in FIG. 3 (c), a high concentration of buried layer N + BL (33) pattern is formed and ion implantation is performed to form a high concentration of P + conductive bottom (P + BTM) 34 pattern. Ion implantation of boron is performed and then diffused simultaneously. At this time, the isolation portion, the collector of the VPNP transistor and the collector region of the NPN transistor are formed together.

When the secondary epitaxial layer 35 is grown, it is shown in FIG. 3 (d).

Next, as shown in FIG. 3E, a high concentration of N + sink 36, a high concentration of P + isolation (ISO) 37, and a low concentration of N-TUB 38 are shown. After forming and ion implantation, these three regions are simultaneously diffused. Then, the sink region 36 and the N + BL region 33 are bonded to each other, and the ISO region 37 and the P + BTM region 34 are bonded to each other and completely separated from each other. On the other hand, the N-TUB 38, which is the base of the VPNP transistor, is formed together.

The P-intrinsic base region 39 is then formed in accordance with the general bipolar process sequence, and the P + extrinsic base (emitter region 40 in the case of a VPNP transistor) is formed. Finally, an N + emitter (base contact in the case of a VPNP transistor) region 41 is formed (see FIG. 3 (f)).

The bipolar transistor of the present invention manufactured by the above-described manufacturing process has an effect of forming a transistor having various characteristics, that is, a breakdown voltage, on one semiconductor substrate by selecting source ions.

Claims (1)

Forming an initial oxide pattern on a P-type substrate divided into a high voltage NPN transistor region, a low voltage NPN transistor region, and a vertical PNP transistor region, implanting and diffusing N-type ions into the substrate using the initial oxide pattern as a mask; Forming a first buried layer in a high voltage NPN transistor region, a low voltage NPN transistor region, and a vertical PNP transistor region, respectively, removing the initial oxide layer, growing a primary epitaxial layer on the substrate, and the low voltage NPN transistor Forming an N + type second buried layer and a first collector region respectively connected to said first buried layer in said primary epitaxial layer of said region and said high voltage NPN transistor region, said high voltage NPN transistor region and a low voltage NPN transistor region And between the vertical PNP transistor regions and the vertical PNP transistor Forming a P + type bottom region in an inverse primary epitaxial layer, growing a second epitaxial layer on the first epitaxial layer, and a second buried layer of the low voltage NPN transistor region and the high voltage NPN transistor region. And forming an N + sink in the secondary epitaxial layer on the first collector region, implanting ions in the secondary epitaxial layer on the P + type bottom region to form a P + isolation, the vertical PNP Forming an N-tub in the secondary epitaxial layer on the P-type bottom region of the transistor, simultaneously diffusing the N + sink, P + isolation, N-tub, and P-endurance according to a general bipolar process sequence Forming a base region, forming a P + exogenous base region, and then forming an N + emitter region. Article methods.