KR100368612B1 - method of fabricating vertical type transistor - Google Patents
method of fabricating vertical type transistor Download PDFInfo
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- KR100368612B1 KR100368612B1 KR10-2000-0039856A KR20000039856A KR100368612B1 KR 100368612 B1 KR100368612 B1 KR 100368612B1 KR 20000039856 A KR20000039856 A KR 20000039856A KR 100368612 B1 KR100368612 B1 KR 100368612B1
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 238000009792 diffusion process Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims description 15
- 229910052787 antimony Inorganic materials 0.000 claims description 5
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 5
- 229910052785 arsenic Inorganic materials 0.000 claims description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 5
- 238000002513 implantation Methods 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims 5
- 238000001465 metallisation Methods 0.000 claims 2
- 238000000059 patterning Methods 0.000 claims 2
- 238000002955 isolation Methods 0.000 abstract description 10
- 230000015556 catabolic process Effects 0.000 abstract description 7
- 238000007796 conventional method Methods 0.000 description 5
- 238000005245 sintering Methods 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000010408 sweeping Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0804—Emitter regions of bipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1004—Base region of bipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66272—Silicon vertical transistors
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Abstract
내압특성이 개선된 수직형 바이폴라 트랜지스터의 제조방법이 개시된다. 그러한 제조방법은, 기판에 N+ 매몰층 및 P 매몰층을 차례로 형성시 상기 P 매몰층의 소오스 이온 농도가 최대치가 되는 부분을 상기 N+ 매몰층의 대체로 상부에 위치되게 형성한 것을 특징으로 하는 것과, N+ 매몰층의 확산깊이를 깊게 하여 P 매몰층의 하부영역이 N+ 매몰층의 하부영역보다는 높도록 한 것을 특징으로 한다. 이에 따라, 콜렉터와 아이솔레이션 간의 내압 특성이 대폭적으로 개선되며, 구동능력이 좋고, 콜렉터 에미터간 포화전압이 감소되어 소비전력이 줄어든다. 상기한 구조를 이용하여 집적회로를 제조 시에 수직형으로서도 수평형 트랜지스터의 사용범위까지 커버하여 사용범위가 넓어진다.A method of manufacturing a vertical bipolar transistor having improved breakdown voltage characteristics is disclosed. Such a manufacturing method is characterized in that, when the N + buried layer and the P buried layer is sequentially formed on the substrate, the portion where the source ion concentration of the P buried layer becomes the maximum is formed to be located substantially above the N + buried layer, The depth of diffusion of the N + buried layer is deepened so that the lower region of the P buried layer is higher than the lower region of the N + buried layer. Accordingly, the breakdown voltage characteristics between the collector and the isolation are greatly improved, the driving ability is good, and the saturation voltage between the collector emitters is reduced, thereby reducing power consumption. When the integrated circuit is manufactured using the above-described structure, the use range of the vertical type also covers the use range of the horizontal type transistor, thereby widening the use range.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 소자특성이 개선된 수직형 트랜지스터의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a vertical transistor with improved device characteristics.
종래의 수직형 바이폴라 PNP트랜지스터는 콜렉터와 아이솔레이션 간의 내압 특성이 비교적 낮아서 약 20볼트 이상으로 전압이 높게 걸리는 집적회로에는 사용하기 어려웠다. 종래의 제조방법에 따라 제조된 트랜지스터의 구조는 도 1에서 도시되어 있다.Conventional vertical bipolar PNP transistors have relatively low breakdown voltage characteristics between the collector and the isolation, making it difficult to use in integrated circuits that require high voltages of about 20 volts or more. The structure of a transistor manufactured according to a conventional manufacturing method is shown in FIG.
도 1을 참조하면, N+ 매몰층 (10:Buried Layer, B/L)의 상부에 P 매몰층(20)의 소오스를 이온 임플란테이션 또는 화학기상증착(CVD)법으로 확산시켜 콜렉터 층(C)으로서 사용한다. 이 경우 P 매몰층(20)의 소오스인 보론(Boron)의 확산속도가 N+ 매몰층(10)의 소오스인 비소(As)나 안티몬(Sb)의 확산속도보다 빨라서 상부로 확산이 되는 동시에 N+ 매몰층(10)을 지나 기판(2)의 하부로도 확산이 된다. 수직형 바이폴라 트랜지스터의 브레이크 다운 메카니즘은 콜렉터(C)에 높은 전압을 걸고 아이솔레이션 ISO(S)에 최저 전위를 걸어 스위프(Sweep)시키면 N+ 매몰층(10)과 기판 쪽의 P 매몰층(20)의 농도에 의해 전계필드가 집중되어 발생된다. 이를 BVCSO라고 하며 이는 평균적으로 수직형 소자에서 20볼트를 넘기 어려운 것으로 알려져 있다. 통상적인 집적회로 소자에는 저전압 소자도 있지만 20볼트가 넘는 소자도 많이 있다. 특히, 저전압 드롭 레귤레이터와 같은 소자는 통상 60볼트 이상의 내압을 요구한다. 따라서, 콜렉터와 아이솔레이션 간의 내압 특성 즉 BVCSO를 증가시키지 않으면 사용범위가 상당히 축소된다.Referring to FIG. 1, a source of the P buried layer 20 is diffused on an N + buried layer (B / L) by ion implantation or chemical vapor deposition (CVD) to collect a collector layer (C). ) Is used. In this case, the diffusion rate of boron (source) of the P buried layer 20 is faster than the diffusion rate of arsenic (As) or antimony (Sb), which is a source of the N + buried layer 10, and is diffused upwards, and N + buried The layer 10 also diffuses below the substrate 2. The breakdown mechanism of the vertical bipolar transistor is applied by applying a high voltage to the collector (C) and sweeping the lowest potential to the isolation ISO (S), and sweeping the N + buried layer 10 and the P buried layer 20 on the substrate side. The electric field is concentrated by the concentration. This is called BVCSO, which is known to be less than 20 volts on average for vertical devices. Conventional integrated circuit devices include low voltage devices, but many are over 20 volts. In particular, devices such as low voltage drop regulators typically require a breakdown voltage of 60 volts or more. Therefore, the use range is considerably reduced unless the pressure resistance characteristic between the collector and the isolation, that is, BVCSO, is increased.
또한, 종래의 방법은 P 매몰층의 최대농도가 N+ 매몰층에 있게 되며, N+ 매몰층 속에 있는 P 매몰층은 콜렉터로서 제대로 기능하지 못하여 전류의 흐름을 최대로 하기 어렵게 된다. 결국, 그러한 경우에 콜렉터의 저항이 증가하게 되어 전류 구동능력(ICmax)이 나빠지며, 콜렉터 에미터간 포화전압(Vce saturation)도 증가하게 되어 소비전류가 아울러 커지게 되는 문제가 있다.In addition, in the conventional method, the maximum concentration of the P buried layer is in the N + buried layer, and the P buried layer in the N + buried layer does not function properly as a collector, making it difficult to maximize the flow of current. As a result, in such a case, the resistance of the collector is increased, the current driving ability (ICmax) is deteriorated, and the saturation voltage (Vce saturation) between the collector emitters is also increased, resulting in a large current consumption.
상기한 바와 같이, 종래의 수직형 트랜지스터는 콜렉터와 아이솔레이션 간의내압 특성이 비교적 낮아서 약 20볼트 이상으로 전압이 높게 걸리는 집적회로에는 사용이 제한되는 문제가 있어왔다.As described above, the conventional vertical transistor has a problem in that its use is limited in an integrated circuit in which the voltage resistance between the collector and the isolation is relatively low, so that the voltage is high above about 20 volts.
따라서, 본 발명의 목적은 상기한 종래의 문제점을 해결할 수 있는 수직형 바이폴라 트랜지스터의 제조방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a vertical bipolar transistor that can solve the above-described conventional problems.
본 발명의 다른 목적은 수직형 바이폴라 트랜지스터의 개선된 구조를 제공함에 있다.Another object of the present invention is to provide an improved structure of the vertical bipolar transistor.
본 발명의 또 다른 목적은 내압 특성이 개선된 수직형 바이폴라 피엔피 트랜지스터의 제조방법을 제공함에 있다.Another object of the present invention is to provide a method of manufacturing a vertical bipolar PNP transistor with improved breakdown voltage characteristics.
상기한 목적들 및 타의 목적을 달성하기 위한 본 발명의 기술적 사상에 따라, 기판에 N+ 매몰층 및 P 매몰층을 차례로 형성시 상기 P 매몰층의 소오스 이온 농도가 최대치가 되는 부분이 상기 N+ 매몰층의 대체로 상부에 위치되도록 한 후에 나머지 공정을 진행하여 트랜지스터를 제조하는 것을 특징으로 한다.According to the technical spirit of the present invention for achieving the above objects and other objects, the portion where the source ion concentration of the P buried layer becomes the maximum when the N + buried layer and the P buried layer in order to form a substrate in order to the maximum N + buried layer It is characterized in that the transistor is manufactured by proceeding with the rest of the process after being positioned on the upper portion of the.
또한, 본 발명의 또 다른 기술적 사상에 따라, N+ 매몰층의 확산깊이를 깊게 하여 P 매몰층의 하부영역이 N+ 매몰층의 하부영역보다는 높도록 제조한 것을 특징으로 한다.In addition, according to another technical idea of the present invention, the depth of diffusion of the N + buried layer is deepened, characterized in that the lower region of the P buried layer is manufactured to be higher than the lower region of the N + buried layer.
도 1은 종래기술에 따른 수직형 바이폴라 트랜지스터의 단면구조도1 is a cross-sectional structure diagram of a vertical bipolar transistor according to the prior art
도 2는 본 발명의 일 실시 예에 따른 수직형 바이폴라 트랜지스터의 단면구조도2 is a cross-sectional structure diagram of a vertical bipolar transistor according to an embodiment of the present invention.
도 3은 본 발명의 또 다른 실시 예에 따른 수직형 바이폴라 트랜지스터의 단면구조도3 is a cross-sectional structure diagram of a vertical bipolar transistor according to another embodiment of the present invention;
상기한 본 발명의 목적들 및 타의 목적들, 특징, 그리고 이점들은, 첨부된도면들을 참조하여 이하에서 기술되는 본 발명의 상세하고 바람직한 실시예의 설명에 의해 보다 명확해질 것이다. 도면들 내에서 서로 동일 내지 유사한 부분들은 설명 및 이해의 편의상 동일 내지 유사한 참조부호들로 기재됨을 주목하여야 한다.The above and other objects, features, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the present invention described below with reference to the accompanying drawings. It should be noted that in the drawings, the same or similar parts to each other are described with the same or similar reference numerals for convenience of description and understanding.
도 2에는 본 발명의 일실시 예에 따른 수직형 바이폴라 트랜지스터의 단면구조가 나타나 있다. 도면을 참조하면, 도 1에서 보여지는 수직형 트랜지스터의 단면구조와는 달리, N+ 매몰층(10) 및 P 매몰층(22)을 차례로 형성시 상기 P 매몰층(22)의 소오스 이온 농도가 최대치가 되는 부분이 상기 N+ 매몰층(10)의 대체로 상부에 위치되도록 한 것이 보여진다.2 illustrates a cross-sectional structure of a vertical bipolar transistor according to an embodiment of the present invention. Referring to the drawing, unlike the cross-sectional structure of the vertical transistor shown in FIG. 1, when the N + buried layer 10 and the P buried layer 22 are sequentially formed, the source ion concentration of the P buried layer 22 is maximum. It can be seen that the portion to be positioned substantially on top of the N + buried layer (10).
기판(2)에 N+ 매몰층(10)을 형성하는 것은 통상의 방법을 그대로 사용할 수 있다. 실시 예에 대한 이해의 편의를 돕기 위해 부가적 사항으로서 설명하면, 상기 N+ 매몰층(10)은 비소나 안티몬 소오스를 확산시켜 수직 PNP트랜지스터의 콜렉터와 기판을 분리한다. 상기 N+ 매몰층(10)은 NPN트랜지스터의 콜렉터 시리즈 저항을 줄이며 기생소자가 생기는 것을 방지하는 목적으로도 사용된다.Forming the N + buried layer 10 on the substrate 2 can use a conventional method as it is. As an additional matter in order to facilitate the understanding of the embodiment, the N + buried layer 10 diffuses arsenic or antimony sources to separate the collector and the substrate of the vertical PNP transistor. The N + buried layer 10 is also used for the purpose of reducing the collector series resistance of the NPN transistor and preventing parasitic elements from occurring.
상기 P 매몰층(22)의 제조는 통상의 방법과는 다르게 형성된다. 즉, 에피텍셜층(FE:제1에피층)을 약 2∼8㎛ 정도로 성장시키고, P 매몰층(22)의 소오스를 이온주입하여 확산시키면, N+ 매몰층(10)의 하부까지 상기 P 매몰층(22)이 확산되지 않는다. 따라서, BVCSO는 약 80볼트 이상으로 상당히 높게 된다. 상기 P 매몰층(22)은 수직형 트랜지스터의 콜렉터로서 사용되어진다. P 매몰층(22)은 아이솔레이션 아래에 위치하여 타의 소자와의 소자분리용으로서 사용된다. 이 후에 최종적으로 원하는 에피텍셜 층의 두께가 되도록 잔여 에피층(SE:제2에피층)을 성장시킨다. 이 경우에 P 매몰층(22)의 최대 농도점은 N+ 매몰층(10) 상부에서 약 2∼8㎛ 정도가 되는 지점이다. 따라서, 콜렉터의 저항을 낮추게 되어, 전류 구동능력(ICmax)이 좋아지고, 콜렉터 에미터간 포화전압(Vce saturation)이 감소되어 저소비전력이 구현된다.The P buried layer 22 is manufactured differently from the conventional method. That is, when the epitaxial layer (FE: first epitaxial layer) is grown to about 2 to 8 μm, and the source of the P buried layer 22 is ion implanted and diffused, the P buried to the lower portion of the N + buried layer 10. Layer 22 does not diffuse. Thus, BVCSO is considerably high, above about 80 volts. The P buried layer 22 is used as a collector of the vertical transistor. The P buried layer 22 is located under isolation and used for device isolation from other devices. Thereafter, the remaining epitaxial layer (SE: second epitaxial layer) is grown to finally have a thickness of the desired epitaxial layer. In this case, the maximum concentration point of the P buried layer 22 is about 2 to 8 µm above the N + buried layer 10. Accordingly, the resistance of the collector is lowered, the current driving capability ICmax is improved, and the saturation voltage Vce saturation between the collector emitters is reduced, thereby achieving low power consumption.
이후의 공정은 기존의 수직형 PNP트랜지스터 공정과 동일할 수 있다. 간략히 기술하면, N-웰을 인 임플란테이션 및 확산공정으로 형성하고, 보론을 주입하여 에미터(E)를 만든다. N- 타입 소오스를 확산시켜 베이스(B)를 만들고, 접촉 창을 형성하여 금속 예컨대 알루미늄을 증착하여 패터닝한다. 이후 신터링 공정으로 소결하면 수직형 트랜지스터 소자가 완성된다.The subsequent process may be the same as the conventional vertical PNP transistor process. In brief, N-wells are formed by in-implantation and diffusion processes and boron is injected to make emitters (E). The N-type source is diffused to form a base (B), and a contact window is formed to deposit and pattern a metal such as aluminum. After sintering by the sintering process, a vertical transistor device is completed.
도 3에는 본 발명의 또 다른 실시 예에 따른 수직형 바이폴라 트랜지스터의 단면구조가 나타나 있다. 도면을 참조하면, N+ 매몰층(12)의 확산깊이를 깊게 하여 P 매몰층(24)의 하부영역이 N+ 매몰층(12)의 하부영역보다는 높도록 한 것이 보여진다.3 illustrates a cross-sectional structure of a vertical bipolar transistor according to another embodiment of the present invention. Referring to the drawings, it can be seen that the depth of diffusion of the N + buried layer 12 is deepened so that the lower region of the P buried layer 24 is higher than the lower region of the N + buried layer 12.
기판(2)에 N+ 매몰층(12)을 형성하는 것은 통상의 방법을 그대로 사용하여 확산시킬 수 있다. 이해의 편의를 돕기 위해 설명하면, 상기 N+ 매몰층(12)은 비소나 안티몬 소오스를 확산시켜 수직 PNP트랜지스터의 콜렉터와 기판을 분리한다. 통상적인 공정에서는 약 4㎛ 이내의 깊이로 확산을 시키나, 본 실시 예에서는 약 8㎛ 정도로 한다. 상기 N+ 매몰층(12)은 NPN트랜지스터의 콜렉터 시리즈 저항을 줄이며 기생소자가 생기는 것을 방지하는 목적으로도 기능한다.Forming the N + buried layer 12 on the substrate 2 can be diffused using a conventional method as it is. For convenience of understanding, the N + buried layer 12 diffuses arsenic or antimony source to separate the collector and the substrate of the vertical PNP transistor. In a typical process, the diffusion is performed to within a depth of about 4 μm, but in this embodiment, it is about 8 μm. The N + buried layer 12 also serves to reduce the collector series resistance of the NPN transistor and to prevent parasitic elements from occurring.
상기 P 매몰층(24)의 제조는 통상의 방법과 동일하게 형성될 수 있다. 상기P 매몰층(24)은 수직형 트랜지스터의 콜렉터(C)로서 사용되어진다. P 매몰층(24)은 아이솔레이션 아래에 위치하여 타의 소자와의 소자분리용으로서 사용된다.The P buried layer 24 may be manufactured in the same manner as a conventional method. The P buried layer 24 is used as the collector C of the vertical transistor. The P buried layer 24 is located under isolation to be used for device isolation from other devices.
상기한 구조에 의해, 콜렉터의 저항을 낮추게 되어, 전류 구동능력(ICmax)이 좋아지고, 콜렉터 에미터간 포화전압(Vce saturation)이 감소되어 저소비전력이 구현된다.By the above structure, the resistance of the collector is lowered, the current driving capability (ICmax) is improved, and the saturation voltage (Vce saturation) between the collector emitters is reduced, thereby achieving low power consumption.
이후의 공정은 기존의 수직형 PNP트랜지스터 공정과 동일할 수 있다. 간략히 기술하면, 에피층을 성장시키고, N-웰을 인 임플란테이션 및 확산공정으로 형성하고, 보론을 주입하여 에미터(E)를 만든다. N- 타입 소오스를 확산시켜 베이스(B)를 만들고, 접촉 창을 형성하여 금속 예컨대 알루미늄을 증착하여 패터닝한다. 이후 신터링 공정으로 소결하면 도 3과 같은 수직형 트랜지스터 소자가 완성된다.The subsequent process may be the same as the conventional vertical PNP transistor process. Briefly, the epi layer is grown, the N-well is formed by in-implantation and diffusion processes, and boron is injected to make the emitter (E). The N-type source is diffused to form a base (B), and a contact window is formed to deposit and pattern a metal such as aluminum. After sintering by the sintering process, a vertical transistor device as shown in FIG. 3 is completed.
상기한 바와 같이, 본 발명은 도면을 기준으로 예를 들어 기술되었지만 이에 한정되지 않으며 발명의 기술적 사상을 벗어나지 않는 범위 내에서 본 발명이 속하는 기술분야에서 통상의 지식을 갖는 자에 의해 다양한 변화와 변경이 가능함은 물론이다. 예를 들어, 매몰층들에 주입되는 소오스의 타입이나 농도 및 사이즈등은 사안에 따라 다양하게 변경 또는 변화시킬 수 있음은 물론이다.As described above, the present invention has been described by way of example only with reference to the drawings, but is not limited thereto, and various changes and modifications by those skilled in the art to which the present invention pertains may be made without departing from the technical spirit of the present invention. Of course this is possible. For example, the type, concentration, and size of the source injected into the buried layers can be varied or changed depending on the matter.
상술한 바와 같이, 기판에 N+ 매몰층 및 P 매몰층을 차례로 형성시 상기 P 매몰층의 소오스 이온 농도가 최대치가 되는 부분이 상기 N+ 매몰층의 대체로 상부에 위치되도록 한 후에 나머지 공정을 진행하여 트랜지스터를 제조하는 것과, N+매몰층의 확산깊이를 깊게 하여 P 매몰층의 하부영역이 N+ 매몰층의 하부영역보다는 높도록 한 것을 특징으로 하는 본 발명에 따르면, 콜렉터와 아이솔레이션 간의 내압 특성을 대폭적으로 개선하는 효과가 있다. 또한, 콜렉터 에미터간 포화전류를 감소시킴에 의해 전력의 소모를 줄이고, 브레이크 다운 전압을 대폭적으로 증가시키므로 저전압 드롭 레귤레이터에 충분히 적용할 수 있는 장점이 있다. 따라서, 수직형 PNP트랜지스터를 이용하여 집적회로를 제조시에 수직형으로서도 수평형 트랜지스터의 사용범위까지 커버하여 사용범위를 넓힐 수 있는 이점이 있다.As described above, when the N + buried layer and the P buried layer are sequentially formed on the substrate, the portion where the source ion concentration of the P buried layer becomes the maximum is generally positioned above the N + buried layer, and then the rest of the process proceeds to the transistor. According to the present invention, the lower region of the P buried layer is higher than the lower region of the N + buried layer, and the pressure resistance between the collector and the isolation is significantly improved. It is effective. In addition, by reducing the saturation current between the collector emitters, the power consumption is reduced, and the breakdown voltage is greatly increased, which is sufficient to apply to a low voltage drop regulator. Therefore, when manufacturing an integrated circuit using a vertical PNP transistor, there is an advantage in that the use range of the vertical type transistor can be covered even if the vertical type is used.
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