JPS61278168A - Compound semiconductor device - Google Patents

Abstract

PURPOSE:To implement a semiconductor device which operates at a high speed, by alternately laminating thin film layers of InAs and AlAs, and adding an N-type impurity into AlAs, thereby enabling a two-dimensional electron storage layer to be formed at the InAs side which is being subjected to elastic tetragonal deformation. CONSTITUTION:A channel layer is provided which has a construction in which InAs layers (40Angstrom thick) 2 formed using the MBE growth method and AlAs layers (40Angstrom thick) 3 are alternately laminated on a semi-insulating InP substrate 1. In the AlAs layers, Si is doped as an N-type impurity. The InAs layers 2 are subjected to elastic tetragonal deformation in the crystal structure thereof, large energy discontinuity exists at the InAs-AlAs interface, and only the AlAs layers 3 are doped with Si. With this, even at a room temperature, a two-dimensional electron storage layer is formed only in the InAs layers 2, which has a larger entrapment effect as compared with the conventional GaAs-GaxAl1-xAs system.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to compound semiconductor devices. More specifically, by spatially separating the crystal region through which electrons travel and the crystal region supplying electrons by a heterojunction, the electron travel speed is increased by eliminating the scattering of electrons by donor impurities. The present invention relates to high electron mobility transistors.

BACKGROUND OF THE INVENTION Epitaxial growth methods are generally used as a manufacturing method for compound semiconductor devices, particularly electronic devices, because of the ease of growing thin, uniform layers and controlling the composition ratio of component elements. Among them, a molecular beam epitaxial growth method (hereinafter referred to as "rMBE growth method" for simplicity) is known as a technique that has recently attracted particular attention. For example, W, T, Ts
ang by Nikkei Electronics 808, 16
3 (1983), the MBE growth method and devices utilizing thin film periodic structures are described in detail. By following this MBE growth method, the crystal growth rate can be controlled at the monatomic level (J, P, van der
Ziel et al., J-Appl-phy, 48 (197
7) P4O10), and even the composition of the l atomic plane can be precisely controlled by using reflection electron diffraction (J, H, Neave et al., Appl.

phy, A31, 1 (1983)). By using such an MBE method, it becomes possible to manufacture a high electron mobility transistor (hereinafter abbreviated as r HEMT J ) as shown in FIG. 2. Note that microwave elements using conventional compound semiconductors are described in, for example, Japanese Patent Laid-Open No. 59-4085 and Japanese Patent Laid-Open No. 58-147169.

The HEMT structure shown in FIG. 2 has a semi-insulating GaAs substrate 10, on which a GaAs layer 11 functioning as a buffer layer is formed, and a channel layer is further formed on it. Undoped GaAsJi 12 is formed. Then, on the GaAs layer 12, n-Gax AI! An electron supply layer 13 with a high impurity concentration such as 1-X As is formed, and a layer 14 made of a semiconductor containing a high concentration of P-type impurities and having a large electron affinity is provided in the center, and A gate electrode 15 is formed on the layer 14. Furthermore,
Surface regions 16 of electron supply layer 13 sandwiching layer 14 are alloyed and source and drain electrodes 17 are formed thereon.

In such a semiconductor device, when an appropriate bias voltage is applied to the gate electrode 15, a secondary electron storage layer 18 is formed on the channel layer 12 side at the interface between the electron supply layer 13 and the channel layer 12.

As a result, a large amount of electrons flow through the channel layer lz, which has a thickness of several tens of A0 near the interface, where there are few impurity ions. Therefore, impurity ion scattering, which is one of the major factors that limit electron mobility, is reduced, and high mobility can be achieved.

In the case of Figure 2, an electron accumulation layer is used at a single hetero interface between a GaAs layer and a Ga AlAs layer, but it is also possible to use multiple hetero interfaces between a GaAs layer and a Ga AI As layer. For cases where R, Din
gle et al., Appi@Phys, Lett, 33,
6B! y (1978) and T.

J, Drurrtnond et al., J., Appl, P.
hys, 53 (2), 1023 (1982), etc.

Problems to be Solved by the Invention However, in such a compound semiconductor device, the channel layer epitaxially grown on the semi-insulating substrate is quite thick, approximately 100A0, and this layer grows in a planar shape with a periodic structure. In this case, the matching condition of the lattice spacing at the hetero interface becomes a problem. Generally, the lattice mismatch rate of the heterointerface between A and B2 materials is expressed by the following formula.

Lattice mismatch rate In order to grow a uniform defect-free epitaxial layer at the heterointerface, the above lattice mismatch rate should be approximately 0.396.
It is necessary to keep it below. For this reason, of course, once the substrate is determined, the composition of the epitaxial layer is also determined, and there is a drawback that it is not possible to maintain a large difference in energy gap at the heterointerface.

FIG. 3 shows the relationship between energy gap and lattice constant for major compound semiconductors.

Since there are only GaAs substrates and InP substrates as semi-insulating substrates, in order to achieve lattice matching at both the interface with the epitaxial growth layer and the hetero interface between the channel layer and the electron supply layer, it is necessary to use the former. For GaAs channel layer and Gax Al +-x
As or AI As electron supply layer, I for the latter
no,ss GaO,47As channel layer and In
(1, sg A structure in which a Gao4sAs electron supply layer is formed is adopted.

However, when the channel layer is made of GaAs and the electron supply layer is made of klAs, as is clear from Fig. 3, the difference in energy gap at the heterointerface between the two is as follows.
It becomes only about 0.7 eV.

The size of the energy discontinuity of the conductor at the actual heterointerface is determined by the difference in the energy gap.
This value is multiplied by a correction coefficient called the 2000 correction coefficient, and this means that the aforementioned effect of confining electrons in the secondary electron storage layer in the channel layer decreases, and the degree of formation of the secondary electron storage layer decreases. This has the disadvantage of lowering electron mobility at the heterointerface. In particular, the decrease in electron mobility in the two-dimensional electron storage layer becomes more pronounced as the temperature approaches room temperature.

The present invention provides a compound semiconductor device that suppresses the decrease in the electron confinement effect in the two-dimensional electron storage layer at room temperature and forms a heterointerface having high electron mobility even at room temperature. That is.

Means to Solve the Problems By using the MBE growth method or metal organic growth method, it is possible to epitaxially grow compound semiconductor thin films with different lattice constants without introducing defects such as dislocations into the thin films. be. Furthermore, when compound semiconductors with different lattice constants are epitaxially grown to a thin enough thickness to prevent defects such as dislocations, the crystal lattice is tetragonally deformed due to elastic strain near the interface.
45. Jff9.

(1974) 8789, etc.

Based on the above knowledge, the present inventor makes the following proposal.

(1) In order to select a material that increases the difference in energy gap at the heterointerface between the channel layer and the electron supply layer, the constraint of keeping the lattice mismatch rate low in the conventional technology is removed.

(2) If the lattice mismatch rate is large, make the epitaxial layer thin to prevent defects such as dislocations.

(3) To increase current capacity when using thin films, use a laminated structure of thin films.

(4) Applying tetragonal deformation of the crystal lattice based on elastic strain near the interface to the channel layer to increase electron mobility under high electric field application.

By doing this, a compound semiconductor device with high electron mobility can be obtained even at room temperature.

From the above, AI with InAs added to the channel layer and n-type impurities added to the electron supply layer! When As is selected, the difference in energy gap is approximately 1.8 eV, as is clear from Figure 3.
and about 0.7e of conventional GaAs-Aj7As
V can take on much larger values. Therefore, it is possible to suppress a reduction in the electron confinement effect within the two-dimensional electron storage layer at room temperature.

Next, the lattice mismatch rate between InAs and Aj' As is approximately 7%, but in this case the thickness of each layer is approximately 50^ (in terms of the number of atomic planes, in the case of InAs, it is approximately 16 atomic planes A/in the case of As, it is approximately 18 atomic planes), it is possible to alternately stack InAs and A/As without introducing lattice misalignment dislocations.

Furthermore, the lattice constant of InAs (approximately 0.65A) is
Since the lattice constant of As (approximately 5.65A) is larger than ζ, near the interface between the two, due to elastic strain,
The atomic arrangement within the InAs crystal is as shown in Figure 4.
Figure 4 (a) shows the structure when there is no original elastic strain.
), the crystal lattice undergoes elastic tetragonal deformation as shown in FIG. 4(b). At this time, the n-type impurity is A
A two-dimensional electron storage layer can be formed in InAs by doping lAs to form an electron supply layer and alternately stacking Evitaky thin layers using InAs as a channel layer. This two-dimensional electron storage layer is parallel to the heterointerface, and electrons traveling therein travel in the X direction. The degree of lattice scattering due to atomic vibration in the Y direction is as shown in Figure 4 (b), compared to the case in Figure 4 (a) where there is no elastic strain, the atomic spacing in the Y direction is wider due to elastic strain. is smaller. As a result, lattice scattering, which is an electron scattering mechanism at room temperature, can also be reduced, and a device with high electron mobility can be realized.

Embodiment FIG. 1 is a schematic cross-sectional view of a field effect transistor (hereinafter abbreviated as FETJ) which is an embodiment of a compound semiconductor device according to the present invention.

The FET shown in FIG.
InAs layer (4OA thickness) 2 formed using the E growth method
and AA' As layers (40 years) 3 are alternately stacked. The AlAs layer has n
Si is doped as a type impurity. The number of each layer is InAs layer, AI! Each of the As layers is formed with 20 layers, and the thickness of the channel layer is 0.16 μm.

The carrier density of the InAs layer (non-doped) is approximately 8
101-"3. AA' As layer is 1X101'7c
It is IIt-3.

On the outermost surface of the epitaxial layer formed using the MBE growth method, a source electrode 4 and a drain electrode 5 are provided using an Au Ge Ni alloy so as to form an ohmic contact with the channel layer. . When forming an ohmic junction, an AuGe Ni alloy was deposited and then alloyed at 400°C. At that time, A
U and Ge atoms diffuse into the channel layer, and in the diffused region 7.7', the periodic structure of InAs and klAs is destroyed and becomes a mixed crystal of InO, 51sJO, sAs, so it is easy to form an electrode. It is possible to form an ohmic junction with. Furthermore, a gate electrode 6 is provided on the outermost surface of the sample by partially forming an oxide film 8 on the outermost surface of the epitaxial layer formed by the MBE growth method and then depositing kl.

In the above FET structure, the InAs layer is the fourth
As shown in Figure (b), the crystal structure is elastically deformed into a tetragonal system, and the interface between InAs and AI As is
MTGaAs-GaxAl! 1->(There is a larger energy discontinuity than in the As system, and kl
Because only the As layer is doped with Si, the conventional GaAs-Gax AA
'Compared to the t-xAs system, a two-dimensional electron storage layer with a greater confinement effect is formed only in the InAs layer.

In such a FET structure, by controlling the voltage applied to the gate electrode, the 0.16 μm below the gate electrode can be
The degree of depletion of the thick channel layer could be controlled, and an FET with better switching speed at room temperature than a conventional FET using the GaAs-Gax A77t-xAs system was obtained.

Effects of the Invention According to the compound semiconductor device of the present invention, InAs and AI!
In is elastically deformed into a tetragonal crystal by stacking Al thin film layers of As alternately and adding n-type impurities to AI As.
A two-dimensional electron storage layer can be formed on the As side.

Since the energy gap difference between InAs and klAs is larger than that between conventional GaAs and Gax AJ'x-xAS, the effect of confining electrons in the two-dimensional electron storage layer is large even at room temperature, and The number of electrons traveling through the two-dimensional electron storage layer with less scattering of impurities increases, and the electron mobility increases. Also, the lattice constant of InAs is AI! Because it is significantly larger than As, it causes elastic tetragonal deformation in the InAs layer, reducing lattice scattering when electrons move in the direction parallel to the interface through the secondary electron storage layer formed within the InAs layer. This effect also increases electron mobility. Therefore, a semiconductor device that operates faster than conventional compound semiconductor devices can be realized.

[Brief explanation of drawings]

FIG. 1 is a schematic cross-sectional view showing a preferred embodiment of the device of the present invention, FIG. 2 is a schematic cross-sectional view of a conventional high electron mobility transistor, and FIG. 3 is a schematic cross-sectional view of a conventional high electron mobility transistor. FIG. 4(a) is a graph showing the relationship between
A schematic diagram of a crystal structure (cubic crystal) without elastic strain, and FIG. 4(b) is a schematic diagram of a crystal structure deformed into a tetragonal crystal due to elastic strain. (Main reference numbers) 1-m-semi-insulating InP substrate, 2. - epitaxial InAs layer, 3---Si-doped epitaxial Aj' As layer, 4 and 5---source and drain electrodes, 6---gate electrode, 7 and 7'1.
・A region where the periodic structure is broken and becomes a mixed crystal when the AuGe Ni electrode is alloyed, 8--Oxide film, 10--Semi-insulating GaAs substrate, l 1--GaAs buffer layer, 12- --GaAs channel layer, l
3--electron supply layer, 14-m-a layer made of a semiconductor containing a high concentration of P-type impurities and having a large electron affinity;
15-m-gate electrode, 16--alloyed region, 17-
--source electrode and drain electrode, 18. - Secondary electron storage layer. ,゛″:″ Agent Patent Attorney Senior Tetsuji゛″′・;”−'y
'Ly, y' LATTICE C0N5TANT (In) Rod 3 figure YaijA': J'lJY: In
As 't-A/As /) A+=ti Directional Procedures Amendment Form August 7, 1985 Michibe Uga, Commissioner of the Patent Office 1, Indication of the Case 1985 Patent Application No. 119328 2, Invention Name of Compound Semiconductor Device & Relationship with the Person Making Amendment Case Patent Applicant Address 5-15 Kitahama, Higashi-ku, Osaka Name (21
3) President of Sumitomo Electric Industries Co., Ltd. Tetsubetsu Yojo Agent Address: 7, Sumitomo Electric Industries Co., Ltd., 1-1-3 Shimaya, Konohana-ku, Osaka, Japan Contents of the amendment (1) Page 4, line 18 of the specification From page 5, line 3 of the specification, ``However, such...'' poses a problem. As a currently useful semi-insulating compound substrate that is configured to form a channel layer with a lattice constant as equal as possible,
Since only GaAs and InP are present, the types of materials that can be used for the channel layer are severely limited. ” he corrected. (2) The two-mentioned lattice--ring--is required from page 5, line 9 of the specification to page 5, line 10 of the specification. It is necessary to make the absolute value of the lattice mismatch rate expressed by ``rh'' as small as possible. ” he corrected. (3) "Increase high electric field application..." from page 8, line 5 of the specification to page 8, line 6 of the specification: 1 (4)
From page 8, line 9 of the specification to line 10 of the specification, ``the electron supply layer has a mouth-type impurity'' is corrected to ``the electron supply layer has an n-type impurity''. (5) [(approximately 0.65A0)” on page 9, line 2 of the specification
(approximately 6.05A”) J. (6) Correct “Epitaxy thin film” on page 9, line 10 of the specification to “Epitaxy thin film J.” (7) Figure 1 of the drawings is attached as an attached sheet. Correct as shown in Figure 1.

Claims (3)

[Claims] (1) In a semiconductor device having an active layer with a multilayer thin film structure on a semi-insulating substrate, the active layer is composed of an InAs thin film and an AlAs thin film doped with n-type impurities, and these are alternately stacked to accumulate secondary electrons. A compound semiconductor device characterized in that a layer is formed within an InAs thin film. (2) The total number of layers of the compound semiconductor multilayer thin film layer is 4 to 1.
2. The compound semiconductor device according to claim 1, wherein the compound semiconductor device is within a range of 000 layers. (3) The thickness of each layer of the compound semiconductor multilayer thin film layer is 3
2. The compound semiconductor device according to claim 1, wherein the atomic plane is within a range of 16 to 16 atomic planes.