JPH0328063B2 - - Google Patents

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Publication number
JPH0328063B2
JPH0328063B2 JP5202285A JP5202285A JPH0328063B2 JP H0328063 B2 JPH0328063 B2 JP H0328063B2 JP 5202285 A JP5202285 A JP 5202285A JP 5202285 A JP5202285 A JP 5202285A JP H0328063 B2 JPH0328063 B2 JP H0328063B2
Authority
JP
Japan
Prior art keywords
layer
compound semiconductor
thin film
crystal
lattice
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP5202285A
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Japanese (ja)
Other versions
JPS61210676A (en
Inventor
Juichi Matsui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP5202285A priority Critical patent/JPS61210676A/en
Priority to CA000504069A priority patent/CA1256590A/en
Priority to EP86103425A priority patent/EP0196517B1/en
Priority to AU54742/86A priority patent/AU577934B2/en
Priority to DE8686103425T priority patent/DE3672360D1/en
Priority to KR1019860001897A priority patent/KR860007745A/en
Publication of JPS61210676A publication Critical patent/JPS61210676A/en
Publication of JPH0328063B2 publication Critical patent/JPH0328063B2/ja
Granted legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025Channel region of field-effect devices
    • H01L29/1029Channel region of field-effect devices of field-effect transistors
    • H01L29/1033Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025Channel region of field-effect devices
    • H01L29/1029Channel region of field-effect devices of field-effect transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/15Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
    • H01L29/151Compositional structures
    • H01L29/152Compositional structures with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
    • H01L29/155Comprising only semiconductor materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/80Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Junction Field-Effect Transistors (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、化合物半導体装置に関する。更に詳
しくは本発明は、格子定数の異なる3種類の化合
物半導体薄膜層を交互に積層させて、既存のいわ
ゆる混晶化合物半導体と異なるエネルギーバンド
構造を実現することにより、高電界印加状態にお
ける電子移動度を大きくした化合物半導体装置に
関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a compound semiconductor device. More specifically, the present invention achieves an energy band structure different from that of existing so-called mixed crystal compound semiconductors by alternately stacking three types of compound semiconductor thin film layers with different lattice constants, thereby improving electron transfer under high electric field conditions. The present invention relates to a compound semiconductor device with a high degree of performance.

従来の技術 化合物半導体デバイス、特に電子デバイスの製
法として、薄い一様な層の成長、成分元素組成比
の制御の容易さからエピタキシヤル成長方法が一
般的に利用されている。なかでも、最近特に注目
されている技術として、分子線エピタキシヤル成
長方法(以下簡単のために「MBE成長法」とい
う)が知られている。例えばW.T.Tsangにより
日経エレクトロニクスNo.308163(1983)において、
MBE成長法並びに薄膜周期構造を利用したデバ
イスが詳細に説明されている。
BACKGROUND OF THE INVENTION Epitaxial growth methods are generally used as methods for manufacturing compound semiconductor devices, particularly electronic devices, because of the ease of growing thin, uniform layers and controlling the composition ratio of component elements. Among these, a molecular beam epitaxial growth method (hereinafter referred to as "MBE growth method" for simplicity) is known as a technique that has recently attracted particular attention. For example, in Nikkei Electronics No. 308163 (1983) by WTTsang,
The MBE growth method and devices using thin film periodic structures are explained in detail.

このMBE成長法に従えば、結晶成長速度を単
原子面レベルで制御することができ(J.P.van
der Ziel他、J.Appl.Phys.48(1977)P3018)、さ
らには、反射型電子線回折法を併用すれば1原子
面の組成をも正確に制御することができる(J.H.
Neave他、Appl.Phys.A31、1(1983))。このよ
うなMBE法を用いることにより、第3図に示す
ような高電子移動度トランジスタ(以下、
HEMTと略す)を製造することが可能となる。
By following this MBE growth method, the crystal growth rate can be controlled at the monatomic level (JPvan
der Ziel et al., J. Appl. Phys. 48 (1977) P3018), and furthermore, the composition of even a single atomic plane can be precisely controlled by using reflection electron diffraction (J.H.
Neave et al., Appl. Phys. A31, 1 (1983)). By using such an MBE method, a high electron mobility transistor (hereinafter referred to as
This makes it possible to manufacture HEMT (abbreviated as HEMT).

なお、従来の化合物半導体を用いたマイクロ波
素子については、たとえば特開昭59−4085号およ
び特開昭58−147169号公報に記されている。
Note that microwave elements using conventional compound semiconductors are described in, for example, Japanese Patent Laid-Open No. 59-4085 and Japanese Patent Laid-Open No. 58-147169.

第3図に示したHEMT構造は、半絶縁性GaAs
基板1を有し、その基板1の上には、バツフア層
として機能するGaAs層2が形成され、更にその
上に、チヤンネル層をなすアンドープのGaAs層
3が形成されている。そして、そのGaAs層3上
には、n−GaxAl1-xAsのような高い不純物濃度
の電子供給層4が形成され、その中央には、高濃
度にp型不純物を含有し、大きな電子親和力を有
する半導体よりなる層5が設けられ、そして、そ
の層5の上にはゲート電極6が形成されている。
更に、層5を挟む電子供給層4の表面領域7は合
金化され、その上にソース及びドレイン電極8が
形成されている。
The HEMT structure shown in Figure 3 is a semi-insulating GaAs
The device has a substrate 1, on which is formed a GaAs layer 2 which functions as a buffer layer, and further on which is formed an undoped GaAs layer 3 which serves as a channel layer. Then, on the GaAs layer 3, an electron supply layer 4 with a high impurity concentration such as n-Ga x Al 1-x As is formed, and in the center thereof, a large A layer 5 made of a semiconductor having electron affinity is provided, and a gate electrode 6 is formed on the layer 5.
Furthermore, the surface region 7 of the electron supply layer 4 sandwiching the layer 5 is alloyed, and the source and drain electrodes 8 are formed thereon.

このような半導体装置において、ゲート電極6
に適当なバイアス電圧を印加すると、電子供給層
4とチヤンネル層3との界面におけるチヤンネル
層3側に、二次元電子ガス9が形成される。この
結果、不純物イオンの少ないチヤンネル層3内の
界面近傍数10Å厚のところを、多量の電子が流れ
ることになる。従つて、電子移動度を制限する1
つの大きな要因である不純物イオン散乱が少な
く、高移動度を実現することができる。
In such a semiconductor device, the gate electrode 6
When an appropriate bias voltage is applied to the electron supply layer 4 and the channel layer 3, a two-dimensional electron gas 9 is formed on the channel layer 3 side at the interface between the electron supply layer 4 and the channel layer 3. As a result, a large amount of electrons flows through the channel layer 3, which has a thickness of several tens of angstroms near the interface, where there are few impurity ions. Therefore, 1 which limits the electron mobility
There is little impurity ion scattering, which is one of the major factors, and high mobility can be achieved.

発明が解決しようとする問題点 しかしながら、このような化合物半導体装置に
おいては、二次元電子ガスにおける電子移動度の
印加電界強度依存性が極めて大きく、低電界の場
合には高移動度を実現できるが、高電界の場合に
はその移動度が著しく低下してしまう。このよう
な現象は、例えば、M.Inoue他、J.J.A.P.22 357
(1983)の記述されている。また、その1例を上
記したマイクロ波素子のようなGaAs/n−Gax
Al1-xAs構造の場合について示すと、第4図の点
線の如くなる。
Problems to be Solved by the Invention However, in such compound semiconductor devices, the dependence of electron mobility in the two-dimensional electron gas on the applied electric field strength is extremely large, and although high mobility can be achieved in the case of a low electric field, , in the case of a high electric field, its mobility decreases significantly. Such a phenomenon has been described, for example, by M. Inoue et al., JJAP 22 357
(1983). In addition, one example is the GaAs/n-Ga x
The case of the Al 1-x As structure is shown by the dotted line in FIG.

このような高電界印加状態における半導体内で
の電子散乱機構としては、インターバレイ(谷
間)散乱やインパクトイオナイゼーシヨンあるい
はフオノン(格子振動)散乱などが挙げられる。
そのため、一般に超高周波トランジスタにおいて
チヤンネル層として用いられる半導体結晶は、以
下の特性の向上が要求される。
Electron scattering mechanisms within the semiconductor under such high electric field application include intervalley scattering, impact ionization, and phonon (lattice vibration) scattering.
Therefore, semiconductor crystals generally used as channel layers in ultra-high frequency transistors are required to have the following improved characteristics.

インターバレイ散乱を起こりにくくするため
に、k空間での谷間のあいだのエネルギー差△
Eが大きいこと。
In order to make intervalley scattering less likely to occur, the energy difference between the valleys in k-space is
E is large.

インパクトイオナイゼーシヨンを起こりにく
くするために、エネルギーギヤツプEgが大き
いこと。
The energy gap E g must be large to make impact ionization less likely to occur.

キヤリア電子の運動エネルギーのフオノン散
乱による損失を小さくするために、有効質量
m*が小さいこと。
In order to reduce the loss of carrier electron kinetic energy due to phonon scattering, the effective mass
m * is small.

谷間間のエネルギー差△E、エネルギーギヤツ
プEgなどのパラメータについては、GaAs結晶の
エネルギーバンド構造を例に挙げるならば、第5
図の如くである。また、有効質量m*はエネルギ
ーバンド構造との間に、 1/m*=1/〓2・d2E(K)/dk2 のような関係がある。
For parameters such as the energy difference ΔE between valleys and the energy gap E g , taking the energy band structure of a GaAs crystal as an example, the fifth
As shown in the figure. Further, the effective mass m * has a relationship with the energy band structure as follows: 1/m * =1/〓 2 ·d 2 E(K)/dk 2 .

しかしながら、従来の化合物半導体装置におい
ては、実質的な厚さを持つ各層の化合物半導体
は、均一な組成構造を追求されているために、上
記した△E、Eg、m*は自ずと決まつていた。そ
のために、上記した散乱の解消には壁があり、高
電界印加状態において高い電子移動度が実現でき
なかつた。
However, in conventional compound semiconductor devices, the compound semiconductor in each layer with a substantial thickness is sought to have a uniform composition structure, so the above-mentioned ΔE, E g and m * are naturally determined. Ta. Therefore, there is a barrier to eliminating the above-mentioned scattering, and high electron mobility cannot be achieved in a state where a high electric field is applied.

そこで、本発明は、上記した電子散乱の影響を
抑えて、高電界印加状態においても高い電子移動
度を有する化合物半導体装置を提供せんとするも
のである。
Therefore, the present invention aims to provide a compound semiconductor device that suppresses the above-mentioned effects of electron scattering and has high electron mobility even when a high electric field is applied.

問題点を解決するための手段 そこで、本発明者は、上記目的のために電子散
乱の問題を種々研究した。
Means for Solving the Problems Therefore, the present inventor conducted various studies on the problem of electron scattering for the above purpose.

上記説明からわかるように、超高周波トランジ
スタにおいて、チヤンネル層として用いられる化
合物半導体結晶は、そのエネルギーバンド構造を
変えることにより、高電界印加状態でのインター
バレイ散乱やインパクトイオナイゼーシヨンによ
る散乱を低下させ、あるいは電子の有効質量を小
さくすることによつて、高電界印加状態における
移動度を大きくすることができる。
As can be seen from the above explanation, the compound semiconductor crystal used as the channel layer in ultra-high frequency transistors reduces scattering due to intervalley scattering and impact ionization when a high electric field is applied by changing its energy band structure. The mobility in a high electric field application state can be increased by increasing or decreasing the effective mass of electrons.

一方、半導体のエネルギーバンド構造に関する
LCAO理論によると、エネルギーバンド構造を計
算する際に重要となるハミルトニアンの非対角行
列要素VLLnは、 VLLn=ηLLn・〓2/m0・d2 で表わされる。ただし、l、l′はそれぞれ結晶を
構成する隣接原子の最外殻p軌道の方位量子数、
mは同じく磁気量子数であり、dは隣接原子の核
間距離、m0は電子質量、ηLLnは結晶構造に依存
した係数、〓=h/2π(h:プランク定数)であ
る。
On the other hand, regarding the energy band structure of semiconductors,
According to LCAO theory, the off-diagonal matrix element V LLn of the Hamiltonian, which is important when calculating the energy band structure, is expressed as V LLnLLn・〓 2 /m 0・d 2 . However, l and l′ are the azimuthal quantum numbers of the outermost p-orbitals of adjacent atoms constituting the crystal, respectively,
Similarly, m is the magnetic quantum number, d is the internuclear distance between adjacent atoms, m 0 is the electron mass, η LLn is a coefficient depending on the crystal structure, 〓=h/2π (h: Planck's constant).

また、ハミルトニアンの対角行列要素εs c、εs a
εp c、εp aなどは、相対的には孤立原子の項値に関
連したものである。ただし、εs cは極性化合物半
導体の陽イオン原子S軌道の項値に関連してお
り、同様に、εs aは陰イオン原子S軌道の項値に、
εp cは陽イオン原子P軌道の項値に、εp aは陰イオ
ン原子P軌道の項値にそれぞれ関連している。
Also, the diagonal matrix elements ε s c , ε s a ,
ε p c , ε p a , etc. are relatively related to the term value of an isolated atom. However, ε s c is related to the term value of the cation atomic S orbit of the polar compound semiconductor, and similarly, ε s a is related to the term value of the anion atomic S orbit,
ε p c is related to the term value of the cation atomic P orbital, and ε p a is related to the term value of the anion atomic P orbital.

この既成理論(たとえば、W.A.Harrison、
Electronic Structure and the Properties of
Solids、1980参照)によれば、結晶構造または原
子配列を変えることにより、すなわち化合物半導
体結晶中における隣接原子の核間距離dならびに
隣接原子の種類を変えることにより、ハミルトニ
アンの行列要素VLLn、εs a、εs c、εp a、εp cを変え
ることができる。このことは、結晶構造または原
子配列を変えることにより化合物半導体のエネル
ギーバンド構造を変えることができることを意味
する。
This established theory (e.g. WAHarrison,
Electronic Structure and the Properties of
Solids, 1980), by changing the crystal structure or atomic arrangement, that is, by changing the internuclear distance d of adjacent atoms in a compound semiconductor crystal as well as the type of adjacent atoms, the matrix element V LLn of the Hamiltonian can be , ε sa , ε sc , ε p a , and ε p c can be changed. This means that the energy band structure of a compound semiconductor can be changed by changing the crystal structure or atomic arrangement.

一方、最近の化合物半導体結晶成長技術におい
ては、上記したように、分子線エピタキシヤル成
長法(MBE法)や有機金属気相成長法
(MOCVD、MOVPEなどと略す)などのように、
成長層厚の制御が単原子層程度にまで向上してお
り、現にGaAsとAlAsを用いて単原子レベルで交
互に積層することに成功している(A.C.
Gossard、Thin Solid Films 57、3(1979))。
On the other hand, as mentioned above, recent compound semiconductor crystal growth techniques include molecular beam epitaxial growth (MBE) and metal organic vapor phase epitaxy (abbreviated as MOCVD, MOVPE, etc.).
Control of the growth layer thickness has been improved to the level of a single atomic layer, and we have actually succeeded in stacking GaAs and AlAs alternately at the single atomic level (AC
Gossard, Thin Solid Films 57 , 3 (1979)).

しかしながら、GaAsとAlAsとを交互に積層し
た場合は、格子不整が約0.3%と極めて小さく、
ゆえにこれら2種類の層を交互に積層することに
よつて生じる結晶格子の歪みは小さい。このこと
は、従来のGaxAl1-x混晶に比べて、原子配列の
みが若干変化し、結晶構造はほとんど変化してい
ないことを意味し、ゆえにエネルギーバンド構造
も大きな変化を示さない。
However, when GaAs and AlAs are stacked alternately, the lattice mismatch is extremely small at about 0.3%.
Therefore, distortion of the crystal lattice caused by alternately stacking these two types of layers is small. This means that compared to the conventional Ga x Al 1-x mixed crystal, only the atomic arrangement has changed slightly, and the crystal structure has hardly changed, and therefore the energy band structure does not show a large change.

ところが、2種類の層の格子不整を約1.5%と
大きくした場合には、エネルギーギヤツプEg
変化が観測されている(G.C.Osbourn他、J.
Appl.Phys.48(1977)3018)。すなわち、このよ
うに格子不整が比較的大きい場合には、原子配列
だけではなく結晶構造の変化も生じ、エネルギー
バンド構造の比較的大きな変化が観測されてい
る。
However, when the lattice misalignment of the two types of layers is increased to approximately 1.5%, a change in the energy gap E g has been observed (GCOsbourn et al., J.
Appl. Phys. 48 (1977) 3018). That is, when the lattice misalignment is relatively large like this, not only the atomic arrangement but also the crystal structure changes, and a relatively large change in the energy band structure is observed.

しかしながら、この報告の場合においては、各
層厚が100〜200Åと厚くなつており、2種類の層
の界面近傍における結晶格子の歪んだ部分に比べ
て、結晶格子の歪んでいない従来通りの結晶構造
をとつている部分の方が極めて多くなつている。
このため、エネルギーバンド構造についてもその
ほとんどが、各層の従来通りの結晶構造に起因し
たエネルギーバンド構造によつて支配されてお
り、結晶格子の歪んだ部分からの寄与は小さい。
このように結晶格子の歪みが、各層の界面近傍に
限られているという事実は、J.M.Brown他、A.
P.L.43(1983)863に記されている。さらに、こ
のような格子不整に基く歪みによつて結晶構造が
変化するという直接的な結果は、J.A.P.45、No.
9、(1974)3789に記されている。
However, in the case of this report, the thickness of each layer is as thick as 100 to 200 Å, and compared to the distorted part of the crystal lattice near the interface between the two types of layers, the conventional crystal structure with an undistorted crystal lattice is observed. There are an extremely large number of areas that have .
Therefore, most of the energy band structure is dominated by the energy band structure resulting from the conventional crystal structure of each layer, and the contribution from distorted portions of the crystal lattice is small.
The fact that the distortion of the crystal lattice is limited to the vicinity of the interface between each layer is explained by JMBrown et al., A.
PL 43 (1983) 863. Furthermore, the direct result that the crystal structure changes due to distortion based on such lattice misalignment is reported in JAP 45 , No.
9, (1974) 3789.

しかし、層の種類が2種類の場合においてはこ
れらを交互に積層化させた結晶と、従来の混晶結
晶との間の原子配列の相違は大きくない。
However, when there are two types of layers, the difference in atomic arrangement between a crystal in which these layers are alternately laminated and a conventional mixed crystal is not large.

以上のことから、格子不整の大きな3種類以上
の化合物半導体薄膜層を交互に積層させることに
より、成長層全体にわたつて結晶構造と原子配列
をともに2種類の層の場合に比べて著しく大きく
変えることができる。
From the above, by alternately stacking three or more types of compound semiconductor thin film layers with large lattice mismatches, both the crystal structure and atomic arrangement throughout the growth layer can be significantly changed compared to the case of two types of layers. be able to.

なお、化合物半導体薄膜層を交互に積層させた
半導体装置という点で類似の報告は、たとえば、
特開昭59−76468号公報あるいはT.Yao、J.J.A.
P.22(1983)L680にあるが、それらは、エネル
ギーバンド構造を改良したものでは全くない。
Note that similar reports regarding semiconductor devices in which compound semiconductor thin film layers are alternately laminated include, for example,
JP-A-59-76468 or T. Yao, JJA
P. 22 (1983) L680, but they do not improve the energy band structure at all.

本発明は、かかる知見に基づく研究の結果なさ
れたものである。すなわち、本発明によるなら
ば、基板と、該基板上に形成されたチヤンネル層
と、該チヤンネル層の上に形成されたシヨツトキ
ー接合のゲート電極と、該ゲート電極の両側にお
いて該ゲート電極から離れて前記チヤンネル層の
上に形成されたオーミツク接合のソース電極及び
ドレイン電極とを具備しており、前記チヤンネル
層が、格子定数の異なる3種類の化合物半導体薄
膜層を交互に積層して構成され、前記化合物半導
体薄膜層の各層の厚さが1〜100原子面の範囲内
にあり、前記格子定数の相違が、0.3%以上13%
以下の範囲にあることを特徴とする化合物半導体
装置が提供される。
The present invention was made as a result of research based on such knowledge. That is, according to the present invention, a substrate, a channel layer formed on the substrate, a Schottky junction gate electrode formed on the channel layer, and a gate electrode on both sides of the gate electrode separated from the gate electrode. The channel layer includes an ohmic junction source electrode and a drain electrode formed on the channel layer, and the channel layer is configured by alternately stacking three types of compound semiconductor thin film layers having different lattice constants, and The thickness of each layer of the compound semiconductor thin film layer is within the range of 1 to 100 atomic planes, and the difference in the lattice constant is 0.3% or more and 13%.
A compound semiconductor device is provided that is characterized by being within the following range.

作 用 以上のような化合物半導体装置において、チヤ
ンネル層をなす各薄膜層の化合物半導体は、互い
に格子定数が異なり且つ極めて薄いので、各層の
実質的部分にわたつてエネルギーバンド構造が変
化し、その結果、高電界印加状態でのチヤンネル
層内における電子輸送過程でのインターバレイ散
乱やインパクトイオナイゼーシヨンによる散乱を
低下させあるいは電子の有効質量を減少させる。
従つて、高電界印加状態でのチヤンネル層におけ
る電子移動度が高く維持される。
Function In the above-described compound semiconductor device, the compound semiconductors in each thin film layer forming the channel layer have different lattice constants and are extremely thin, so the energy band structure changes over a substantial portion of each layer. , to reduce scattering due to intervalley scattering or impact ionization during the electron transport process in the channel layer under high electric field application, or to reduce the effective mass of electrons.
Therefore, the electron mobility in the channel layer is maintained at a high level when a high electric field is applied.

実施例 以下に図面を参照して本発明について詳細に説
明する。
EXAMPLES The present invention will be described in detail below with reference to the drawings.

第1図は、本発明による化合物半導体装置の実
施例を図解した断面図である。なお、第1図は、
本発明を電界効果トランジスタ(以下FETと略
す)として実施した例を示している。
FIG. 1 is a cross-sectional view illustrating an embodiment of a compound semiconductor device according to the present invention. In addition, Figure 1 shows
An example in which the present invention is implemented as a field effect transistor (hereinafter abbreviated as FET) is shown.

第1図に示すFETは、半絶縁性InP基板10上
に、InAsとGaAs、InSbをそれぞれ数原子層づつ
交互にそれぞれ約80層づつ積層させた結晶構造を
有するInxGa1-xAsySb1-y化合物半導体結晶多層薄
膜層11がFETのチヤンネル層として形成され
ている。その多層薄膜層11の全体の膜厚は
0.15μmでありInAs層は10Åの厚さで、GaAs層
は20Åの厚さで、InSb層は3.5Åの厚さである。
なお、このような多層薄膜層11は、半絶縁性の
InP基板10上にMBE成長法を用いて形成した。
The FET shown in FIG . 1 has a crystal structure in which about 80 layers each of InAs, GaAs, and InSb are alternately stacked on a semi-insulating InP substrate 10 , each with several atomic layers each . An Sb 1-y compound semiconductor crystal multilayer thin film layer 11 is formed as a channel layer of the FET. The total thickness of the multilayer thin film layer 11 is
The InAs layer is 10 Å thick, the GaAs layer is 20 Å thick, and the InSb layer is 3.5 Å thick.
Note that such a multilayer thin film layer 11 is made of semi-insulating material.
It was formed on an InP substrate 10 using the MBE growth method.

さらに、多層薄膜層11の表面には、AuGeNi
オーミツク接合電極12を蒸着し、ソースとドレ
イン電極を形成した。また、Alシヨツトキー接
合電極13を蒸着し、ゲート電極を形成した。
Furthermore, on the surface of the multilayer thin film layer 11, AuGeNi
Ohmic junction electrodes 12 were deposited to form source and drain electrodes. Further, an Al shot key junction electrode 13 was deposited to form a gate electrode.

AuGeNiオーミツク電極12を形成する際の蒸
着ならびに合金処理によつて、Au原子が化合物
半導体結晶多層薄膜層11中に拡散していく。こ
れによつて、化合物半導体結晶多層薄膜層11内
の積層構造の周期性が乱れ、この領域14におけ
る結晶構造は、従来のInxGa1-xAsySb1-y混晶結晶
と同一になつてしまう。この結果、この領域での
エネルギーバンド構造も、従来のInxGa1-xAsy
Sb1-y混晶結晶と同一になり、オーミツク接合を
形成することに何ら弊害は生じなかつた。このよ
うな拡散によつて化合物半導体多層薄膜層の積層
構造の周期性が破壊されるという類似の現象は、
すでにN.Holonyak他、A.P.L.39(1981)102な
どで発表されている。
Au atoms are diffused into the compound semiconductor crystal multilayer thin film layer 11 by vapor deposition and alloying treatment when forming the AuGeNi ohmic electrode 12. As a result, the periodicity of the laminated structure in the compound semiconductor crystal multilayer thin film layer 11 is disturbed, and the crystal structure in this region 14 is the same as that of the conventional In x Ga 1-x As y Sb 1-y mixed crystal. I get used to it. As a result, the energy band structure in this region also changes from the conventional In x Ga 1-x As y
It became the same as the Sb 1-y mixed crystal, and no adverse effects occurred in forming an ohmic junction. A similar phenomenon in which the periodicity of the laminated structure of a compound semiconductor multilayer thin film layer is destroyed by such diffusion is as follows.
It has already been published in N. Holonyak et al., APL 39 (1981) 102, etc.

第1図に示すソース電極12、ドレイン電極1
2、ゲート電極13などについては、従来の
FET構造作製時に行なわれている従来技術を用
いることにより、FETとしての機能を有するこ
とも確認できた。
Source electrode 12 and drain electrode 1 shown in FIG.
2. Regarding gate electrode 13 etc., conventional
By using the conventional technology used to fabricate the FET structure, we were able to confirm that it functions as an FET.

さらに、第1図における化合物半導体結晶多層
薄膜層11において、結晶構造やエネルギーバン
ド構造が同一組成を有するInxGa1-xAsySb1-y混晶
結晶とは全く異なることについても、X線回折や
光吸収などの測定を行なうことによつて確認でき
た。この結果、第2図に示すように高電界領域に
おける電子移動度が、同一組成を有する従来の
InxGa1-xAsySb1-y混晶の場合に比べて約5倍に向
上した。
Furthermore , regarding the fact that the compound semiconductor crystal multilayer thin film layer 11 in FIG. 1 has a crystal structure and an energy band structure that are completely different from the In This was confirmed by measurements such as line diffraction and optical absorption. As a result, as shown in Figure 2, the electron mobility in the high electric field region is lower than that of the conventional one with the same composition.
The improvement was approximately five times that of the In x Ga 1-x As y Sb 1-y mixed crystal.

なお、上記実施例と同様な構成で、化合物半導
体結晶多層薄膜層11の各薄膜層の厚さを1原子
面から100原子面の間で変えたところ、従来例に
比較しての差に相違はあつたが、同様な結果が得
られた。但し、同一組成の薄膜層は、多層薄膜層
全体にわたつて同一の厚さが好ましい。
In addition, when the thickness of each thin film layer of the compound semiconductor crystal multilayer thin film layer 11 was changed from 1 atomic plane to 100 atomic planes using the same structure as the above example, there was a difference compared to the conventional example. However, similar results were obtained. However, it is preferable that the thin film layers having the same composition have the same thickness throughout the multilayer thin film layer.

なお、上記実施例において、多層薄膜層の構成
層としてInAs(格子定数6.058Å)、GaAs(5.654
Å)及びInSb(6.479Å)を使用した。格子定数の
最も大きいInSbを基準にみるならば、格子定数
の最も小さいGaAsとの格子定数の差は、約13%
である。
In the above example, InAs (lattice constant 6.058 Å) and GaAs (5.654 Å) were used as constituent layers of the multilayer thin film layer.
Å) and InSb (6.479 Å) were used. Based on InSb, which has the largest lattice constant, the difference in lattice constant from GaAs, which has the smallest lattice constant, is approximately 13%.
It is.

一般に、化合物半導体結晶多層薄膜層11の各
層の厚さが厚くなるに従い、各薄膜層がその化合
物半導体結晶本来の格子定数をとる傾向が強ま
り、従つて、多層薄膜層11の各層の厚さを薄く
するほど、各薄膜層がその化合物半導体結晶本来
の格子定数をとる傾向が弱くなると言える。それ
故、格子不整による転位は、格子定数の差を一定
とした場合、膜厚が厚くなるほど生じやすいと言
える。換言するならば、格子不整による転位が生
じない格子不整の上限は膜厚に依存すると言え
る。
Generally, as the thickness of each layer of the compound semiconductor crystal multilayer thin film layer 11 increases, the tendency for each thin film layer to adopt the lattice constant inherent to the compound semiconductor crystal increases. It can be said that the thinner the layer, the weaker the tendency of each thin film layer to take on the lattice constant inherent in the compound semiconductor crystal. Therefore, it can be said that dislocations due to lattice misalignment are more likely to occur as the film thickness increases, assuming that the difference in lattice constant is constant. In other words, it can be said that the upper limit of lattice misalignment at which dislocations do not occur due to lattice misalignment depends on the film thickness.

すなわち、化合物半導体結晶多層薄膜層11の
各層の厚さを1原子面から100原子面の範囲とし
た場合、多層薄膜層11の各層の厚さを薄くする
ほど、格子定数の差を大きくとることができ、多
層薄膜層11の各層の厚さが厚くなるに従い、格
子定数の差を小さくする必要がある。そこで、上
記実施例でのInAs層、GaAs層及びInSb層の厚さ
を考えるならば、上記した格子定数の差約13%
は、格子定数の差の上限とみることができる。
That is, when the thickness of each layer of the compound semiconductor crystal multilayer thin film layer 11 is in the range of 1 atomic plane to 100 atomic planes, the thinner the thickness of each layer of the multilayer thin film layer 11, the larger the difference in lattice constant. As the thickness of each layer of the multilayer thin film layer 11 increases, it is necessary to reduce the difference in lattice constants. Therefore, considering the thicknesses of the InAs layer, GaAs layer, and InSb layer in the above example, the difference in the lattice constants described above is approximately 13%.
can be seen as the upper limit of the difference in lattice constants.

なお、多層薄膜層は、上記した実施例の組合せ
に限られるものではなく、他の組合せも可能であ
り、格子定数の差が0.3%以上、更に好ましくは
1.5%以上であれば、程度に差はあるが同様な効
果が得られる。例えば、格子定数の大きな化合物
半導体としては、InAsの他に、GaSb(6.095Å)
などがあり、また、格子定数の小さな化合物半導
体としては、GaAsの他に、GaP(5.451Å)、InP
(5.869Å)などがある。それらを適当に組合せて
4元系の化合物半導体多層薄膜チヤンネル層を形
成することもできる。
Note that the multilayer thin film layers are not limited to the combinations of the above-mentioned embodiments, and other combinations are also possible, and the difference in lattice constant is 0.3% or more, more preferably
If it is 1.5% or more, similar effects can be obtained although there are differences in degree. For example, in addition to InAs, GaSb (6.095Å) is a compound semiconductor with a large lattice constant.
In addition to GaAs, other compound semiconductors with small lattice constants include GaP (5.451Å), InP
(5.869Å) etc. A quaternary compound semiconductor multilayer thin film channel layer can also be formed by appropriately combining them.

発明の効果 本発明の半導体装置によれば、従来のFETの
チヤンネル層に用いられている化合物半導体の結
晶構造または原子配列を変えることにより、エネ
ルギーバンド構造を変え、高電界印加状態での半
導体結晶内における種々の散乱を低下させ、また
有効質量をし減少させることが可能となる。従つ
て、高電界印加状態における電子の移動度が、従
来の化合物半導体混晶に比べて著しく速い。
Effects of the Invention According to the semiconductor device of the present invention, by changing the crystal structure or atomic arrangement of the compound semiconductor used in the channel layer of a conventional FET, the energy band structure is changed, and the semiconductor crystal under high electric field application is This makes it possible to reduce various types of scattering within the space and also to reduce the effective mass. Therefore, electron mobility under high electric field application is significantly faster than in conventional compound semiconductor mixed crystals.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明による化合物半導体装置を実
施したFETの概略断面図、第2図は、本発明の
化合物半導体装置における電子移動度の印加電界
強度依存性の測定結果を示すグラフ、第3図は、
従来の高電子移動度トランジスタの概略断面図、
第4図は、従来の高電子移動度トランジスタにお
ける電子移動度の印加電界強度依存性の測定結果
を示すグラフ、第5図は、化合物半導体のエネル
ギーバンド構造を説明するための図である。 〔主な参照番号〕、1……半絶縁性GaAs基板、
2……GaAsバツフア層、3……GaAsチヤンネ
ル層、4……電子供給層、5……高濃度にp型不
純物を含有し、大きな電子親和力を有する半導体
よりなる層、6……ゲート電極、7……合金化領
域、8……ソース電極、ドレイン電極、9……二
次元電子ガス、10……InP基板、11……多層
薄膜層、12……ソース電極、ドレイン電極、1
3……ゲート電極、14……混晶化領域。
FIG. 1 is a schematic cross-sectional view of an FET implementing a compound semiconductor device according to the present invention, FIG. 2 is a graph showing measurement results of the dependence of electron mobility on applied electric field strength in the compound semiconductor device according to the present invention, The diagram is
Schematic cross-sectional diagram of a conventional high electron mobility transistor,
FIG. 4 is a graph showing measurement results of the dependence of electron mobility on applied electric field strength in a conventional high electron mobility transistor, and FIG. 5 is a diagram for explaining the energy band structure of a compound semiconductor. [Main reference number], 1...Semi-insulating GaAs substrate,
2...GaAs buffer layer, 3...GaAs channel layer, 4...electron supply layer, 5...layer made of a semiconductor containing a high concentration of p-type impurity and having a large electron affinity, 6...gate electrode, 7... Alloying region, 8... Source electrode, drain electrode, 9... Two-dimensional electron gas, 10... InP substrate, 11... Multilayer thin film layer, 12... Source electrode, drain electrode, 1
3...Gate electrode, 14...Mixed crystal region.

Claims (1)

【特許請求の範囲】[Claims] 1 基板と、該基板上に形成されたチヤンネル層
と、該チヤンネル層の上に形成されたシヨツトキ
ー接合のゲート電極と、該ゲート電極の両側にお
いて該ゲート電極から離れて前記チヤンネル層の
上に形成されたオーミツク接合のソース電極及び
ドレイン電極とを具備しており、前記チヤンネル
層が、格子定数の異なる3種類の化合物半導体薄
膜層を交互に積層して構成され、前記化合物半導
体薄膜層の各層の厚さが1〜100原子面の範囲内
にあり、前記格子定数の相違が、0.3%以上13%
以下の範囲にあることを特徴とする化合物半導体
装置。
1. A substrate, a channel layer formed on the substrate, a Schottky junction gate electrode formed on the channel layer, and a Schottky junction gate electrode formed on both sides of the gate electrode away from the gate electrode. The channel layer is formed by alternately stacking three types of compound semiconductor thin film layers having different lattice constants, and each of the compound semiconductor thin film layers has a The thickness is within the range of 1 to 100 atomic planes, and the difference in the lattice constant is 0.3% or more and 13%.
A compound semiconductor device characterized by being in the following range.
JP5202285A 1985-03-15 1985-03-15 Compound semiconductor device Granted JPS61210676A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP5202285A JPS61210676A (en) 1985-03-15 1985-03-15 Compound semiconductor device
CA000504069A CA1256590A (en) 1985-03-15 1986-03-13 Compound semiconductor device with layers having different lattice constants
EP86103425A EP0196517B1 (en) 1985-03-15 1986-03-14 Compound semiconductor device
AU54742/86A AU577934B2 (en) 1985-03-15 1986-03-14 Compound semiconductor device
DE8686103425T DE3672360D1 (en) 1985-03-15 1986-03-14 CONNECTING SEMICONDUCTOR COMPONENT.
KR1019860001897A KR860007745A (en) 1985-03-15 1986-03-15 Compound Semiconductor Device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5202285A JPS61210676A (en) 1985-03-15 1985-03-15 Compound semiconductor device

Publications (2)

Publication Number Publication Date
JPS61210676A JPS61210676A (en) 1986-09-18
JPH0328063B2 true JPH0328063B2 (en) 1991-04-17

Family

ID=12903185

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5202285A Granted JPS61210676A (en) 1985-03-15 1985-03-15 Compound semiconductor device

Country Status (1)

Country Link
JP (1) JPS61210676A (en)

Also Published As

Publication number Publication date
JPS61210676A (en) 1986-09-18

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