JPS6028273A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain an FET which can be operated stably by a method wherein a laminated structure, consisting of alternately laminated first layer of ultralow density of impurities, the second layer of small electron affinity and of ultralow density with which an electron can be tunnelled through, and the third layer containing N type impurities having the affinity larger than that of the second layer and the thickness below the electron wavelength is formed on a semiconductor substrate. CONSTITUTION:The second layer 8 of high purity AlAs of 50Angstrom or less and the third layer 9 of Si-added GaAs of 100Angstrom or less are alternately superposed on the first layer 2 of high purity GaAs located on a semiinsulating GaAs 1, a Schottky gate electrode 9 is attached to the surface, and a source and drain electrode is attached to both sides. According to this constitution, the electron generating from N-GaAs 9 is distributed all over the laminated body of the layers 8 and 9 by the quantization level Eq generating from layers 8 and 9, and a deep trap level relating to impurities is not formed. As the level Eq is higher than the conductive band end Ec of the layer 2, the electron on the Eq is partially dropped on the layer 2 side, and electron gas 4 is formed on the 8-2 interface. However, as there is no deep trap level, secondary two-dimensional electron is fluctuated by the irradiation of light and hot electron, and also there is no difference in the two-dimensional electron density at the room temperature and a low temperature, thereby enabling to perform a stable FET operation.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device having high electron mobility and capable of stable operation.

As an active semiconductor device that can be expected to operate at high speed, FET (Field
Effect Transistor). This is a hetero-interface of semiconductors with different electron affinities (for example, 1'
In dtz G 2LzA5 3A8), a semiconductor with a small electron affinity is doped with an impurity, two-dimensional electrons are generated on the side of the semiconductor with a large electron affinity, and these two
It is characterized by the use of high mobility of dimensional electrons. However, in the AlxGa1-xAS/GaA3 system, there is a phenomenon that is inconvenient in terms of operation.

AIX Ga1-x generally doped with n-type impurities
There is a deep TR9 level in As that is related to impurities. Since electrons are captured in this trap level, the carrier concentration is lower than the doped impurity concentration, and the concentration decreases significantly at a low temperature of about 77°C.

This decreasing tendency at low temperatures is very sensitive to the composition ratio X of A/, and at 02<X<05, the carrier concentration decreases rapidly as X increases. Moreover, the carrier concentration increases when exposed to light at low temperatures, and this state is maintained even when the light is cut off.
ductivity (PPC). Therefore, in an FET using two-dimensional electrons of the lxG, xAs/GaA; system, the two-dimensional electron concentration decreases at low temperatures, so the threshold voltage differs significantly between room temperature and low temperature.

Furthermore, since it is sensitive to the A1 composition ratio X, there are large variations in characteristics due to FET manufacturing. Furthermore, hot electrons accelerated by the photoirradiation effect (PPC) at low temperature and the drain electric field enter A/xGa-1,A from the A/xGai-xAs/GaAs interface and are captured in the trap. In particular, the drain current changes.

In this way, FETs using the 1xGa, '4=xAs/GaAs system are required to suppress threshold fluctuations due to temperature, to manufacture products with uniform characteristics with good reproducibility, and to be stable under light irradiation and high electric fields. It was extremely difficult to operate.

FIG. 1 is a schematic cross-sectional view of an example of a conventional FET using two-dimensional electrons.

In Figure 1, 1 is a semi-insulating semiconductor substrate, 2 is a semiconductor layer of copper 1 with as few impurities as possible, and 3 is an electron supply made of a semiconductor containing n-type impurities and having a lower electron affinity than the first semiconductor #1. 4 is a two-dimensional electron gas formed at the interface between the first semiconductor layer 2 and the electron supply layer 3; 5 is a gate electrode forming a Schottky junction with the electron supply layer 3; 6 is an alloy with the electron supply layer 3; A source electrode 7 is in electrical contact with the two-dimensional electron gas 4, and 7 is a drain electrode similar to 6.

FIG. 2 is a diagram showing the band structure under the gate electrode of the F'ET shown in FIG. 1.

Components in FIG. 2 with the same numbers as in FIG. 1 have the same functions. Bt is a deep electron trap level in the electron supply layer 3, Eo is the conduction band edge, Ef is the Fermi level,
'Bv is the charged zone edge.

Next, we will introduce the conventional FET using two-dimensional electrons shown in Figure 1.
The operation will be explained. Here, in the FBT, the first semiconductor layer 2 is made of GaAs, and the electron supply layer 3 is made of n-type Aj5o3Ga.
P,? It is assumed that the transistor is made of All Al, the source is at zero potential, and the drain is applied with a positive voltage.

When the gate voltage is 0■, n kilo , s Ga6
,7 Assuming that As is completely depleted and has the band structure shown in Figure 2, A & -3 Gao under the gate,
7 As/GaAs interface (GaAs side) has nA7
A two-dimensional electron gas induced by the ionized donors in 70,3 Gao, y A S is formed,
A drain current flows between the source and drain through two-dimensional electron gas.

Here, as the gate voltage increases in a negative direction, the two-dimensional electron gas under the gate decreases and the drain current decreases, and conversely, as the gate voltage increases in a positive direction, the two-dimensional electron gas under the gate decreases. The gas increases and the drain current increases.

Now, in n-type Aa, s Gau, 7 As, there are many deep electron trap levels Bt related to impurities,
As the temperature decreases, the rate at which electrons are captured in this electron trap increases, and the concentration of two-dimensional electrons decreases. When light is irradiated at a low temperature of about 77° C., the electrons trapped in the electron trap level Et are ejected into the conduction band by the light energy, and the number of two-dimensional electrons increases. Also, some of the two-dimensional electrons are accelerated by the drain electric field between the source and drain and become hot, resulting in A7Ll, 3 Gap, ?
When they jump into As, they are captured by an electron trap level and the number of two-dimensional electrons decreases.

Since these phenomena change the number of two-dimensional electrons, the drain current changes and stable FET operation is inhibited.

The object of the present invention is to eliminate the above-mentioned drawbacks, to provide an FET that uses two-dimensional electrons, has no difference in two-dimensional electron density at room temperature and low temperature, and is capable of stable operation under light irradiation and high electric field. The object of the present invention is to provide a semiconductor device that is of high quality.

According to the present invention, a first semiconductor layer with an extremely low impurity concentration is provided on a semiconductor substrate, and an electron tunneling layer is provided on the first semiconductor layer and has a smaller t-son affinity than the first semiconductor layer. a second semiconductor layer with an extremely low impurity concentration and a third semiconductor layer having a thickness equal to or less than the electron wavelength and containing an n-type impurity, which has a larger stain affinity than the second semiconductor layer; an interface between a J-th semiconductor layer and a second semiconductor layer provided on the laminated surface with the gate electrode sandwiched therebetween; A semiconductor device is obtained, which includes a pair of electrodes forming electrical contact with carriers present in the semiconductor device.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a schematic cross-sectional view of the first embodiment of the present invention. In FIG. 3, the same numbers as in FIG. 1 are equivalent to those in FIG. 1 and perform the same functions. 8 The first semiconductor layer 2 has a stain affinity of 1. The second semiconductor layer has a thickness that allows electrons to tunnel and has an extremely low impurity concentration. This is a third semiconductor layer containing an n-type impurity that has a large affinity and a thickness that is equal to or less than the electron wavelength. The extremely low impurity concentration mentioned above means that the impurity is not doped intentionally or is doped only slightly. The thicknesses of the second and third layers are sufficiently thin so that quantum effects are noticeable, and this varies depending on the material. For example, the first semiconductor layer 2 is made of high-purity GaAs, the second semiconductor layer 8 is made of high-purity A/As of about 50 A or less, and the third semiconductor layer 9 is made of Si-doped G of about 100 A or less.
It is a As.

Hereinafter, the operation of the first embodiment will be explained in detail using the above-mentioned materials for each semiconductor layer and using FIG. 4, which is a diagram of the band structure.

Figure 4 shows the gate of the FET shown in Figure 3! FIG. 3 is a diagram showing the bottom band structure. In FIG. 4, parts with the same numbers as in FIGS. 1 to 3 are equivalent to those in FIGS. 1 to 3 and perform the same functions. Eq is the lowest quantization level of electrons newly formed by the stacked structure of the second semiconductor layer 8 and the third semiconductor layer 9.

Electrons generated from n-GaAs are distributed not only in n-GaAs but also in high-purity AIAs and distributed throughout the p n-GaAs/AAAs stacked structure, depending on the quantization level Eq. At this time, n-GaAs in s and high purity AIA
During s, n-A10. , Gao, y The deep electron trap levels associated with impurities such as in As are not formed. This is because there are no such trap levels in n-GaAs and there are no impurities in AlAs.

The quantization level Eq is the conduction band edge Be of high purity Ga As.
Since it is at a higher energy position, some of the electrons at the quantization level Eq fall to the high-purity GaAs side, and a two-dimensional electron gas is formed at the high-purity GaAs IA/As interface. . Therefore, the operation as an FET is the same as that of the conventional structure shown above. However, in this first embodiment, the electron supply layer 3 of the conventional structure is made of n-GaAs/AA! Since there is no deep electron trap level in the As stacked structure, even if hot electrons jump into the stacked structure due to light irradiation, two-dimensional electron fluctuations are small and the FBT operation is stable. Furthermore, since there is no difference in the two-dimensional electron band width between room temperature and low temperature, it is easy to design an FET that operates at low temperatures, and the reproducibility of FET manufacturing is also good.

In this example, MBB (Mole
High purity GaA with a thickness of 1 μm was deposited on a semi-insulating GaAs substrate using
Growth of s-layer followed by 15A thick high-purity IAs
A laminated structure of n-type GaAs containing Si impurity of 1.7×10”cIn was grown to a total thickness of 500A with a thickness of 23A. A as an electrode
u-G e IA u was used. As a result, a mutual conductance gm of 450 mS/vm at 77K was obtained for a FET with a gate length of 0.3 μm1 and a gate-source distance and a gate-drain distance of 0.3 μm, and the mutual conductance gm was 450 mS/vm under light irradiation and high electric field. There was no change in the characteristics.

FIG. 5 is a schematic cross-sectional view of an embodiment of the winnow 2 of the present invention. In FIG. 5, the same numbers as in FIGS. 1 to 4 are equivalent to those in FIGS. 1 to 4 and perform the same functions. ] 0 means that the electron affinity is smaller than that of the first semiconductor layer 2, and the conduction band is equal to or equal to the quantization level Bq formed by the stacked structure of the second semiconductor layer 8 and the third semiconductor Na9. This is a spacer layer with a very low impurity concentration. For example, the space V layer is A4. , Gao,, As.

Hereinafter, the operation of the second embodiment will be explained using high purity GaAs as the first semiconductor layer 2, high purity A/As as the second semiconductor layer 8, and n-type GaAs as the third semiconductor layer 9.
, high purity A4,3Ga as the spacer layer 10. ,,A
This will be explained in detail using FIG. 6, which is a diagram of this band structure.

FIG. 6 is a diagram showing the band structure under the gate electrode of the FBT shown in FIG. 5. In FIG. 6, the same numbers as in FIGS. 1 to 5 are equivalent to those in FIGS. 1 to 5 and indicate the same functions.

Electrons generated from n GaAs9 also spread into high-purity A/AsS due to the quantization level Eq, and some of them fall into high-purity GaAs2 through the spacer layer A/, s Gau, , As 10. , high purity GaA s/A4. s
A two-dimensional electron gas is formed at the Gaa, yAs interface.

Since almost no impurities exist in the high-purity A-based, Gao, or As layer that is the spacer layer, there are no electron traps related to impurities. Therefore, as in the first embodiment, stable FET operation can be obtained even under light irradiation and under a high electric field. Furthermore, since the distance between the two-dimensional electron layer and the n-type GaAs containing impurities is separated by the spacer layer 10, ionized impurity scattering of two-dimensional electrons is reduced, and A/, s Ga...7 As/
Since the GaAs interface can be easily formed to have better interface flatness than the A II As /Ga As interface, the two-dimensional electron mobility is greater than that in the first embodiment.

According to this example, MBE is used as the crystal growth method,
High purity Ga with a thickness of 1 μm on a semi-insulating GaAs substrate
Grow A s and then grow high purity A44 with a thickness of 100A.
Grow Ga,,7As followed by 2.4X10CWL with 20A of high purity A12As and a thickness of 23A.
A stacked structure with n-type GaAs containing Si impurities was grown to a total thickness of 400A. K1 is used as the Schottky gate electrode, and A is used as the source and drain electrodes.
u-Ge/Au was used. As a result, 77K
The mobility is as high as 100.0007.4'S, and in a FET with a gate length of 0.3 μm and a gate-source distance and a gate-drain distance of 0.3 μm,
The mutual conductance gm at 7 is 500 m5//)I
i was obtained, and there was no change in characteristics under light irradiation or under high electric field.

In the above two embodiments of the present invention, only SiL is shown as the impurity in the GaAs layer, but SiL, Se, 8n, and 8 may be used as the n-type impurity.

In addition, the n-type impurity was added to GaAs corresponding to the third semiconductor layer.
If doping is performed not on the entire layer but on the interface with the A/As layer of the second semiconductor layer, this interface (A/x
It is possible to completely eliminate electron traps related to impurities generated in Ga 1-xAs. Additionally, if the third semiconductor layer located within about 100X from the two-dimensional electrons in the structure of the first embodiment is made into a structure in which no impurities are doped, the two-dimensional electron mobility will be reduced as in the second embodiment. can be increased.

In the two embodiments of the present invention, the first semiconductor layer and the third semiconductor layer use the same GaAs, but the third semiconductor layer is made of GaAs(xGa z−xAs(x <0.
2) may also be used. In addition, the second semiconductor, high purity A
AjlxGal xA with many A4 compositions as a replacement for llAs
s (x>0.3).

In the two embodiments of the present invention, the gate Schottky electrode is formed on the surface of the third semiconductor layer 9 constituting the stacked structure, but the effect is exactly the same even if it is formed on the surface of the second semiconductor layer 9. . A semiconductor layer having a thickness of 20 to 300 Å may be further formed on the stacked structure, and a gate Schottky electrode may be formed on the surface of the semiconductor layer. In this case, the semiconductor layer is a high resistance or n-type GaAs or A
iVxGa]xAs is used.

Although only the Schottky junction gate electrode is shown, the gate electrodes include a p-n junction gate electrode, a $asi-8chottky gate electrode, and a camel gate electrode.
1 game) [A polar insulated gate electrode may be used.

Although only a semi-insulating GaAs substrate is shown as a substrate, a substrate whose top layer is semi-insulating A/xGa1 xAs and a superlattice whose top layer is A 11 A s /G a As s are also available. The substrate may be a superlattice of xGa 1-xAs/GaAs.

Although only A/As and GaAs systems are shown in the embodiments of the present invention, it is clear that other semiconductor systems may also be used. For example, high purity In. , 5°Ga
O, 4? As the first semiconductor layer, high purity (n
x A /l 1-xA s (x”0.53) is the second semiconductor layer, n-type InxGa 1-xA4 (x=
The present invention is effective even when the third semiconductor layer is 0.53). In this case, X=053 and the substrate is 1np
However, even if the lattice deviates from this, there is no problem because misalignment and distortion are absorbed at each interface of the laminated structure.Furthermore, by decreasing the X of InxA/+-xAs, the barrier to two-dimensional electrons can be increased. This is effective because it can increase the height.

In principle, any crystal growth method may be used to form the structure of the present invention, but since it requires the ability of several people to control the film thickness, the MBE method and MOCVD (Metal
Organic Chemical Vapor D
eposition) method is suitable. Among them, M.B.B.
In this method, the molecular beam emitted from the molecular beam source containing the raw material can be controlled simply by opening and closing a shutter, so it is easy to create a steep interface with a transition layer of several amps, and it is also easy to automatically control using a computer. This is the most suitable method.

[Brief explanation of the drawing]

Fig. 1 is a schematic cross-sectional view of an FET using two-dimensional electrons with a conventional structure, Fig. 2 is a band structure diagram under the gate electrode of a conventional structure, and Fig. 3 is a schematic diagram showing the first embodiment of the present invention. 4 is a schematic sectional view showing the band structure under the gate electrode of the first embodiment, FIG. 5 is a schematic sectional view showing the second embodiment of the present invention, and FIG. 6 is a diagram of the second embodiment. Example game)! This is a diagram of the bottom band structure. l... Semiconductor substrate 2... First semiconductor layer 3... Electron supply layer 4... Two-dimensional electron gas 5... Gate electrode 6... Source electrode 7... Drain electrode 8. 2
Semiconductor #layer 9...Third semiconductor layer 1o...Spacer layer Ei...Electron trap level Ec...Conduction band edge Bf
... 7-stage Lumi level Ev..., filling zone edge Bq--
Quantization level mourning 1 national mourning Z mouth 3 paintings

Claims (2)

[Claims] (1) First layer with extremely low impurity concentration provided on the semiconductor substrate
a second semiconductor layer provided on the first semiconductor layer and having an extremely low impurity concentration and having a thickness that allows tunneling of electrons and having a smaller stain electron affinity than the first semiconductor layer; A laminated structure in which a third semiconductor layer having an electron affinity greater than that of the second semiconductor layer and having a thickness equal to or less than the electron wavelength and containing an n-type impurity is laminated alternately, and a third semiconductor layer provided on a part of the upper surface of the laminated structure. a pair of electrodes that form electrical contact with a gate electrode that is provided on the upper surface of the laminated structure with the gate electrode in between and exists at the interface between the 11 semiconductor layers and the second semiconductor layer; A semiconductor device comprising: (2) The semiconductor device according to claim (1), further comprising a spacer layer containing no impurities between the first semiconductor layer and the laminated structure.