JPS61210677A - Compound semiconductor device - Google Patents

Compound semiconductor device

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Publication number
JPS61210677A
JPS61210677A JP5202385A JP5202385A JPS61210677A JP S61210677 A JPS61210677 A JP S61210677A JP 5202385 A JP5202385 A JP 5202385A JP 5202385 A JP5202385 A JP 5202385A JP S61210677 A JPS61210677 A JP S61210677A
Authority
JP
Japan
Prior art keywords
compound semiconductor
thin film
layer
crystal
film layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5202385A
Other languages
Japanese (ja)
Other versions
JPH0354853B2 (en
Inventor
Yuichi Matsui
松居 祐一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP5202385A priority Critical patent/JPS61210677A/en
Priority to CA000504069A priority patent/CA1256590A/en
Priority to AU54742/86A priority patent/AU577934B2/en
Priority to EP86103425A priority patent/EP0196517B1/en
Priority to DE8686103425T priority patent/DE3672360D1/en
Priority to KR1019860001897A priority patent/KR860007745A/en
Publication of JPS61210677A publication Critical patent/JPS61210677A/en
Publication of JPH0354853B2 publication Critical patent/JPH0354853B2/ja
Granted legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/80Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025Channel region of field-effect devices
    • H01L29/1029Channel region of field-effect devices of field-effect transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025Channel region of field-effect devices
    • H01L29/1029Channel region of field-effect devices of field-effect transistors
    • H01L29/1033Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/15Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
    • H01L29/151Compositional structures
    • H01L29/152Compositional structures with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
    • H01L29/155Comprising only semiconductor materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)

Abstract

PURPOSE:To obtain high electron mobility even when a high electric field is applied, by alternately laminating two kinds of compound semiconductor thin film layers having large lattice irregularities, thereby suppressing electron scattering. CONSTITUTION:On a semi-insulating InP substrate 10, InAs and AlAs are laminated by about 80 layers, respectively. Each layer comprises several atomic layers. Such a crystal structure is provided in AlxIn1-xAs compound- semiconductor-crystal multiple thin film layer 11. The layer 11 is formed as a channel layer in an FET. The total thickness of the multiple thin film layer 11 is 0.1mum. Said multiple thin film layer 11 is formed by using an MBE growing method on the semi-insulating InP substrate 10. On the surface of the multiple thin film layer 11, an AuGeNi ohmic junction electrode 12 is evaporated, and source and drain electrodes are formed. An Al Schottky junction electrode 13 is evaporated, and a gate electrode is formed.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、化合物半導体装置に関する。更に詳しくは本
発明は、格子定数の異なる2種類の化合物半導体薄膜層
を交互に積層させて、既存のいわゆる混晶化合物半導体
と異なるエネルギーバンド構造を実現することにより、
高電界印加状態における電子移動度を大きくした化合物
半導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to compound semiconductor devices. More specifically, the present invention realizes an energy band structure different from that of existing so-called mixed crystal compound semiconductors by alternately stacking two types of compound semiconductor thin film layers with different lattice constants.
The present invention relates to a compound semiconductor device with increased electron mobility in a state where a high electric field is applied.

従来の技術 化合物半導体デバイス、特に電子デバイスの製法として
、薄い一様な層の成長、成分元素組成比の制御の容易さ
からエピタキシャル成長方法が一般的に利用されている
。なかでも、最近特に注目されている技術として、分子
線エピタキシャル成長方法(以下簡単のためにrMBE
成長法」という)が知られている。例えばW、 T、 
Tsangにより日経エレクトロニクスNo、308.
163 (1983)において、MBEF&長法並びに
薄膜周期構造を利用したデバイスが詳細に説明されてい
る。
BACKGROUND OF THE INVENTION Epitaxial growth methods are generally used as a manufacturing method for compound semiconductor devices, particularly electronic devices, because of the ease of growing thin, uniform layers and controlling the composition ratio of component elements. Among them, a technique that has recently attracted particular attention is the molecular beam epitaxial growth method (hereinafter referred to as rMBE for simplicity).
``growth method'') is known. For example, W, T,
Nikkei Electronics No. 308 by Tsang.
163 (1983), devices utilizing the MBEF & length method and thin film periodic structures are described in detail.

このMBE成長法に従えば、結晶成長速度を単原子面レ
ベルで制御することができ(J、 P、 van de
rZiel他、J、Appl、Phys、48 (19
77)  P4O10) 、さらには、反射型電子線回
折法を併用すれば1原子面の組成をも正確に制御するこ
とができる(J、H,Neave他、Appl、Phy
s、  A3L1 (1983) ) 、 コのような
MBE法を用いることにより、第3図に示すような高電
子移動度トランジスタ(以下、HEMTと略す)を製造
することが可能となる。
By following this MBE growth method, the crystal growth rate can be controlled at the monatomic level (J, P, van de
rZiel et al., J. Appl. Phys., 48 (19
77) P4O10) Furthermore, if reflection electron diffraction is used in combination, it is possible to precisely control the composition of a single atomic plane (J. H. Neave et al., Appl. Phys.
By using the MBE method such as that described in S., A3L1 (1983), and Ko, it becomes possible to manufacture a high electron mobility transistor (hereinafter abbreviated as HEMT) as shown in FIG.

なお、従来の化合物半導体を用いたマイクロ波素子につ
いては、たとえば特開昭59−4085号および特開昭
58−147169号公報に記されている。
Note that microwave elements using conventional compound semiconductors are described in, for example, Japanese Patent Laid-Open No. 59-4085 and Japanese Patent Laid-Open No. 58-147169.

第3図に示したHEMT構造は、半絶縁性Ga八sの基
板1を有し、その基板1の上には、バッファ層として機
能するGaAs層2が形成され、更にその上に、チャン
ネル層をなすアンドープのGaAs層3が形成されてい
る。そして、そのGaAs層3上には、n  GagA
I+−MへSのような高い不純物濃度の電子供給層4が
形成され、その中央には、高濃度にp型不純物を含有し
、大きな電子親和力を有する半導体よりなる層5が設け
られ、そして、その層5の上にはゲート電極6が形成さ
れている。更に、層5を挟む電子供給層4の表面領域7
は合金化され、その上にソース及びドレインの電極8が
形成されている。
The HEMT structure shown in FIG. 3 has a semi-insulating GaAs substrate 1, on which is formed a GaAs layer 2 which functions as a buffer layer, and further on which is a channel layer. An undoped GaAs layer 3 is formed. Then, on the GaAs layer 3, n GagA
An electron supply layer 4 having a high impurity concentration such as S to I+-M is formed, and a layer 5 made of a semiconductor containing a high concentration of p-type impurity and having a large electron affinity is provided in the center thereof, and , a gate electrode 6 is formed on the layer 5 . Furthermore, the surface region 7 of the electron supply layer 4 sandwiching the layer 5
are alloyed, and source and drain electrodes 8 are formed thereon.

このような半導体装置において、ゲート電極6に適当な
バイアス電圧を印加すると、電子供給層4とチャンネル
層3との界面におけるチャンネル層3側に、二次元電子
ガス9が形成される。この結果、不純物イオンの少ない
チャンネル層3内の界面近傍数10人厚のところを、多
量の電子が流れることになる。従って、電子移動度を制
限する1つの大きな要因である不純物イオン散乱が少な
く、高移動度を実現することができる。
In such a semiconductor device, when an appropriate bias voltage is applied to the gate electrode 6, a two-dimensional electron gas 9 is formed on the channel layer 3 side at the interface between the electron supply layer 4 and the channel layer 3. As a result, a large amount of electrons flows through the channel layer 3, which has a few impurity ions, at a thickness of several tens of layers near the interface. Therefore, impurity ion scattering, which is one of the major factors that limit electron mobility, is reduced, and high mobility can be achieved.

発明が解決しようとする問題点 しかしながら、このような化合物半導体装置においては
、二次元電子ガスにおける電子移動度の印加電界強度依
存性が極めて大きく、低電界の場合には高移動度を実現
できるが、高電界の場合にはその移動度が著しく低下し
てしまう。このような現象は、例えば、M、 Inou
e他J、J、A、P、 22357(1983)に記述
されている。また、その1例を上記したマイクロ波素子
のようなGaAs層 n−GaXA1+−XAs構造の
場合について示すと、第4図の点線の如くなる。
Problems to be Solved by the Invention However, in such a compound semiconductor device, the dependence of electron mobility in a two-dimensional electron gas on the applied electric field strength is extremely large, and although high mobility can be achieved in the case of a low electric field, , in the case of a high electric field, its mobility decreases significantly. Such a phenomenon is, for example, M, Inou
J, J, A, P, 22357 (1983). An example of this is shown in the case of a GaAs layer n-GaXA1+-XAs structure such as the above-mentioned microwave device, as shown by the dotted line in FIG.

このような高電界印加状態における半導体内での電子散
乱機構としては、インターバレイ(谷間)散乱やインパ
クトイオナイゼーションあるいはフォノン(格子振動)
散乱などが挙げられる。そのため、一般に超高周波トラ
ンジスタにおいてチャンネル層として用いられる半導体
結晶は、以下の特性の向上が要求される。
Electron scattering mechanisms within semiconductors under such high electric field conditions include intervalley scattering, impact ionization, and phonon (lattice vibration).
Examples include scattering. Therefore, semiconductor crystals generally used as channel layers in ultra-high frequency transistors are required to have the following improved characteristics.

■ インターバレイ散乱を起こりにくくするために、k
空間での谷間のあいだのエネルギー差△Eが大きいこと
■ To make intervalley scattering less likely to occur, k
The energy difference △E between the valleys in space is large.

■ インパクトイオナイゼーションを起こりにくくする
ために、エネルギーギャップE9が大きいこと。
■ The energy gap E9 must be large to make impact ionization less likely to occur.

■ キャリア電子の運動エネルギーのフォノン散乱によ
る損失を小さくするために、有効質量m1が小さいこと
■ The effective mass m1 must be small in order to reduce the loss of kinetic energy of carrier electrons due to phonon scattering.

谷間間のエネルギー差△E1エネルギーギャップE、な
どのパラメータについては1.GaAs結晶のエネルギ
ーバンド構造を例に挙げるならば、第5図の如くである
。また、有効質量m*はエネルギーバンド構造との間に
、 m*   +I、2     dk2 のような関係がある。
Parameters such as energy difference between valleys △E1 energy gap E, etc. are described in 1. An example of the energy band structure of a GaAs crystal is shown in FIG. Further, the effective mass m* has a relationship with the energy band structure as m* +I, 2 dk2.

しかしながら、従来の化合物半導体装置においては、実
質的な厚さを持つ各層の化合物半導体は、均一な組成構
造を追求されているために、上記した八E、E1、m*
は自ずと決まっていた。そのために、上記した散乱の解
消には壁があり、高電界印加状態において高い電子移動
度が実現できなかった。
However, in conventional compound semiconductor devices, the compound semiconductor of each layer having a substantial thickness is required to have a uniform composition structure.
was decided by itself. Therefore, there is a barrier to eliminating the above-mentioned scattering, and high electron mobility cannot be achieved in a state where a high electric field is applied.

そこで、本発明は、上記した電子散乱の影響を抑えて、
高電界印加状態においても高い電子移動度を有する化合
物半導体装置を提供せんとするものである。
Therefore, the present invention suppresses the influence of electron scattering described above, and
The present invention aims to provide a compound semiconductor device that has high electron mobility even when a high electric field is applied.

問題点を解決するための手段 そこで、本発明者は、上記目的のために電子散乱の問題
を種々研究した。
Means for Solving the Problems Therefore, the present inventor conducted various studies on the problem of electron scattering for the above purpose.

上記説明かられかるように、超高周波トランジスタにお
いて、チャンネル層として用いられる化合物半導体結晶
は、そのエネルギーバンド構造を変えることにより、高
電界印加状態でのインターバレイ散乱やインパクトイオ
ナイゼーションによる散乱を低下させ、あるいは電子の
有効質量を小さくすることによって、高電界印加状態に
おける移動度を大きくすることができる。
As can be seen from the above explanation, the compound semiconductor crystal used as the channel layer in ultra-high frequency transistors reduces intervalley scattering and impact ionization scattering when a high electric field is applied by changing its energy band structure. Alternatively, by reducing the effective mass of electrons, the mobility under high electric field application can be increased.

一方、半導体のエネルギーバンド構造に関するLCAO
理論によると、エネルギーバンド構造を計算する際に重
要となるハミルトニアンの非対角行列要素V L L・
0は、 で表わされる。ただし、11 ビはそれぞれ結晶を構成
する隣接原子の最外殻p軌道の方位量子数、mは同じく
磁気量子数であり、dは隣接原子の核間距離、moは電
子質量、η5.・0は結晶構造に依存した係数、R=h
/2π(hニブランク定数)である。
On the other hand, LCAO regarding the energy band structure of semiconductors
According to theory, the off-diagonal matrix elements of the Hamiltonian, V L L , are important when calculating the energy band structure.
0 is represented by . However, 11 Bi is the azimuthal quantum number of the outermost p-orbital of the adjacent atoms constituting the crystal, m is the magnetic quantum number, d is the internuclear distance of adjacent atoms, mo is the electron mass, η5.・0 is a coefficient depending on the crystal structure, R=h
/2π(hniblank constant).

また、ハミルトニアンの対角行列要素εsc1εa1 
εPc% ε、aなどは、相対的には孤立原子の積値に
関連したものである。ただし、εScは極性化合物半導
体の陽イオン原子S軌道の積値に関連しており、同様に
、εaは陰イオン原子S軌道の積値に、ε、′は陽イオ
ン原子P軌道の積値に、ε、″は陰イオン原子P軌道の
積値にそれぞれ関連している。
Also, the diagonal matrix element εsc1εa1 of the Hamiltonian
εPc% ε, a, etc. are relatively related to the product value of an isolated atom. However, εSc is related to the product value of the cation atomic S orbitals of the polar compound semiconductor, and similarly, εa is related to the product value of the anion atomic S orbitals, and ε,′ is related to the product value of the cation atomic P orbitals. , ε, ″ are respectively related to the product value of the anion atomic P orbital.

この既成理論(たとえば、凱へ、 Harrison。This established theory (for example, Gai, Harrison.

Blectronic 5tructure and 
the  Properties ofSolids、
 1980参照)によれば、結晶構造または原子配列を
変えることにより、すなわち化合物半導体結晶中におけ
る隣接原子の核間距離dならびに隣接原子の種類を変え
ることにより、ハミルトニアンの行列要素V11’mz
εS”% ε、、C1εpa1 ε、Cを変えることが
できる。このことは、結晶構造または原子配列を変える
ことにより化合物半導体のエネルギーバンド構造を変え
ることができることを意味する。
Blectronic 5structure and
the Properties of Solids;
(1980), by changing the crystal structure or atomic arrangement, that is, by changing the internuclear distance d of adjacent atoms in a compound semiconductor crystal and the type of adjacent atoms, the matrix element V11'mz of the Hamiltonian can be changed.
εS''% ε, , C1εpa1 ε, C can be changed. This means that the energy band structure of the compound semiconductor can be changed by changing the crystal structure or atomic arrangement.

一方、最近の化合物半導体結晶成長技術にふいては、上
記したように、分子線エビクキシャル成長法(MBE法
)や有機金属気相成長法(’MO’CVD、MOVPE
などと略す)などのように、成長層厚の制御が単原子層
程度にまで向上しており、現にGaAsとへIへsを用
いて単原子レベルで交互に積層することに成功している
(A、C,Gossard、 T’h’1nSolid
 Films 57. 3 (1979) )。
On the other hand, as mentioned above, recent compound semiconductor crystal growth techniques include molecular beam eviaxial growth (MBE), metal organic vapor phase epitaxy ('MO'CVD, and MOVPE).
The control of the growth layer thickness has been improved to the level of a single atomic layer, and it has actually been possible to alternately stack layers of GaAs and ions at the monatomic level. (A, C, Gossard, T'h'1nSolid
Films 57. 3 (1979)).

しかしながら、GaAsとAlAsとを交互に積層した
場合は、格子不整が約0.3%と極めて小さく、ゆえに
これら2種類の層i交互に積層することによって生じる
結晶格子の歪みは小さい。このことは、従来のGa、A
l I−XAS混晶に比べて、原子配列のみが若干変化
し、結晶構造はほとんど変化していないことを意味し、
ゆえにエネルギーバンド構造も大きな変化を示さない。
However, when GaAs and AlAs are alternately laminated, the lattice mismatch is extremely small, about 0.3%, and therefore the strain in the crystal lattice caused by alternately laminating these two types of layers i is small. This means that conventional Ga, A
l This means that compared to the I-XAS mixed crystal, only the atomic arrangement has changed slightly, and the crystal structure has hardly changed,
Therefore, the energy band structure does not show any major changes.

ところが、2種類の層の格子不整を約1.5%と大きく
した場合には、エネルギーギャップE9の大きな変化が
観測されている(G、 C9[]5bourn他、J、
Appl、 Phys、郵(1977) 3018) 
。すなわち、このように格子不整が比較的大きい場合に
は、原子配列だけではな、く結晶構造の変化も生じ、エ
ネルギーバンド構造の比較的大きな変化が観測されてい
る。
However, when the lattice mismatch between the two types of layers is increased to about 1.5%, a large change in the energy gap E9 has been observed (G, C9[]5bourn et al., J.
Appl, Phys, Yu (1977) 3018)
. That is, when the lattice misalignment is relatively large like this, not only the atomic arrangement but also the crystal structure changes, and a relatively large change in the energy band structure is observed.

しかしながら、この報告の場合においては、各層厚が1
00〜200人と厚くなっており、2種類の層の界面近
傍における結晶格子の歪んだ部分に比べて、結晶格子の
歪んでいない従来通りの結晶構造をとっている部分の方
が極めて多くなっている。
However, in the case of this report, each layer thickness is 1
00 to 200 people, and compared to the distorted part of the crystal lattice near the interface between the two types of layers, the part where the crystal lattice is not distorted and has the conventional crystal structure is extremely large. ing.

このため、エネルギーバンド構造についてもそのほとん
どが、各層の従来通りの結晶構造に起因したエネルギー
バンド構造によって支配されており、結晶格子の歪んだ
部分からの寄与は小さい。このように結晶格子の歪みが
、各層の界面近傍に限られティるという事実は、JoM
、 Brown他、A、 P、 L、 43(1983
)  863に記されている。さらに、このような格子
不整に基く歪みによって結晶構造が変化するという直接
的な結果は、J、八、P、45. No、9 、 (1
974)3789に記されている。
Therefore, most of the energy band structure is dominated by the energy band structure resulting from the conventional crystal structure of each layer, and the contribution from distorted portions of the crystal lattice is small. The fact that the distortion of the crystal lattice is limited to the vicinity of the interface of each layer in this way suggests that the JoM
, Brown et al., A. P. L. 43 (1983
) 863. Furthermore, the direct result that the crystal structure changes due to distortion based on such lattice misalignment is J, 8, P, 45. No, 9, (1
974) 3789.

以上のことから、格子不整の大きな2種類の化合物半導
体薄膜層を交互に積層させることにより、成長層全体に
わたって結晶構造または原子配列を変えることができる
From the above, by alternately stacking two types of compound semiconductor thin film layers with large lattice mismatches, the crystal structure or atomic arrangement can be changed over the entire growth layer.

なお、化合物半導体薄膜層を交互に積層させた半導体装
置という点で類似の報告は、たとえば、特開昭59−7
6468号公報あるいはT、 Yao、 J、J、A、
 P。
A similar report in terms of a semiconductor device in which compound semiconductor thin film layers are alternately laminated is, for example, published in Japanese Patent Laid-Open No. 59-7.
No. 6468 or T, Yao, J, J, A,
P.

互(1983’) L680にあるが、それらは、エネ
ルギーバンド構造を改良したものでは全くない。
(1983') L680, but they do not improve the energy band structure at all.

本発明は、かかる知見に基づく研究の結果なされたもの
である。すなわち、本発明によるならば、チャンネル層
が、格子定数の異なる2種類の化合物半導体薄膜層を交
互に積層して構成されて、チャンネル層をなす化合物半
導体の結晶構造または原子配列が変化してその化合物半
導体のエネルギーバンド構造が変化し、チャンネル層内
での高電界印加状態における電子移動度が高くなるよう
にしたことを特徴とする化合物半導体装置が提供される
The present invention was made as a result of research based on such knowledge. That is, according to the present invention, the channel layer is constituted by alternately stacking two types of compound semiconductor thin film layers having different lattice constants, and the crystal structure or atomic arrangement of the compound semiconductor forming the channel layer is changed. Provided is a compound semiconductor device characterized in that the energy band structure of the compound semiconductor is changed and electron mobility is increased in a high electric field application state within a channel layer.

昨月 以上のような化合物半導体装置において、チャンネル層
をなす各薄膜層の化合物半導体は、互いに格子定数が異
なり且つ極めて薄いので、各層の実質的部分にわたって
エネルギーバンド構造が変化し、その結果、高電界印加
状態でのチャンネル層内における電子輸送過程でのイン
ターバレイ散乱やインパクトイオナイゼーションによる
散乱を低下させあるいは電子の有効質量を減少させる。
In the compound semiconductor device described above, the compound semiconductors in each thin film layer forming the channel layer have different lattice constants and are extremely thin, so the energy band structure changes over a substantial portion of each layer, resulting in high It reduces intervalley scattering or scattering due to impact ionization in the electron transport process in the channel layer when an electric field is applied, or reduces the effective mass of electrons.

従って、高電界印加状態でのチャンネル層における電子
移動度が高く維持される。
Therefore, the electron mobility in the channel layer is maintained high when a high electric field is applied.

実施例 以下に図面を参照して本発明について詳細に説明する。Example The present invention will be described in detail below with reference to the drawings.

第1図は、本発明による化合物半導体装置の実施例を図
解した断面図である。なお、第1図は、本発明を電界効
果トランジスタ(以下FETと略す)として実施した例
を示している。
FIG. 1 is a cross-sectional view illustrating an embodiment of a compound semiconductor device according to the present invention. Note that FIG. 1 shows an example in which the present invention is implemented as a field effect transistor (hereinafter abbreviated as FET).

第1図に示すFETは、半絶縁性InP基板10上に、
InAsとAlAsをそれぞれ数原子層づつ交互にそれ
ぞれ約80層づつ積層させた結晶構造を有するへlXI
n1−X八S化合物半導体結晶多層薄膜層11がFET
のチャンネル層として形成されている。その多層薄膜層
11の全体の膜厚は0.1μmである。なお、このよう
な多層薄膜層11は、半絶縁性のInP基板10上にM
BE成長法を用いて形成した。
The FET shown in FIG. 1 has a semi-insulating InP substrate 10,
IXI has a crystal structure in which approximately 80 layers of InAs and AlAs are alternately stacked each with several atomic layers each.
n1-X8S compound semiconductor crystal multilayer thin film layer 11 is FET
It is formed as a channel layer. The total thickness of the multilayer thin film layer 11 is 0.1 μm. Incidentally, such a multilayer thin film layer 11 is formed by depositing M on a semi-insulating InP substrate 10.
It was formed using the BE growth method.

さらに、多層薄膜層11の表面には、AuGeNiオー
ミック接合電極12を蒸着し、ソースとドレイン電極を
形成した。また、AIショットキー接合電極13を蒸着
し、ゲート電極を形成した。
Furthermore, AuGeNi ohmic junction electrodes 12 were deposited on the surface of the multilayer thin film layer 11 to form source and drain electrodes. Further, an AI Schottky junction electrode 13 was deposited to form a gate electrode.

へuGeNiオーミック電極12を形成する際の蒸着な
らびに合金処理によって、Au原子が化合物半導体結晶
多層薄膜層11中に拡散していく。これによって、化合
物半導体結晶多層薄膜層11内の積層構造の周期性が乱
れ、この領域14における結晶構造は、従来のへ]xI
n+−Js混晶結晶と同一になってしまう。
Au atoms are diffused into the compound semiconductor crystal multilayer thin film layer 11 by vapor deposition and alloying treatment when forming the uGeNi ohmic electrode 12 . As a result, the periodicity of the laminated structure in the compound semiconductor crystal multilayer thin film layer 11 is disturbed, and the crystal structure in this region 14 is changed to the conventional one.
It becomes the same as the n+-Js mixed crystal.

この結果、この領域でのエネルギーバンド構造も、従来
のAlxIn+−Js混晶結晶と同一になり、オーミッ
ク接合を形成することに何ら弊害は生じなかった。この
ような拡散によって化合物半導体多層薄膜層の積層構造
の周期性が破壊されるという類似の現象は、すでにN、
■olonyak他、A、 P、 L、 39 (19
81)102などで発表されている。
As a result, the energy band structure in this region was also the same as that of the conventional AlxIn+-Js mixed crystal, and no problem occurred in forming an ohmic junction. A similar phenomenon in which the periodicity of the laminated structure of a compound semiconductor multilayer thin film layer is destroyed by such diffusion has already been observed in N,
■olonyak et al., A, P, L, 39 (19
81) Published in 102, etc.

第1図に示すソース電極12、ドレイン電極12、ゲー
ト電極13などについては、従来のFET構造作製時に
行なわれている従来技術を用いることにより、FETと
しての機能を有することも確認できた。
It was also confirmed that the source electrode 12, drain electrode 12, gate electrode 13, etc. shown in FIG. 1 had a function as an FET by using the conventional technique used in manufacturing a conventional FET structure.

さらに、第1図における化合物半導体結晶多層薄膜層1
1において、結晶構造やエネルギーバンド構造が同一組
成を有するへ1□Ir+、−11八s混晶結晶とは全く
異なることについても、X線回折や光吸収などの測定を
行なうことによって確認できた。この結果、第2図に示
すように高電界領域における電子移動度が、同一組成を
有する従来の^]jn+−、、As混晶の場合に比べて
約3倍に向上した。
Furthermore, the compound semiconductor crystal multilayer thin film layer 1 in FIG.
It was also confirmed by measurements such as X-ray diffraction and optical absorption that the crystal structure and energy band structure of 1. . As a result, as shown in FIG. 2, the electron mobility in the high electric field region was improved by about three times compared to the conventional ^]jn+-,,As mixed crystal having the same composition.

また、上記実施例と同様な構成で、化合物半導体結晶多
層薄膜層11の各薄膜層の厚さを1原子面から100原
子面の間で変えたところ、従来例に比較しての差に相違
はあったが、同様な結果が得られた。但し、同一組成の
薄膜層は、多層薄膜層全体にわたって同一の厚さが好ま
しい。
In addition, when the thickness of each thin film layer of the compound semiconductor crystal multilayer thin film layer 11 was changed from 1 atomic plane to 100 atomic planes using the same structure as the above example, there was a difference compared to the conventional example. However, similar results were obtained. However, the thin film layers having the same composition preferably have the same thickness throughout the multilayer thin film layer.

なお、上記実施例において、多層薄膜層の構成層として
InAs (格子定数6.058人)、AlAs (5
,662人)、を使用した。しかし、多層薄膜層は、上
記した実施例の組合せに限られるものではなく、他の組
合せも可能であり、格子定数の差が0.3%以上、更に
好ましくは1.5%以上あれば、程度に差はあるが同様
な効果が得られる。例えば、格子定数の大きな化合物半
導体としては、TnAsの他に、Ga5b(6,095
人)、In5b(6,479人)などがあり、また、格
子定数の小さな化合物半導体としては、へIへsのはか
に、GaAs (5,654人)、Ga P (5,4
51人)、In P (5,869人)などがある。そ
れらを適当に組合せて3元系の化合物半導体多層薄膜チ
ャンネル層を形成することもできる。
In the above embodiment, InAs (lattice constant: 6.058), AlAs (5.0
, 662 people) were used. However, the multilayer thin film layer is not limited to the combinations of the above embodiments, and other combinations are also possible, and if the difference in lattice constant is 0.3% or more, more preferably 1.5% or more, Although there are differences in degree, similar effects can be obtained. For example, as a compound semiconductor with a large lattice constant, in addition to TnAs, Ga5b (6,095
In addition, as compound semiconductors with small lattice constants, there are GaAs (5,654 people), In5b (5,479 people), etc.
51 people), In P (5,869 people), etc. A ternary compound semiconductor multilayer thin film channel layer can also be formed by appropriately combining them.

発明の効果 本発明の半導体装置によれば、従来のFETのチャンネ
ル層に用いられている化合物半導体の結晶構造または原
子配列を変えることにより、エネルギーバンド構造を変
え、高電界印加状態での半導体結晶内における種々の散
乱を低下させ、また有効質量をし減少させることが可能
となる。従って、高電界印加状態における電子の移動度
が、従来の化合物半導体混晶に比べて速い。
Effects of the Invention According to the semiconductor device of the present invention, by changing the crystal structure or atomic arrangement of the compound semiconductor used in the channel layer of a conventional FET, the energy band structure is changed, and the semiconductor crystal becomes more stable under high electric field application. This makes it possible to reduce various types of scattering within the space and also to reduce the effective mass. Therefore, electron mobility under high electric field application is faster than in conventional compound semiconductor mixed crystals.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明による化合物半導体装置を実施したF
ETの概略断面図、 第2図は、本発明の化合物半導体装置における電子移動
度の印加電界強度依存性の測定結果を示すグラフ、 第3図は、従来の高電子移動度トランジスタの概略断面
図、 第4図は、従来の高電子移動度トランジスタにおける電
子移動度の印加電界強度依存性の測定結果を示すグラフ
、 第5図は、化合物半導体のエネルギーバンド構造を説明
するための図である。 〔主な参照番号〕 1・・半絶縁性GaAs基板、 2・・GaAsバッファ層、 3・・Ga八へチャンネル層、 4・・電子供給層、 6・・ゲート電極、 7・・合金化領域、 8・・ソース電極、ドレイン電極、 9・・二次元電子ガス、 10・・InP基板 11・・多層薄膜層、 12・・ソース電極、ドレイン電極、 13・・ゲート電極、 14・・混晶化領域
FIG. 1 shows an F in which a compound semiconductor device according to the present invention is implemented.
A schematic cross-sectional view of ET; FIG. 2 is a graph showing the measurement results of the dependence of electron mobility on applied electric field strength in the compound semiconductor device of the present invention; FIG. 3 is a schematic cross-sectional view of a conventional high electron mobility transistor. , FIG. 4 is a graph showing measurement results of the dependence of electron mobility on applied electric field strength in a conventional high electron mobility transistor, and FIG. 5 is a diagram for explaining the energy band structure of a compound semiconductor. [Main reference numbers] 1. Semi-insulating GaAs substrate, 2. GaAs buffer layer, 3. Ga channel layer, 4. Electron supply layer, 6. Gate electrode, 7. Alloying region , 8... Source electrode, drain electrode, 9... Two-dimensional electron gas, 10... InP substrate 11... Multilayer thin film layer, 12... Source electrode, drain electrode, 13... Gate electrode, 14... Mixed crystal area

Claims (3)

【特許請求の範囲】[Claims] (1)チャンネル層が、格子定数の異なる2種類の化合
物半導体薄膜層を交互に積層して構成されて、チャンネ
ル層をなす化合物半導体の結晶構造または原子配列が変
化してその化合物半導体のエネルギーバンド構造が変化
し、チャンネル層内での高電界印加状態における電子移
動度が高くなるようになされていることを特徴とする化
合物半導体装置。
(1) The channel layer is constructed by alternately stacking two types of compound semiconductor thin film layers with different lattice constants, and the crystal structure or atomic arrangement of the compound semiconductor forming the channel layer changes to change the energy band of the compound semiconductor. 1. A compound semiconductor device characterized in that the structure is changed so that electron mobility increases in a high electric field application state within a channel layer.
(2)前記化合物半導体多層薄膜層の各層の厚さは1〜
100原子面の範囲内にあることを特徴とする特許請求
の範囲第1項記載の化合物半導体装置。
(2) The thickness of each layer of the compound semiconductor multilayer thin film layer is 1 to 1.
2. The compound semiconductor device according to claim 1, wherein the area is within a range of 100 atomic planes.
(3)前記格子定数の相違は、0.3%以上であること
を特徴とする特許請求の範囲第1項記載の化合物半導体
装置。
(3) The compound semiconductor device according to claim 1, wherein the difference in lattice constant is 0.3% or more.
JP5202385A 1985-03-15 1985-03-15 Compound semiconductor device Granted JPS61210677A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP5202385A JPS61210677A (en) 1985-03-15 1985-03-15 Compound semiconductor device
CA000504069A CA1256590A (en) 1985-03-15 1986-03-13 Compound semiconductor device with layers having different lattice constants
AU54742/86A AU577934B2 (en) 1985-03-15 1986-03-14 Compound semiconductor device
EP86103425A EP0196517B1 (en) 1985-03-15 1986-03-14 Compound semiconductor device
DE8686103425T DE3672360D1 (en) 1985-03-15 1986-03-14 CONNECTING SEMICONDUCTOR COMPONENT.
KR1019860001897A KR860007745A (en) 1985-03-15 1986-03-15 Compound Semiconductor Device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5202385A JPS61210677A (en) 1985-03-15 1985-03-15 Compound semiconductor device

Publications (2)

Publication Number Publication Date
JPS61210677A true JPS61210677A (en) 1986-09-18
JPH0354853B2 JPH0354853B2 (en) 1991-08-21

Family

ID=12903214

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5202385A Granted JPS61210677A (en) 1985-03-15 1985-03-15 Compound semiconductor device

Country Status (1)

Country Link
JP (1) JPS61210677A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63144579A (en) * 1986-12-08 1988-06-16 Nec Corp Field-effect element
US5206528A (en) * 1990-11-30 1993-04-27 Nec Corporation Compound semiconductor field effect transistor having a gate insulator formed of insulative superlattice layer

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS607121A (en) * 1983-06-24 1985-01-14 Nec Corp Structure of super lattice
JPS6028273A (en) * 1983-07-26 1985-02-13 Nec Corp Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS607121A (en) * 1983-06-24 1985-01-14 Nec Corp Structure of super lattice
JPS6028273A (en) * 1983-07-26 1985-02-13 Nec Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63144579A (en) * 1986-12-08 1988-06-16 Nec Corp Field-effect element
US5206528A (en) * 1990-11-30 1993-04-27 Nec Corporation Compound semiconductor field effect transistor having a gate insulator formed of insulative superlattice layer

Also Published As

Publication number Publication date
JPH0354853B2 (en) 1991-08-21

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