JPH02130933A - Field effect transistor - Google Patents

Abstract

PURPOSE:To improve device characteristics by constituting an electron channel layer of a superlattice layer composed of an InAs layer and a GaAs layer, and setting the thickness of the superlattice layer as a value by which crystallizability is not deteriorated. CONSTITUTION:On a high resistive InP substrate 11, the following are grown in each specified value by electron beam epitaxy method or the like: a non- doped AlInAs layer 12, a non-doped InGaAs layer 13, an InAs/GaAs superlattice layer 14 turning to an electron channel layer, a non-doped AlInAs layer 15, an N-type AlInAs layer 16 doped with Si, and a non-doped AlInAs layer 17. Next, by ordinary lithography art, a source electrode 18 and a drain electrode 19 of AuGe/Ni are patterned; by performing spike alloy at a specified temperature in an H atmosphere, an ohmic electrode is formed, and further an Al gate electrode 20 is formed. In this case, lattice unconformity between InAs and GaAs is present in the layer 14, so that these are laminated under the condition that the thickness of the superlattice layer is 500Angstrom or less in which dislocation is not caused.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high-speed field effect transistor that utilizes a two-dimensional electron gas.

[Conventional technology]

InCraAs, which is lattice-matched to InP, has been studied for application to ultrahigh-speed devices because of its high room temperature mobility and electron saturation speed. For example, Hirobe et al.
International Conference on Gallium Arsenide and Related Compounders (Insti juts of Physics Co.
nference 5eries Number 79
+ P529+1985), N-Al InAs/I
An nGaAs selectively doped FET has been announced, and a structural cross-sectional view of its main parts is shown in FIG.

The FET shown in FIG. 2 is manufactured as follows.

That is, high-resistance InP is produced by molecular beam epitaxy.
On the substrate 1, a non-doped 7'A1[
5000 layers of nAs layer 2, non-doped InGaAs layer 3
1000 people, non-doped A11nAs layer 4 by 20 people,
It is formed by sequentially growing 250 Si-doped N-Aj2 InAs layers 5 and 100 undoped A11nAs layers 6, and then providing a gate electrode 9, a source electrode 7, and a drain electrode 8.

This selectively doped FET has a transconductance of 440 m5/mm at room temperature and 7
At 7K, a characteristic of 700 m5/mm (7) was obtained.

In order to further improve the characteristics of this element, InGaAs
Improving the electron transport properties of is very effective. However, nQaAs has a mixed crystal scattering mechanism for electrons peculiar to mixed crystals, which limits the electron transport properties of InGaAs, especially at low temperatures. A method that is expected to be able to overcome this point is described, for example, by Yao et al. in the Japanese Journal of Applied Physics (Jpn, J. Appl, Phys, vol.
2. Nol, L680.1983), which uses 1nAS and GaAs instead of InGaAs.
It uses a superlattice of In this case, InAs and G
Since aAs has a lattice mismatch of about 7%, it has been proposed that this can be achieved by stacking layers with a sufficiently thin thickness (50 Å or less) so as not to generate dislocations.

[Problem to be solved by the invention]

However, although there are many reports on the growth of InAs and GaAs superlattices, the crystallinity is still not in a sufficient condition.
Furthermore, there are no reports of its application to actual semiconductor devices.

The object of the present invention is to provide InAs and Ga with good crystallinity.
The object of the present invention is to provide a high-performance field effect transistor using an As superlattice layer.

[Means to solve the problem]

The present invention provides a field effect transistor that uses two-dimensional electron gas, in which the electron channel layer is a superlattice layer consisting of an InAs layer and a GaAs layer, and the thickness of the superlattice layer is such that crystallinity does not deteriorate. characterized by something.

Further, according to the present invention, the thickness of the superlattice layer is set to 500 Å or less.

[Effect]

According to the present invention, the electron channel layer contains 1nAs, Qa, 6. An s-monolayer superlattice is used. In experiments conducted by the present inventors, the crystallinity of a monoatomic layer superlattice deteriorates as its total thickness increases, and particularly when the thickness exceeds 500 layers, the crystallinity deteriorates rapidly. Therefore, good electrical characteristics can be obtained by using this thickness as an eaves reduction of about 500 people, and when applying this to a field effect transistor using two-dimensional electron gas, the thickness is sufficient to improve the characteristics. It is thick enough.

〔Example〕

FIG. 1 is a structural sectional view of main parts for explaining one embodiment of a field effect transistor according to the present invention. This field effect transistor is manufactured as follows.

First, a high resistance 1nP base + ffj 11 is coated with a substrate temperature of 450° C. by, for example, electron beam epitaxy (MBE method).
In , 5000 people formed the non-doped AlInAs layer I2, 1000 people formed the non-doped InGaAs layer 13, 200 to 500 people formed the InAs/GaAs superlattice layer 14 which becomes the electron channel layer, and the non-doped A4! r
nAsJii15 for 80 people, Si for 2 XIO"cm-
``Grow 200 doped N-A1!nAS layers (electron supply layer) 16 and 100 undoped AlInAs layers 17.

Next, AuGe/
A source electrode 18 and a drain electrode 19 of Ni were patterned, and spike alloying was performed at 380° C. for 2 minutes in a hydrogen atmosphere to form an ohmic electrode, and further an Affi gate electrode 20 was formed.

Note that the non-doped InGaAs layer 12, 15, 17, the non-doped InGaAs layer 13, the N-AjllnAs layer 1
No. 6 was grown under conditions of lattice matching to InP.

In the field effect transistor having the above configuration, the gate electrode 20 controls the two-dimensional electron gas induced in the electron channel layer 14, and the source electrode 18 and the drain electrode 19
makes ohmic contact with the two-dimensional electron gas.

As described above, according to this embodiment, AI that lattice matches InP on the InPJJ board II! nAsJi, InGaA
InAs layer is formed and further becomes an electron channel layer.
A superlattice layer 14 consisting of a GaAs layer and a GaAs layer is sequentially formed,
Furthermore, Ai! has an N-type impurity that becomes an electron supply layer that is lattice-matched to InP! InAS layers 16 are sequentially formed, and a gate electrode 20 for controlling two-dimensional electron gas induced in the electron channel layer, and a source electrode 18 and a drain electrode 19 for making ohmic contact with the two-dimensional electron gas are provided.

Next, the I n A s / G a A s superlattice IJ
The configuration of No. 14 will be described below. InAs and GaAs are about 7
% lattice misalignment, and when stacking them, it is necessary to stack each layer under film thickness conditions that do not cause dislocations.

In this case, the InAs layer and GaAsJi become elastically strained, a so-called strained superlattice, and good crystallinity can be obtained. I
The layer thicknesses of nAs and GaAs are such that the lattice constant of the entire superlattice is I
The same film thickness was chosen for each to almost match nP.

The inventors of the present invention have confirmed using a transmission electron microscope that dislocations do not occur when InAs and GaAS are laminated to the same thickness, each layer having a thickness of approximately 10 atomic layers or less (approximately 30 people). Furthermore, it was confirmed that the crystallinity deteriorates rapidly when the total thickness exceeds 500 layers, and the characteristics of the manufactured field effect transistor deteriorate.

This deterioration of crystallinity was confirmed by simultaneously observing the state of the crystal surface during crystal growth using reflection high-speed electron diffraction (RHEED), which revealed that the crystal growth mode shifted from two-dimensional growth (MBE) to three-dimensional growth. It is assumed that this occurs because of

Therefore, the total thickness of the InAs/Ga, As superlattice layer 14 is 50
It is necessary to make it 0 Å or less.

In addition, I n A s / Ga A s superlattice JW
The spread of the wave function of the two-dimensional electron gas induced in 14 extends from the non-doped AI InAs layer interface to about 200 degrees of eaves, so that I n A s / Ga
The thickness of the As superlattice layer 14 is preferably 200 Å or more.

〔Effect of the invention〕

The field effect transistor of the present invention is made of conventional InGaAs.
Compared to a field-effect transistor using only a channel for the channel, it was possible to obtain characteristics that were equivalent to or better than that of a field-effect transistor, and the improvement in characteristics was particularly noticeable at low temperatures.

[Brief explanation of drawings]

FIG. 1 is a structural sectional view of the main part for explaining an embodiment of the present invention, and FIG. 2 is a structural sectional view of the main part for explaining a conventional example. 1.11... High resistance InP substrate 2, 4. 6.12.15.17 3, 13・ 5.16・ 7.18・ 8.19・ 9.20・ 14・ ・ ・ ・ Non-dope Aj! InA three-layer non-doped InGaAs layer N-AlInAs layer source electrode drain electrode gate electrode InAs/GaAs superlattice layer

Claims (2)

[Claims] (1) In a field effect transistor that uses two-dimensional electron gas, the electron channel layer is a superlattice layer consisting of an InAs layer and a GaAs layer, and the thickness of this superlattice layer is such that crystallinity does not deteriorate. A field effect transistor characterized by: 2. The field effect transistor according to claim 1, wherein: (2) the thickness of the superlattice layer is 500 Å or less.