CN110085665A - The multi-functional superlattices super large-scale integration of novel multi-vitamin - Google Patents
The multi-functional superlattices super large-scale integration of novel multi-vitamin Download PDFInfo
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- CN110085665A CN110085665A CN201910372092.9A CN201910372092A CN110085665A CN 110085665 A CN110085665 A CN 110085665A CN 201910372092 A CN201910372092 A CN 201910372092A CN 110085665 A CN110085665 A CN 110085665A
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- 230000010354 integration Effects 0.000 title claims abstract description 28
- 229940088594 vitamin Drugs 0.000 title claims abstract description 26
- 239000011782 vitamin Substances 0.000 title claims abstract description 26
- 230000007704 transition Effects 0.000 claims abstract description 72
- 239000000758 substrate Substances 0.000 claims abstract description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 18
- 239000010703 silicon Substances 0.000 claims abstract description 18
- 238000013461 design Methods 0.000 claims abstract description 16
- 239000004047 hole gas Substances 0.000 claims abstract description 15
- 230000005533 two-dimensional electron gas Effects 0.000 claims abstract description 13
- 150000001875 compounds Chemical class 0.000 claims abstract description 10
- 230000005669 field effect Effects 0.000 claims description 39
- 238000002955 isolation Methods 0.000 claims description 26
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- 229910052581 Si3N4 Inorganic materials 0.000 claims description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 13
- 239000003990 capacitor Substances 0.000 claims description 9
- 230000015654 memory Effects 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 230000003471 anti-radiation Effects 0.000 abstract description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 44
- 239000000463 material Substances 0.000 description 33
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 28
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 28
- 229910052757 nitrogen Inorganic materials 0.000 description 24
- 238000005516 engineering process Methods 0.000 description 19
- 229910002601 GaN Inorganic materials 0.000 description 18
- 238000002294 plasma sputter deposition Methods 0.000 description 18
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 15
- 229910052733 gallium Inorganic materials 0.000 description 15
- 238000001816 cooling Methods 0.000 description 11
- 229910000838 Al alloy Inorganic materials 0.000 description 10
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 10
- 239000011810 insulating material Substances 0.000 description 10
- 239000000203 mixture Substances 0.000 description 10
- 238000004544 sputter deposition Methods 0.000 description 10
- 229910005540 GaP Inorganic materials 0.000 description 9
- 239000003638 chemical reducing agent Substances 0.000 description 9
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 9
- 238000000992 sputter etching Methods 0.000 description 9
- 238000002513 implantation Methods 0.000 description 8
- 239000012212 insulator Substances 0.000 description 8
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- 238000010586 diagram Methods 0.000 description 3
- 230000005621 ferroelectricity Effects 0.000 description 3
- 239000010408 film Substances 0.000 description 3
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- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000013473 artificial intelligence Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
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Classifications
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
- H01L29/157—Doping structures, e.g. doping superlattices, nipi superlattices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/735—Lateral transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/78391—Field effect transistors with field effect produced by an insulated gate the gate comprising a layer which is used for its ferroelectric properties
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/8605—Resistors with PN junctions
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors with potential-jump barrier or surface barrier
- H01L29/93—Variable capacitance diodes, e.g. varactors
Abstract
The present invention provides a kind of multi-functional superlattices super large-scale integration of novel multi-vitamin, comprising: substrate；Transition zone, setting is on the substrate；Component layer is arranged above the excessive layer, and component layer is to construct high-performance superlattices integrated circuit using based on the device that the property of superlattices integrated circuit two-dimensional electron gas and two-dimensional hole gas designs.High-performance superlattices integrated circuit is constructed using based on the device of the property of superlattices integrated circuit two-dimensional electron gas and two-dimensional hole gas design above transition zone, it is designed to that the multi-functional superlattices super large-scale integration of novel multi-vitamin (MDMFSL-ULSI:Multi-Dimension Multi-Functional Superlattice Ultra-Large Scale Integrated Circuit) is that based on two-dimensional electron gas and two-dimensional hole gas superlattices and quantum well and have many characteristics, such as the highly reliable anti-radiation anti-high and low-temp of ultrahigh speed, and design efficiency is high, the manufacturing process period is short, it is at low cost, the shortcoming of the above traditional silicon Yu compound integrated circuit will be greatly improved.
Description
Technical field
The present invention relates to technical field of integrated circuits, in particular to the ultra-large collection of a kind of multi-functional superlattices of novel multi-vitamin
At circuit.
Background technique
Currently, the super large-scale integration component and technique based on silicon materials be already close to quantum limit, no
It is only that device performance is restricted, and manufacturing process is sufficiently complex and cost is high.The big data of high speed development, artificial intelligence
Can and comprehensive data intelligence market in urgent need high-performance it is highly reliable and with acceptable cost novel ultra-large integrated electricity
Road.More importantly silicon super large-scale integration component has been increasingly difficult to meet artificial intelligence and space era to super
At a high speed, anti-high and low-temp, the particular/special requirements such as anti-radiation.
Summary of the invention
The present invention provides a kind of multi-functional superlattices super large-scale integration (MDMFSL-ULSI:Multi- of novel multi-vitamin
Dimension Multi-Functional Superlattice Ultra-Large Scale Integrated Circuit)
It is that based on two-dimensional electron gas and two-dimensional hole gas superlattices and Quantum Well and there is the highly reliable anti-radiation anti-height of ultrahigh speed
The features such as temperature, and design efficiency is high, the manufacturing process period is short, and it is at low cost, the above traditional silicon and compound will be greatly improved
The shortcoming of integrated circuit.
The present invention provides a kind of multi-functional superlattices super large-scale integration of novel multi-vitamin, comprising:
Substrate；
Transition zone, setting is on the substrate；
Component layer is arranged above the excessive layer, and component layer is using based on superlattices integrated circuit two dimension electricity
The device of the property of sub- gas and two-dimensional hole gas design constructs high-performance superlattices integrated circuit.Wherein, component layer
Both it can be constructed with homogeneity superlattice layer, such as intrinsic gallium nitride (GaN), n type gallium nitride (GaN), p-type gallium nitride (GaN) etc. can also
It is constructed with using heterogeneous superlattice layer, such as intrinsic nitrogen calorize gallium Ga (x) Al (1-x) N, N-type nitrogen calorize gallium Ga (x) Al (1-x) N, P
Type nitrogen calorize gallium Ga (x) Al (1-x) N etc..
In one embodiment, substrate uses silicon, germanium or compound semiconductor.
In one embodiment, transition zone is one of using silica, silicon nitride and compound semiconductor layer.
In one embodiment, component layer is using based on superlattices integrated circuit two-dimensional electron gas and two-dimensional hole gas
The device of property design construct high-performance superlattices integrated circuit.
In one embodiment, it is designed based on the property of superlattices integrated circuit two-dimensional electron gas and two-dimensional hole gas
Device include p-type superlattices field effect transistor, N-type superlattices field effect transistor, NPN type superlattices bipolar transistor
Pipe, positive-negative-positive superlattices bipolar junction transistor, superlattices flash memories, superlattices capacitor and variodenser, superlattices resistance and change
Device and superlattices inductance are hindered in conjunction with varinodr one or more of them.
In one embodiment, substrate bottom is evenly distributed with multiple through-holes.
The multidimensional structure of the multi-functional superlattices super large-scale integration of novel multi-vitamin by according to the needs of device performance with
Each specific function block of channel insulator separation simultaneously uses special process (such as ion implanting and quick high-temp thermal annealing work
Skill) to form multiple carriers (electronics or hole) channel.
In one embodiment, N-type superlattices field effect transistor includes:
First superlattices intrinsic layer is set to above the transition zone；
Superlattices N-type layer is arranged above the first superlattices intrinsic layer；
The top of the superlattices N-type layer is arranged in second superlattices intrinsic layer；
First superlattice p-type layer is arranged above the second superlattices intrinsic layer；
The top of the first superlattice p-type layer is arranged in first grid insulating layer；
First N+ conductive layer, from the upper surface of the first superlattice p-type layer and to perpendicular to first superlattice p-type
Lower surface of the direction of layer downward through extremely the first superlattices intrinsic layer；
First channel insulating layer, for annular, from the upper surface of the first superlattice p-type layer and to perpendicular to described first
Downward through to the lower surface of the first superlattices intrinsic layer, the first N+ conductive layer is arranged in the direction of superlattice p-type layer
In the first channel insulating layer；
First ohmic contact layer, be arranged above the first N+ conductive layer and with the first N+ conductive layer contact；
Second ohmic contact layer is arranged above the first grid insulating layer and connects with the first grid insulating layer
Touching,
First dielectric protection layer is arranged between first ohmic contact layer and the second ohmic contact layer；
Second dielectric protection layer is arranged on the outside of first ohmic contact layer.
Above-mentioned device configuration is only one of N-type superlattices field effect transistor multiple combinations simple combination.
In one embodiment, p-type superlattices field effect transistor includes:
Third superlattices intrinsic layer is set to above the transition zone；
Superlattice P-type layer is arranged above the third superlattices intrinsic layer；
The superlattice P-type layer top is arranged in 4th superlattices intrinsic layer；
First superlattice n-type layer is arranged above the 4th superlattices intrinsic layer；
The top of the first superlattice n-type layer is arranged in second grid insulating layer；
First P+ conductive layer, from the upper surface of the first superlattice n-type layer and to perpendicular to first superlattice n-type
Lower surface of the direction of layer downward through the extremely third superlattices intrinsic layer；
Second channel insulating layer is shape needed for device isolation, comprising: rectangle, annular wait close-shaped.From described
The upper surface of one superlattice n-type layer simultaneously surpasses to the direction perpendicular to the first superlattice n-type layer downward through to the third
The lower surface of lattice intrinsic layer, the first P+ conductive layer are arranged in the second channel insulating layer；
Third ohmic contact layer, be arranged above the first P+ conductive layer and with the first P+ conductive layer contact；
4th ohmic contact layer is arranged above the second grid insulating layer and connects with the second grid insulating layer
Touching,
Third dielectric protection layer is arranged between the third ohmic contact layer and the 4th ohmic contact layer；
4th dielectric protection layer is arranged on the outside of the third ohmic contact layer.
The above device configuration is only one of p-type superlattices field effect transistor multiple combinations simple combination.
In one embodiment, positive-negative-positive superlattices bipolar transistor be divided into superlattice planes type P-N-P bipolar transistor and
Superlattices vertical-type P-N-P bipolar transistor；
Wherein, superlattices vertical-type P-N-P bipolar transistor includes:
Superlattices collector P-type layer is arranged above the transition zone；
Superlattices base stage N-type layer is arranged above the superlattices collector P-type layer；
Superlattices emitter P-type layer is arranged above the superlattices base stage N-type layer；
2nd P+ conductive layer and the 2nd N+ conductive layer, from the upper surface of the superlattices emitter P-type layer and to perpendicular to
Lower surface of the direction of the superlattices emitter P-type layer downward through the extremely superlattices collector P-type layer；
Third channel insulating layer is shape, such as rectangle needed for device isolation, annular, etc.；From the superlattices emitter P
The upper surface of type layer and to the direction perpendicular to the superlattices emitter P-type layer downward through to the superlattices collector P
The lower surface of type layer, the 2nd P+ conductive layer and the 2nd N+ conductive layer are arranged in the third channel insulating layer；
5th ohmic contact layer, be arranged above the 2nd P+ conductive layer and with the 2nd P+ conductive layer contact；
6th ohmic contact layer, be arranged above the 2nd N+ conductive layer and with the 2nd N+ conductive layer contact；
7th ohmic contact layer, be arranged above the superlattices emitter P-type layer and with the superlattices emitter p-type
Layer contact,
5th dielectric protection layer, setting is in the 7th ohmic contact layer and the 5th ohmic contact layer, 7th ohm described
Between contact layer and the 6th ohmic contact layer；
The 5th ohmic contact layer, the 6th ohmic contact layer outside is arranged in 6th dielectric protection layer.
7th dielectric protection layer is arranged in the superlattices emitter P-type layer and the 2nd N+ conductive layer, the super crystalline substance
Between lattice emitter P-type layer and the 2nd P+ conductive layer；
Wherein, superlattice planes type P-N-P bipolar transistor includes:
Superlattice planes type P-N-P bipolar transistor includes:
Superlattices emitter p type island region is cylindrical type, is arranged above the transition zone；
Superlattices base stage N-type region 46 is arranged above the transition zone for annular and is set in the superlattices emitter
On the outside of p type island region；
Superlattices collector p type island region is arranged above the transition zone for annular and is set in setting in the superlattices
46 outside of base stage N-type region；
4th channel insulating layer is set in and is arranged on the outside of superlattices base stage p type island region for annular, also, described the
Four channel insulating layers are arranged above the transition zone or setting is above the transition zone and embedding after the transition zone
Enter in the substrate；
8th ohmic contact layer is circle, is arranged above superlattices emitter p type island region and sends out with the superlattices
The contact of emitter-base bandgap grading p type island region；
9th ohmic contact layer be annular, be arranged above the superlattices base stage N-type region 46 and with the superlattices base
Pole N-type region 46 contacts；
Tenth ohmic contact layer be annular, be arranged above superlattices collector p type island region and with the superlattices collection
The contact of electrode p type island region；
8th dielectric protection layer is arranged between the 8th ohmic contact layer and the 9th ohmic contact layer for annular；
9th dielectric protection layer is arranged between the 9th ohmic contact layer and the tenth ohmic contact layer for annular；
The outside of the tenth ohmic contact layer is arranged in for annular in tenth dielectric protection layer.
In one embodiment, NPN type superlattices bipolar transistor be divided into superlattices vertical-type N-P-N bipolar transistor and
Superlattice planes type N-P-N bipolar transistor；
Wherein, superlattices vertical-type N-P-N bipolar transistor includes:
Superlattices collector N-type layer is arranged above the transition zone；
Superlattices base stage P-type layer is arranged above the superlattices collector N-type layer；
Superlattices emitter N-type layer is arranged above the superlattices base stage P-type layer；
3rd P+ conductive layer and the 3rd N+ conductive layer, from the upper surface of the superlattices emitter N-type layer and to perpendicular to
Lower surface of the direction of the superlattices emitter N-type layer downward through the extremely superlattices collector N-type layer；
5th channel insulating layer is shape, such as rectangle needed for device isolation, annular, etc. from the superlattices emitter N
The upper surface of type layer and to the direction perpendicular to the superlattices emitter N-type layer downward through to the superlattices collector N
The lower surface of type layer, the 3rd P+ conductive layer and the 3rd N+ conductive layer are arranged in the 5th channel insulating layer；
11st ohmic contact layer, be arranged above the 3rd P+ conductive layer and with the 3rd P+ conductive layer contact；
12nd ohmic contact layer, be arranged above the 3rd N+ conductive layer and with the 3rd N+ conductive layer contact；
13rd ohmic contact layer, be arranged above the superlattices emitter N-type layer and with the superlattices emitter N
The contact of type layer,
11st dielectric protection layer, setting is in the 13rd ohmic contact layer and the 11st ohmic contact layer, described the
Between 13 ohmic contact layers and the 12nd ohmic contact layer；
The 11st ohmic contact layer, the 12nd ohmic contact layer outside is arranged in 12nd dielectric protection layer.
13rd dielectric protection layer, setting is in the superlattices emitter N-type layer and the 3rd N+ conductive layer, described super
Between lattice emission pole N-type layer and the 3rd P+ conductive layer；
Wherein, superlattice planes type N-P-N bipolar transistor includes:
Superlattices emitter N-type region is cylindrical type, is arranged above the transition zone；
Superlattices base stage p type island region is arranged above the transition zone for annular and is set in the superlattices emitter N
On the outside of type area；
Superlattices collector N-type region is arranged above the transition zone for annular and is set in setting in the superlattices
On the outside of base stage p type island region；
6th channel insulating layer is set in and is arranged on the outside of the superlattices collector N-type region for annular, also, described
After 6th channel insulating layer is arranged above the transition zone or is arranged above the transition zone and runs through the transition zone
It is embedded in the substrate；
14th ohmic contact layer be circle, be arranged above the superlattices emitter N-type region and with the superlattices
The contact of emitter N-type region；
15th ohmic contact layer be annular, be arranged above superlattices base stage p type island region and with the superlattices base
The contact of pole p type island region；
16th ohmic contact layer be annular, be arranged above the superlattices collector N-type region and with the superlattices
The contact of collector N-type region；
14th dielectric protection layer is arranged for annular in the 14th ohmic contact layer and the 15th ohmic contact layer
Between；
15th dielectric protection layer, for annular, be arranged the 15th ohmic contact layer and the 16th ohmic contact layer it
Between；
The outside of the 16th ohmic contact layer is arranged in for annular in 16th dielectric protection layer.
In one embodiment, superlattices capacitor includes: with variodenser
5th superlattices intrinsic layer is set to above the transition zone；
Second superlattice p-type layer is arranged above the 5th superlattices intrinsic layer；
The top of the second superlattice p-type layer is arranged in 6th superlattices intrinsic layer；
First superlattices low-resistance N-type layer is arranged above the 6th superlattices intrinsic layer；
4th P+ conductive layer and the 4th N+ conductive layer from the upper surface of the first superlattices low-resistance N-type layer and to perpendicular to
Lower surface of the direction of the first superlattices low-resistance N-type layer downward through extremely the 5th superlattices intrinsic layer；
7th channel insulating layer is shape, such as rectangle needed for device isolation, annular, etc. from the first superlattices low-resistance
The upper surface of N-type layer and to the direction perpendicular to the first superlattices low-resistance N-type layer downward through to the 5th superlattices
The lower surface of intrinsic layer, the 4th P+ conductive layer and the 4th N+ conductive layer are arranged in the 7th channel insulating layer；
17th ohmic contact layer, be arranged above the first superlattices low-resistance N-type layer and with first superlattices
The contact of low-resistance N-type layer；
18th ohmic contact layer, be arranged above the 4th N+ conductive layer and with the 4th N+ conductive layer contact；
19th ohmic contact layer, be arranged above the 4th P+ conductive layer and with the 4th P+ conductive layer contact；
17th dielectric protection layer is arranged in the 17th ohmic contact layer and the 18th ohmic contact layer, the 17th
Between ohmic contact layer and the 19th ohmic contact layer；
The 18th ohmic contact layer, the 19th ohmic contact layer outside is arranged in 18th dielectric protection layer.
In one embodiment, superlattices resistance includes: with rheostat
7th superlattices intrinsic layer is set to above the transition zone；
Third superlattice p-type layer is arranged above the 7th superlattices intrinsic layer；
The top of the third superlattice p-type layer is arranged in 8th superlattices intrinsic layer；
Second superlattices low-resistance N-type layer is arranged above the 8th superlattices intrinsic layer；
5th P+ conductive layer and the 5th N+ conductive layer from the upper surface of the second superlattices low-resistance N-type layer and to perpendicular to
Lower surface of the direction of the second superlattices low-resistance N-type layer downward through extremely the 7th superlattices intrinsic layer；
8th channel insulating layer is shape, such as rectangle needed for device isolation, annular, etc. from the second superlattices low-resistance
The upper surface of N-type layer and to the direction perpendicular to the second superlattices low-resistance N-type layer downward through to the 7th superlattices
The lower surface of intrinsic layer, the 5th P+ conductive layer and the 5th N+ conductive layer are arranged in the 8th channel insulating layer；
One the 20th ohmic contact layer, the 21st ohmic contact layer and the 22nd ohmic contact layer are
One group, share two groups；
20th ohmic contact layer, be arranged above the second superlattices low-resistance N-type layer and with second superlattices
The contact of low-resistance N-type layer；
21st ohmic contact layer is arranged above the 5th N+ conductive layer and connects with the 5th N+ conductive layer
Touching；
22nd ohmic contact layer is arranged above the 5th P+ conductive layer and connects with the 5th P+ conductive layer
Touching；
19th dielectric protection layer is arranged in the 20th ohmic contact layer and the 21st ohmic contact layer, second
Between ten ohmic contact layers and the 22nd ohmic contact layer；
The 21st ohmic contact layer, the 22nd ohmic contact layer outside is arranged in 20th dielectric protection layer.
In one embodiment, superlattices inductance includes: with varinodr
9th superlattices intrinsic layer is set to above the transition zone；
4th superlattice p-type layer is arranged above the 9th superlattices intrinsic layer；
The top of the 4th superlattice p-type layer is arranged in tenth superlattices intrinsic layer；
Third superlattices low-resistance N-type layer is arranged above the tenth superlattices intrinsic layer；
6th P+ conductive layer and the 6th N+ conductive layer from the upper surface of the third superlattices low-resistance N-type layer and to perpendicular to
Lower surface of the direction of the third superlattices low-resistance N-type layer downward through extremely the 9th superlattices intrinsic layer；
9th channel insulating layer is shape, such as rectangle needed for device isolation, annular, etc. from the third superlattices low-resistance
The upper surface of N-type layer and to the direction perpendicular to the third superlattices low-resistance N-type layer downward through to the 9th superlattices
The lower surface of intrinsic layer, the 6th P+ conductive layer and the 6th N+ conductive layer are arranged in the 9th channel insulating layer；
One the 23rd ohmic contact layer, the 24th ohmic contact layer and the 25th ohmic contact layer
It is one group, shares two groups；
23rd ohmic contact layer is arranged above the third superlattices low-resistance N-type layer and super brilliant with the third
The contact of lattice low-resistance N-type layer；
24th ohmic contact layer is arranged above the 6th N+ conductive layer and connects with the 6th N+ conductive layer
Touching；
25th ohmic contact layer is arranged above the 6th P+ conductive layer and connects with the 6th P+ conductive layer
Touching；
21st dielectric protection layer, setting the 23rd ohmic contact layer and the 24th ohmic contact layer,
Between 23rd ohmic contact layer and the 24th ohmic contact layer；
The 24th ohmic contact layer, the 25th ohmic contact layer outside is arranged in 22nd dielectric protection layer.
In one embodiment, superlattices flash memories include: including being imitated by doping P channel n-i-p-i superlattices field
Answer ferroelectric transistor or doping N channel n-i-p-i superlattices field-effect ferroelectric transistor；
Wherein, P channel n-i-p-i superlattices field-effect ferroelectric transistor includes:
11st superlattices intrinsic layer is set to above the transition zone；
Superlattices low-resistance P-type layer is arranged above the 11st superlattices intrinsic layer；
The top of the superlattices low-resistance P-type layer is arranged in 12nd superlattices intrinsic layer；
Second superlattice n-type layer is arranged above the 12nd superlattices intrinsic layer；
The top of the second superlattice n-type layer is arranged in first ferroelectric thin film layer；
7th P+ conductive layer, from the upper surface of the second superlattice n-type layer and to perpendicular to second superlattice n-type
Lower surface of the direction of layer downward through extremely the 11st superlattices intrinsic layer；
Tenth channel insulating layer is shape, such as rectangle needed for device isolation, annular, etc. from second superlattice n-type
The upper surface of layer and to the direction perpendicular to the second superlattice n-type layer downward through to the 11st superlattices intrinsic layer
Lower surface, the 7th P+ conductive layer is arranged in the tenth channel insulating layer；
26th ohmic contact layer, be arranged above first ferroelectric thin film layer and with first ferroelectric thin film layer
Contact,
27th ohmic contact layer is arranged above the 7th P+ conductive layer and connects with the 7th P+ conductive layer
Touching；
23rd dielectric protection layer, setting the 26th ohmic contact layer and the 27th ohmic contact layer it
Between；
24th dielectric protection layer is arranged on the outside of the 27th ohmic contact layer；
Wherein, N channel n-i-p-i superlattices field-effect ferroelectric transistor includes:
13rd superlattices intrinsic layer is set to above the transition zone；
Superlattices low-resistance N-type layer is arranged above the 13rd superlattices intrinsic layer；
The top of the superlattices low-resistance N-type layer is arranged in 14th superlattices intrinsic layer；
5th superlattice p-type layer is arranged above the 14th superlattices intrinsic layer；
The top of the 5th superlattice p-type layer is arranged in second ferroelectric thin film layer；
7th N+ conductive layer, from the upper surface of the 5th superlattice p-type layer and to perpendicular to the 5th superlattice p-type
Lower surface of the direction of layer downward through extremely the 13rd superlattices intrinsic layer；
11st channel insulating layer is shape, such as rectangle needed for device isolation, annular, etc. from the 5th superlattice P
The upper surface of type layer is simultaneously intrinsic downward through extremely the 13rd superlattices to the direction perpendicular to the 5th superlattice p-type layer
The lower surface of layer, the 7th N+ conductive layer are arranged in the 11st channel insulating layer；
28th ohmic contact layer, be arranged above second ferroelectric thin film layer and with second ferroelectric thin film layer
Contact,
29th ohmic contact layer is arranged above the 7th N+ conductive layer and connects with the 7th N+ conductive layer
Touching；
25th dielectric protection layer, setting the 28th ohmic contact layer and the 29th ohmic contact layer it
Between；
26th dielectric protection layer is arranged on the outside of the 29th ohmic contact layer.
The utility model multi-dimensional multifunctional superlattices super large-scale integration has the advantage that
1, ultrahigh speed: higher by 10 to hundreds times than conventional macro-scale integrated circuit speed.Up to trillion hertz of (THz) ranges.
2. high-performance: various field effect transistors, bipolar transistor (vertical-type and plane) and spy can be made full use of
Different function element, such as: superlattices flash memories, superlattices capacitor and variodenser, superlattices resistance and rheostat and superlattices
The different high performance integrated circuit of the designs such as inductance and varinodr.
3. highly reliable: anti-high and low-temp and radiation resistance are greatly better than traditional silicon and compound integrated circuit.
4. design flexibility: utilizing the property of superlattices integrated circuit two-dimensional electron gas and two-dimensional hole gas and special
Device, can manufacture and design various high performance integrated circuits, such as linear integrated circuit, and Analogous Integrated Electronic Circuits is linearly mixed with simulation
Integrated circuit, central processing unit (CPU), etc..
5. technique simplifies, with short production cycle, cost is reasonable: since superlattices integrated circuit two-dimensional electron gas and two are utilized
The property of hole gas is tieed up come ic component needed for designing industrial application, processing step can greatly simplify, such as light
Die sinking plate number and corresponding processing step can reduce 30 percent, so that production cycle and cost all can significantly optimize.
Other features and advantages of the present invention will be illustrated in the following description, also, partly becomes from specification
It obtains it is clear that understand through the implementation of the invention.The objectives and other advantages of the invention can be by written explanation
Specifically noted structure is achieved and obtained in book, claims and attached drawing.
Below by drawings and examples, technical scheme of the present invention will be described in further detail.
Detailed description of the invention
Attached drawing is used to provide further understanding of the present invention, and constitutes part of specification, with reality of the invention
It applies example to be used to explain the present invention together, not be construed as limiting the invention.In the accompanying drawings:
Fig. 1 is a kind of schematic diagram of the multi-functional superlattices super large-scale integration of novel multi-vitamin in the embodiment of the present invention；
Fig. 2 is a kind of schematic cross-section of N-type superlattices field effect transistor in the embodiment of the present invention；
Fig. 3 is a kind of schematic cross-section of p-type superlattices field effect transistor in the embodiment of the present invention；
Fig. 4 is a kind of schematic cross-section of superlattices vertical-type P-N-P bipolar transistor in the embodiment of the present invention；
Fig. 5 is a kind of schematic cross-section of superlattice planes type P-N-P bipolar transistor in the embodiment of the present invention；
Fig. 6 is a kind of top view of superlattice planes type P-N-P bipolar transistor in the embodiment of the present invention；
Fig. 7 is a kind of schematic cross-section of superlattices vertical-type N-P-N bipolar transistor in the embodiment of the present invention；
Fig. 8 is a kind of schematic cross-section of superlattice planes type N-P-N bipolar transistor in the embodiment of the present invention；
Fig. 9 is a kind of top view of superlattice planes type N-P-N bipolar transistor in the embodiment of the present invention；
Figure 10 is a kind of schematic cross-section of superlattices capacitor and variodenser in the embodiment of the present invention；
Figure 11 is a kind of superlattices resistance and rheostatic schematic cross-section in the embodiment of the present invention；
Figure 12 is a kind of superlattices resistance and rheostatic top view in the embodiment of the present invention；
Figure 13 is a kind of schematic cross-section of superlattices inductance and varinodr in the embodiment of the present invention；
Figure 14 is a kind of top view of superlattices inductance and varinodr in the embodiment of the present invention；
Figure 15 is a kind of section signal of P channel n-i-p-i superlattices field-effect ferroelectric transistor in the embodiment of the present invention
Figure；
Figure 16 is a kind of section signal of N channel n-i-p-i superlattices field-effect ferroelectric transistor in the embodiment of the present invention
Figure；
Figure 17 is a kind of schematic diagram of autonomous cooling insulating layer in the embodiment of the present invention；
Figure 18 is a kind of schematic diagram for completely cutting off insulating layer in the embodiment of the present invention.
Specific embodiment
Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings, it should be understood that preferred reality described herein
Apply example only for the purpose of illustrating and explaining the present invention and is not intended to limit the present invention.
The embodiment of the invention provides the multi-functional superlattices super large-scale integration of novel multi-vitamin, as shown in Figure 1, packet
It includes:
Substrate 1；
Transition zone 2 is arranged above the substrate 1；
Component layer 3 is arranged above the excessive layer 2, and component layer 3 is using based on superlattices integrated circuit two dimension
The device of the property of electron gas and two-dimensional hole gas design constructs high-performance superlattices integrated circuit.
The working principle and beneficial effect of the above-mentioned multi-functional superlattices super large-scale integration of novel multi-vitamin:
It is set above transition zone using the property based on superlattices integrated circuit two-dimensional electron gas and two-dimensional hole gas
The device of meter constructs high-performance superlattices integrated circuit, is designed to the multi-functional superlattices super large-scale integration of novel multi-vitamin
(MDMFSL-ULSI:Multi-Dimension Multi-Functional Superlattice Ultra-Large Scale
Integrated Circuit) it is based on two-dimensional electron gas and two-dimensional hole gas superlattices and Quantum Well and to have high speed high
Features such as reliable anti-radiation anti-high and low-temp, and design efficiency is high, the manufacturing process period is short, at low cost, will greatly improve with
The shortcoming of upper traditional silicon and compound integrated circuit.
In one embodiment, substrate is using silicon or germanium or compound semiconductor.
In one embodiment, transition zone is one of using silica, silicon nitride and compound semiconductor layer.
To realize that component layer constitutes the multi-functional superlattices super large-scale integration of novel multi-vitamin, in one embodiment
In, the device based on the design of the property of superlattices integrated circuit two-dimensional electron gas and two-dimensional hole gas includes p-type superlattices
Field effect transistor, N-type superlattices field effect transistor, NPN type superlattices bipolar transistor, positive-negative-positive superlattices bipolar transistor
Pipe, superlattices flash memories, superlattices capacitor and variodenser, superlattices resistance and rheostat and superlattices inductance and varinodr
One or more of them combines.
To keep heat dissipation quicker, in one embodiment, substrate bottom is evenly distributed with multiple through-holes.Pass through what is gathered
Aperture, the heat for generating circuit operation distribute faster.
In one embodiment, as shown in Fig. 2, N-type superlattices field effect transistor includes:
First superlattices intrinsic layer 11 is set to 2 top of transition zone；
Superlattices N-type layer 12 is arranged above the first superlattices intrinsic layer 11；
The top of the superlattices N-type layer 12 is arranged in second superlattices intrinsic layer 13；
First superlattice p-type layer 14 is arranged above the second superlattices intrinsic layer 13；
The top of the first superlattice p-type layer 14 is arranged in first grid insulating layer 15；
First N+ conductive layer 20 surpasses from the upper surface of the first superlattice p-type layer 14 and the first crystalline substance to perpendicular to described
Lower surface of the direction of lattice P-type layer 14 downward through extremely the first superlattices intrinsic layer 11；
First channel insulating layer 19 is shape, such as rectangle needed for device isolation, annular, etc. from first superlattice P
The upper surface of type layer 14 and to the direction perpendicular to the first superlattice p-type layer 14 downward through to the first superlattices sheet
The lower surface of layer 11 is levied, the inside of the first channel insulating layer 19 is arranged in the first N+ conductive layer 20；
First ohmic contact layer 18 is arranged above the first N+ conductive layer 20 and connects with the first N+ conductive layer 20
Touching；
Second ohmic contact layer 17, be arranged above the first grid insulating layer 15 and with the first grid insulating layer
15 contacts,
First dielectric protection layer 16 is arranged between first ohmic contact layer 18 and the second ohmic contact layer 17；
18 outside of the first ohmic contact layer is arranged in second dielectric protection layer 21.
Wherein, the first N+ conductive layer can be set to one it is endless belt-shaped may be set to be two pieces or muti-piece it is independent its
The N+ conductive layer of his shape；When the first N+ conductive layer is one endless belt-shaped, the first ohmic contact layer can be synchronized and is set as
It is endless belt-shaped, it may be set to be the N+ conductive layer of two pieces or the independent other shapes of muti-piece.
It the principle of above-mentioned N-type superlattices field effect transistor and has the beneficial effect that
N-type superlattices field effect transistor is adulterated super brilliant by the intrinsic layer (the first superlattices intrinsic layer) of doped superlattice
The N-type layer (superlattices N-type layer) of lattice, the intrinsic layer (the second superlattices intrinsic layer) of superlattices, the P-type layer (of doped superlattice
One superlattice p-type layer), the composition such as the first N+ conductive layer.For the performance requirement for reaching integrated circuit, the repetition of more layers can be designed
Structure, such as p-i-n-i-p-i-n-i-p-i., homogeneity superlattice layer, such as silicon, gallium nitride (GaN) , Arsenic not only can be used
Gallium (GaAs), can also be used heterogeneous superlattice layer, Ru Dan Arsenic gallium Ga (x) As (1-x) N, nitrogen calorize gallium Ga (x) Al (1-x) N,
Nitrogen gallium phosphide Ga (x) Ps (1-x) N, etc. forming special Quantum Well using different forbidden bandwidths to promote device performance.Use low energy
Ion implantation technique forms P+ conductive layer, and Ohmic electrode is formed with plasma sputtering technology, but plasma sputtering material will
Depending on the material of superlattice semiconductor layer, such as to gallium nitride material, it is generally available titanium-aluminium alloy, etc..Gate insulating layer can
With silicon nitride etc..It is needed between device with insulator separation (the first channel insulating layer).Channel insulating layer can with special channel from
Sub- etching technics simultaneously then chemically-mechanicapolish polishes to be formed plus insulating materials ion sputtering.Ion note can also be used in channel insulating layer
Enter to be formed PN junction channel insulating layer, if it is desired, can reach on same superlattices integrated circuit using a variety of isolation methods
Optimize to maximum performance.
As shown in figure 3, the p-type superlattices field effect transistor includes:
Third superlattices intrinsic layer 22 is set to 2 top of transition zone；
Superlattice P-type layer 23 is arranged above the third superlattices intrinsic layer 22；
The superlattice P-type layer 23 top is arranged in 4th superlattices intrinsic layer 24；
First superlattice n-type layer 25 is arranged above the 4th superlattices intrinsic layer 24；
The top of the first superlattice n-type layer 25 is arranged in second grid insulating layer 26；
First P+ conductive layer 27 surpasses from the upper surface of the first superlattice n-type layer 25 and the first crystalline substance to perpendicular to described
Lower surface of the direction of lattice N-type layer 25 downward through the extremely third superlattices intrinsic layer 22；
Second channel insulating layer 28, is rectangle or annular, from the upper surface of the first superlattice n-type layer 25 and to vertical
In the direction of the first superlattice n-type layer 25 downward through to the lower surface of the third superlattices intrinsic layer 22, described the
One P+ conductive layer 27 is arranged in the second channel insulating layer 28；
Third ohmic contact layer 30 is arranged above the first P+ conductive layer 27 and connects with the first P+ conductive layer 27
Touching；
4th ohmic contact layer 32, be arranged above the second grid insulating layer 26 and with the second grid insulating layer
26 contacts,
Third dielectric protection layer 31 is arranged between the third ohmic contact layer 30 and the 4th ohmic contact layer 32；
30 outside of third ohmic contact layer is arranged in 4th dielectric protection layer 29.
It the principle of aforementioned p-type superlattices field effect transistor and has the beneficial effect that
By the intrinsic layer (third superlattices intrinsic layer) of doped superlattice, the P-type layer (superlattice P-type of doped superlattice
Layer), superlattices intrinsic layer (the 4th superlattices intrinsic layer), the N-type layer (the first superlattice n-type layer) of doped superlattice, the first P+
The composition such as conductive layer.For the performance requirement for reaching integrated circuit, the repetitive structure of more layers, such as n-i-p-i--n-i- can be designed
p-i-n-i., homogeneity superlattice layer, such as silicon not only can be used, (GaN) , Arsenic gallium (GaAs), can also be used different gallium nitride
Matter superlattice layer, Ru Dan Arsenic gallium Ga (x) As (1-x) N, nitrogen calorize gallium Ga (x) Al (1-x) N, nitrogen gallium phosphide Ga (x) Ps (1-x)
N etc. forms special Quantum Well using different forbidden bandwidths to promote device performance.It is conductive that P+ is formed with low energy ion beam implantation technology
Layer, Ohmic electrode formed with plasma sputtering technology, but plasma sputtering material is by the material according to superlattice semiconductor layer
Depending on material, such as to gallium nitride material, it is generally available titanium-aluminium alloy etc..Gate insulating layer can use silicon nitride etc..It is needed between device
Use insulator separation.Channel insulating layer can be with special channel ion etching technics and plus insulating materials ion sputtering deposit then
Chemically mechanical polishing is formed.Channel insulating layer can also be used ion implanting and form PN junction channel insulating layer, if it is desired, can be
A variety of isolation methods are used on same superlattices integrated circuit to reach maximum performance optimization.
Positive-negative-positive superlattices bipolar transistor is divided into superlattice planes type P-N-P bipolar transistor and superlattices vertical-type P-
N-P bipolar transistor, NPN type superlattices bipolar transistor is divided into superlattices vertical-type N-P-N bipolar transistor and superlattices are flat
Face type N-P-N bipolar transistor.
As shown in figure 4, superlattices vertical-type P-N-P bipolar transistor includes:
Superlattices collector P-type layer 33 is arranged above the transition zone 2；
Superlattices base stage N-type layer 34 is arranged above the superlattices collector P-type layer 33；
Superlattices emitter P-type layer 35 is arranged above the superlattices base stage N-type layer 34；
2nd P+ conductive layer 37 and the 2nd N+ conductive layer 36, from the upper surface of the superlattices emitter P-type layer 35 and to
Perpendicular to the superlattices emitter P-type layer 35 direction downward through to the superlattices collector P-type layer 33 lower surface；
Third channel insulating layer 38, is rectangle or annular, from the upper surface of the superlattices emitter P-type layer 35 and to hanging down
Directly in the direction of the superlattices emitter P-type layer 35 downward through the lower surface of the extremely superlattices collector P-type layer 33, institute
It states the 2nd P+ conductive layer 37 and the 2nd N+ conductive layer 36 is arranged in the third channel insulating layer 38；
5th ohmic contact layer 39 is arranged above the 2nd P+ conductive layer 37 and connects with the 2nd P+ conductive layer 3
Touching；
6th ohmic contact layer 40 is arranged above the 2nd N+ conductive layer 36 and connects with the 2nd N+ conductive layer 36
Touching；
7th ohmic contact layer 41 is arranged above the superlattices emitter P-type layer 35 and emits with the superlattices
Pole P-type layer 35 contacts,
5th dielectric protection layer 42, setting is in the 7th ohmic contact layer 41 and the 5th ohmic contact layer 39, described the
Between seven ohmic contact layers 41 and the 6th ohmic contact layer 40；
The 5th ohmic contact layer 39,40 outside of the 6th ohmic contact layer is arranged in 6th dielectric protection layer 43.
7th dielectric protection layer 44 is arranged in the superlattices emitter P-type layer 35 and the 2nd N+ conductive layer 36, institute
It states between superlattices emitter P-type layer 35 and the 2nd P+ conductive layer 37.
Superlattices vertical-type P-N-P bipolar transistor by doped superlattice collector P-type layer (superlattices collector p-type
Layer), the base stage N-type layer (superlattices base stage N-type layer) of doped superlattice, emitter P-type layer (the superlattices transmitting of doped superlattice
Pole P-type layer), the composition such as the 2nd P+ conductive layer and the 2nd N+ conductive layer.For the performance requirement for reaching bipolar transistor integrated circuit,
The structure of more layers, such as p-i-n-i-p can be designed., it not only can be used homogeneity superlattice layer, such as silicon, gallium nitride (GaN),
Heterogeneous superlattice layer, Ru Dan Arsenic gallium Ga (x) As (1-x) N, nitrogen calorize gallium Ga (x) Al (1- can also be used in Arsenic gallium (GaAs)
X) N, nitrogen gallium phosphide Ga (x) Ps (1-x) N, etc. forming special Quantum Well using different forbidden bandwidths to promote device performance.With
Low energy ion beam implantation technology is respectively formed N+ and P+ conductive layer, and Ohmic electrode is formed with plasma sputtering technology, but wait from
Daughter sputter material, such as to gallium nitride material, is generally available titanium-aluminium alloy for depending on the material of foundation superlattice semiconductor layer,
Deng.Gate insulating layer can use silicon nitride etc..It needs to use insulator separation between device.Channel insulating layer can use special channel ion
Etching technics simultaneously then chemically-mechanicapolish polishes to be formed plus insulating materials ion sputtering.Ion implanting can also be used in channel insulating layer
PN junction channel insulating layer is formed, if it is desired, can have reached on same superlattices integrated circuit using a variety of isolation methods
Maximum performance optimization.
As shown in Figure 5 and Figure 6, superlattice planes type P-N-P bipolar transistor includes:
Superlattices emitter p type island region 45 is cylindrical type, is arranged above the transition zone；
Superlattices base stage N-type region 46 is arranged above the transition zone for annular and is set in the superlattices emitter
45 outside of p type island region；
Superlattices collector p type island region 47 is arranged above the transition zone for annular and is set in setting in the super crystalline substance
46 outside of lattice pole N-type region；
4th channel insulating layer 48 is set in and is arranged on the outside of superlattices base stage p type island region for annular, also, described
4th channel insulating layer 48 is arranged above the transition zone or is arranged above the transition zone and runs through the transition zone
After be embedded in the substrate；
8th ohmic contact layer 49 be circle, be arranged above superlattices emitter p type island region 45 and with the super crystalline substance
Lattice emitter p type island region 45 contacts；
9th ohmic contact layer 51 be annular, be arranged above the superlattices base stage N-type region 46 and with the superlattices
Base stage N-type region 46 contacts；
Tenth ohmic contact layer 53 be annular, be arranged above superlattices collector p type island region 47 and with the super crystalline substance
Lattice collector p type island region 47 contacts；
8th dielectric protection layer 50 is arranged for annular in the 8th ohmic contact layer 49 and the 9th ohmic contact layer 51
Between；
9th dielectric protection layer 52, for annular, be arranged the 9th ohmic contact layer 51 and the tenth ohmic contact layer 53 it
Between；
The outside of the tenth ohmic contact layer 53 is arranged in for annular in tenth dielectric protection layer 54.
Superlattice planes type P-N-P bipolar transistor by doped superlattice collector p type island region (superlattices collector p-type
Area), the base stage N-type region (superlattices base stage N-type region 46) of doped superlattice, p type island region (the superlattices hair of doped superlattice emitter
Emitter-base bandgap grading p type island region), the composition such as p-type and N-type ohmic contact layer.For the performance requirement for reaching bipolar transistor integrated circuit, can design
The structure of more layers, such as p-i-n-i-p., homogeneity superlattice layer, such as silicon, gallium nitride (GaN) , Arsenic gallium not only can be used
(GaAs), heterogeneous superlattice layer, Ru Dan Arsenic gallium Ga (x) As (1-x) N, nitrogen calorize gallium Ga (x) Al (1-x) N, nitrogen can also be used
Gallium phosphide Ga (x) Ps (1-x) N, etc. forming special Quantum Well using different forbidden bandwidths to promote device performance.With low energy from
Sub- injection technique is respectively formed superlattices collector p type island region, doped superlattice base stage N-type region 46, doped superlattice emitter p-type
Area etc..Ohmic electrode is formed with plasma sputtering technology, but plasma sputtering material will be according to superlattice semiconductor layer
Depending on material, such as to gallium nitride material, it is generally available titanium-aluminium alloy, etc..Gate insulating layer can use silicon nitride etc..It is needed between device
Use insulator separation.Channel insulating layer can then be changed with special channel ion etching technics and plus insulating materials ion sputtering
Mechanical polishing is learned to be formed.Channel insulating layer can also be used ion implanting and form PN junction channel insulating layer, if it is desired, can be same
Maximum performance optimization is had reached using a variety of isolation methods on one superlattices integrated circuit.
As shown in fig. 7, superlattices vertical-type N-P-N bipolar transistor includes:
Superlattices collector N-type layer 65 is arranged above the transition zone 2；
Superlattices base stage P-type layer 66 is arranged above the superlattices collector N-type layer 65；
Superlattices emitter N-type layer 67 is arranged above the superlattices base stage P-type layer 66；
3rd P+ conductive layer 68 and the 3rd N+ conductive layer 69, from the upper surface of the superlattices emitter N-type layer 67 and to
Perpendicular to the superlattices emitter N-type layer 67 direction downward through to the superlattices collector N-type layer 65 lower surface；
5th channel insulating layer 70, for annular, from the upper surface of the superlattices emitter N-type layer 67 and to perpendicular to institute
State lower surface of the direction of superlattices emitter N-type layer 67 downward through the extremely superlattices collector N-type layer 65, the third
P+ conductive layer 68 and the 3rd N+ conductive layer 69 are arranged in the 5th channel insulating layer 70；
11st ohmic contact layer 72, be arranged above the 3rd P+ conductive layer 68 and with the 3rd P+ conductive layer 68
Contact；
12nd ohmic contact layer 71, be arranged above the 3rd N+ conductive layer 69 and with the 3rd N+ conductive layer 69
Contact；
13rd ohmic contact layer 73 is arranged above the superlattices emitter N-type layer 67 and sends out with the superlattices
Emitter-base bandgap grading N-type layer 67 contacts,
11st dielectric protection layer 74, setting the 13rd ohmic contact layer 73 and the 11st ohmic contact layer 72,
Between 13rd ohmic contact layer 73 and the 12nd ohmic contact layer 71；
The 11st ohmic contact layer 72,71 outside of the 12nd ohmic contact layer is arranged in 12nd dielectric protection layer 75.
13rd dielectric protection layer 76, setting the superlattices emitter N-type layer 67 and the 3rd N+ conductive layer 69,
Between the superlattices emitter N-type layer 67 and the 3rd P+ conductive layer 68.
Superlattices vertical-type N-P-N bipolar transistor by doped superlattice collector N-type layer (superlattices collector N-type
Layer), the base stage P-type layer (superlattices base stage P-type layer) of doped superlattice, emitter N-type layer (the superlattices transmitting of doped superlattice
Pole N-type layer), the composition such as the 3rd P+ conductive layer and the 3rd N+ conductive layer.For the performance requirement for reaching bipolar transistor integrated circuit,
The structure of more layers, such as n-i-p-i-n can be designed., it not only can be used homogeneity superlattice layer, such as silicon, gallium nitride (GaN),
Heterogeneous superlattice layer, Ru Dan Arsenic gallium Ga (x) As (1-x) N, nitrogen calorize gallium Ga (x) Al (1- can also be used in Arsenic gallium (GaAs)
X) N forms special Quantum Well using different forbidden bandwidths to promote device performance.N+ is respectively formed with low energy ion beam implantation technology
And P+ conductive layer, Ohmic electrode are formed with plasma sputtering technology, but plasma sputtering material will be according to superlattices half
Depending on the material of conductor layer, such as to gallium nitride material, it is generally available titanium-aluminium alloy, etc..Gate insulating layer can use silicon nitride etc..Device
It needs to use insulator separation between part.Channel insulating layer can be splashed with special channel ion etching technics and plus insulating materials ion
Then chemically mechanical polishing is penetrated to be formed.
Channel insulating layer can also be used ion implanting and form PN junction channel insulating layer, if it is desired, can be in same super crystalline substance
Maximum performance optimization is had reached using a variety of isolation methods on lattice integrated circuit.
As shown in Figure 8 and Figure 9, superlattice planes type N-P-N bipolar transistor includes:
Superlattices emitter N-type region 55 is cylindrical type, is arranged above the transition zone 2；
Superlattices base stage p type island region 56 is arranged above the transition zone 2 for annular and is set in the superlattices transmitting
55 outside of pole N-type region；
Superlattices collector N-type region 57 is arranged above the transition zone 2 for annular and is set in setting described super
56 outside of lattice base stage p type island region；
6th channel insulating layer 58 is set in setting in 57 outside of superlattices collector N-type region for annular, also,
The 6th channel insulating layer 58 is arranged above the transition zone 2 or is arranged above the transition zone 2 and runs through described
It is embedded in after transition zone 2 in the substrate；
14th ohmic contact layer 59 is circle, is arranged above the superlattices emitter N-type region 55 and surpasses with described
Lattice emission pole N-type region 55 contacts；
15th ohmic contact layer 61 be annular, be arranged above superlattices base stage p type island region 56 and with the super crystalline substance
Lattice pole p type island region 56 contacts；
16th ohmic contact layer 63 is annular, is arranged above the superlattices collector N-type region 57 and surpasses with described
Lattice collector N-type region 57 contacts；
14th dielectric protection layer 60, for annular, setting connects in the 14th ohmic contact layer 59 and the 15th ohm
Between contact layer 61；
The 15th ohmic contact layer 61 and the 16th Ohmic contact is arranged for annular in 15th dielectric protection layer 62
Between layer 63；
The outside of the 16th ohmic contact layer 63 is arranged in for annular in 16th dielectric protection layer 64.
Superlattice planes type N-P-N bipolar transistor by doped superlattice collector N-type region (superlattices collector N-type
Area), the base stage p type island region (superlattices base stage p type island region) of doped superlattice, emitter N-type region (the superlattices transmitting of doped superlattice
Pole N-type region), the composition such as ohmic contact layer.For the performance requirement for reaching bipolar transistor integrated circuit, the knot of more layers can be designed
Structure, such as n-i-p-i-n., it not only can be used homogeneity superlattice layer, such as silicon, gallium nitride (GaN) , Arsenic gallium (GaAs),
Heterogeneous superlattice layer, Ru Dan Arsenic gallium Ga (x) As (1-x) N, nitrogen calorize gallium Ga (x) Al (1-x) N, nitrogen gallium phosphide Ga can be used
(x) Ps (1-x) N etc. forms special Quantum Well using different forbidden bandwidths to promote device performance.With low energy ion beam implantation technology
It is respectively formed superlattices collector N-type region, doped superlattice base stage p type island region, doped superlattice emitter N-type region, etc..Ohm electricity
Pole is formed with plasma sputtering technology, but plasma sputtering material by according to superlattice semiconductor layer material depending on, such as
To gallium nitride material, it is generally available titanium-aluminium alloy, etc..Gate insulating layer can use silicon nitride etc..It needs to use insulating layer between device
Isolation.Channel insulating layer can then be chemically-mechanicapolish polished with special channel ion etching technics and plus insulating materials ion sputtering
It is formed.Channel insulating layer can also be used ion implanting and form PN junction channel insulating layer, if it is desired, can be in same superlattices collection
Optimize at using a variety of isolation methods to have reached maximum performance on circuit.
As shown in Figure 10, the superlattices capacitor includes: with variodenser
5th superlattices intrinsic layer 77 is set to 2 top of transition zone；
Second superlattice p-type layer 78 is arranged above the 5th superlattices intrinsic layer 77；
The top of the second superlattice p-type layer 78 is arranged in 6th superlattices intrinsic layer 79；
First superlattices low-resistance N-type layer 80 is arranged above the 6th superlattices intrinsic layer 79；
4th P+ conductive layer 81 and the 4th N+ conductive layer 82 from the upper surface of the first superlattices low-resistance N-type layer 80 and to
Perpendicular to the first superlattices low-resistance N-type layer 80 direction downward through to the 5th superlattices intrinsic layer 77 following table
Face；
7th channel insulating layer 83, for annular, from the upper surface of the first superlattices low-resistance N-type layer 80 and to perpendicular to
The direction of the first superlattices low-resistance N-type layer 80 downward through to the 5th superlattices intrinsic layer 77 lower surface, it is described
4th P+ conductive layer 81 and the 4th N+ conductive layer 82 are arranged in the 7th channel insulating layer 83；
17th ohmic contact layer 84 is arranged above the first superlattices low-resistance N-type layer 80 and the first surpasses with described
Lattice low-resistance N-type layer 80 contacts；
18th ohmic contact layer 85, be arranged above the 4th N+ conductive layer 82 and with the 4th N+ conductive layer 82
Contact；
19th ohmic contact layer 86, be arranged above the 4th P+ conductive layer 81 and with the 4th P+ conductive layer 81
Contact；
17th dielectric protection layer 87, setting the 17th ohmic contact layer 84 and the 18th ohmic contact layer 85,
Between 17th ohmic contact layer 84 and the 19th ohmic contact layer 86；
The 18th ohmic contact layer 85,86 outside of the 19th ohmic contact layer is arranged in 18th dielectric protection layer 88.
Superlattices n-i-p-i diode and capacitance of PN junction variodenser (superlattices capacitor and variodenser) are by superlattices intrinsic layer
(the 5th superlattices intrinsic layer), the base stage P-type layer (the second superlattice p-type layer) of doped superlattice, (six surpasses superlattices intrinsic layer
Lattice intrinsic layer), the N-type layer (the first superlattices low-resistance N-type layer) of doped superlattice, the 4th P+ conductive layer and the 4th N+ conductive layer
Deng composition.For the performance requirement for reaching bipolar transistor integrated circuit, the structure of more layers, such as n-i-p-i- can be designed
n., homogeneity superlattice layer, such as silicon not only can be used, (heterogeneous super crystalline substance can also be used in GaN) , Arsenic gallium (GaAs) to gallium nitride
Compartment, Ru Dan Arsenic gallium Ga (x) As (1-x) N, nitrogen calorize gallium Ga (x) Al (1-x) N, nitrogen gallium phosphide Ga (x) Ps (1-x) N etc., benefit
Special Quantum Well is formed with different forbidden bandwidths to promote device performance.N+ and P+ are respectively formed with low energy ion beam implantation technology
Conductive layer, Ohmic electrode are formed with plasma sputtering technology, but plasma sputtering material will be according to superlattice semiconductor layer
Material depending on, such as to gallium nitride material, be generally available titanium-aluminium alloy, etc..Gate insulating layer can use silicon nitride etc..Between device
It needs to use insulator separation.Channel insulating layer can be with special channel ion etching technics and plus insulating materials ion sputtering then
Chemically mechanical polishing is formed.Channel insulating layer can also be used ion implanting and form PN junction channel insulating layer, if it is desired, can be
Maximum performance optimization is had reached using a variety of isolation methods on same superlattices integrated circuit.
As shown in figure 11, the superlattices resistance includes: with rheostat
7th superlattices intrinsic layer 89 is set to 2 top of transition zone；
Third superlattice p-type layer 90 is arranged above the 7th superlattices intrinsic layer 89；
The top of the third superlattice p-type layer 90 is arranged in 8th superlattices intrinsic layer 91；
Second superlattices low-resistance N-type layer 92 is arranged above the 8th superlattices intrinsic layer 91；
The 5th P+ conductive layer 93 and the 5th N+ conductive layer 94 are from the upper surface of the second superlattices low-resistance N-type layer 92
And to the direction perpendicular to the second superlattices low-resistance N-type layer 92 downward through under extremely the 7th superlattices intrinsic layer 89
Surface；
8th channel insulating layer 95, is rectangle or annular, from the upper surface of the second superlattices low-resistance N-type layer 92 and to
Perpendicular to the second superlattices low-resistance N-type layer 92 direction downward through to the 7th superlattices intrinsic layer 89 following table
Face, the 5th P+ conductive layer 93 and the 5th N+ conductive layer 94 are arranged in the 8th channel insulating layer 95；
One the 20th 96, the 21st ohmic contact layer 97 of ohmic contact layer and the 22nd Ohmic contact
Layer 98 is one group, shares two groups；
20th ohmic contact layer 96 is arranged above the second superlattices low-resistance N-type layer 92 and the second surpasses with described
Lattice low-resistance N-type layer 92 contacts；
21st ohmic contact layer 97, be arranged above the 5th N+ conductive layer 94 and with the 5th N+ conductive layer
94 contacts；
22nd ohmic contact layer 98, be arranged above the 5th P+ conductive layer 93 and with the 5th P+ conductive layer
93 contacts；
19th dielectric protection layer 99 is arranged in the 20th ohmic contact layer 96 and the 21st ohmic contact layer
97, between the 20th ohmic contact layer 96 and the 22nd ohmic contact layer 98；
The 21st ohmic contact layer 97, the 22nd ohmic contact layer 98 is arranged in 20th dielectric protection layer 100
Outside.
As shown in figure 12, in one embodiment, superlattices inductance and varinodr include two group of the 5th P+ conductive layer 93 and
5th N+ conductive layer 94 and two group of the 20th ohmic contact layer 96, the 21st ohmic contact layer 97 and the 22nd ohm connect
Contact layer 98.Wherein the 9th channel insulating layer 107 is that there are the annulars of drum vacancy；One group is respectively set at the both ends of drum vacancy
5th P+ conductive layer 93 and the 5th N+ conductive layer 94 and the 20th ohmic contact layer 96, the 21st ohmic contact layer 97 and second
12 ohmic contact layers 98.
(seven surpasses crystalline substance by superlattices intrinsic layer for superlattices n-i-p-i resistance and rheostat (superlattices resistance and rheostat)
Lattice intrinsic layer), the base stage P-type layer (third superlattice p-type layer) of doped superlattice, (the 8th superlattices are intrinsic for superlattices intrinsic layer
Layer), the N-type layer (the second superlattices low-resistance N-type layer) of doped superlattice, the composition such as the 5th P+ conductive layer and the 5th N+ conductive layer.
For the performance requirement for reaching bipolar transistor integrated circuit, the structure of more layers, such as n-i-p-i-n can be designed., not only
Homogeneity superlattice layer, such as silicon can be used, (heterogeneous superlattice layer, Ru Dan Arsenic can also be used in GaN) , Arsenic gallium (GaAs) to gallium nitride
Change gallium Ga (x) As (1-x) N, nitrogen calorize gallium Ga (x) Al (1-x) N, nitrogen gallium phosphide Ga (x) Ps (1-x) N etc., utilizes different forbidden bands
Width forms special Quantum Well to promote device performance.N+ and P+ conductive layer, Europe are respectively formed with low energy ion beam implantation technology
Nurse electrode is formed with plasma sputtering technology, but plasma sputtering material by according to superlattice semiconductor layer material and
It is fixed, such as to gallium nitride material, it is generally available titanium-aluminium alloy, etc..Gate insulating layer can use silicon nitride etc..It is needed between device with exhausted
Edge layer isolation.Channel insulating layer can use special channel ion etching technics and the post-chemical mechanical plus insulating materials ion sputtering
Polishing is formed.Channel insulating layer can also be used ion implanting and form PN junction channel insulating layer, if it is desired, can be in same super crystalline substance
Maximum performance optimization is had reached using a variety of isolation methods on lattice integrated circuit.
As shown in figure 13, the superlattices inductance includes: with varinodr
9th superlattices intrinsic layer 101 is set to 2 top of transition zone；
4th superlattice p-type layer 102 is arranged above the 9th superlattices intrinsic layer 101；
The top of the 4th superlattice p-type layer 102 is arranged in tenth superlattices intrinsic layer 103；
Third superlattices low-resistance N-type layer 104 is arranged above the tenth superlattices intrinsic layer 103；
The 6th P+ conductive layer 105 and the 6th N+ conductive layer 106 are from the upper of the third superlattices low-resistance N-type layer 104
Surface and to the direction perpendicular to the third superlattices low-resistance N-type layer 104 downward through to the 9th superlattices intrinsic layer
101 lower surface；
9th channel insulating layer 107, be rectangle or annular, simultaneously from the upper surface of the third superlattices low-resistance N-type layer 104
To the direction perpendicular to the third superlattices low-resistance N-type layer 104 downward through under extremely the 9th superlattices intrinsic layer 101
Surface, the 6th P+ conductive layer 105 and the 6th N+ conductive layer 106 are arranged in the 9th channel insulating layer 107；
One the 23rd ohmic contact layer, 108, the 24th ohmic contact layers 109 and one the 25th ohm
Contact layer 110 is one group, shares two groups；
23rd ohmic contact layer 108 is arranged above the third superlattices low-resistance N-type layer 104 and with described the
The contact of three superlattices low-resistance N-type layers 104；
24th ohmic contact layer 109 is arranged above the 6th N+ conductive layer 106 and conductive with the 6th N+
Layer 106 contacts；
25th ohmic contact layer 110 is arranged above the 6th P+ conductive layer 105 and conductive with the 6th P+
Layer 105 contacts；
21st dielectric protection layer 111, setting connect in the 23rd ohmic contact layer 108 and the 24th ohm
Between contact layer 109, the 23rd ohmic contact layer 108 and the 24th ohmic contact layer 109；
The 24th ohmic contact layer 109, the 25th Ohmic contact is arranged in 22nd dielectric protection layer 112
110 outside of layer.
As shown in figure 14, in one embodiment, superlattices inductance and varinodr include two group of the 6th P+ conductive layer 105 and
6th N+ conductive layer 106 and two group of the 23rd ohmic contact layer 108, the 24th ohmic contact layer 109 and the 25th Europe
Nurse contact layer 110.Wherein the 9th channel insulating layer 107 is that there are the annulars of S type vacancy；It is respectively set at the both ends of S type vacancy
One group of the 6th P+ conductive layer 105 and the 6th N+ conductive layer 106 and the 23rd ohmic contact layer 108, the 24th Ohmic contact
The 109 and the 25th ohmic contact layer 110 of layer.
(nine surpasses crystalline substance by superlattices intrinsic layer for superlattices n-i-p-i inductance and varinodr (superlattices inductance and varinodr)
Lattice intrinsic layer), the base stage P-type layer (the 4th superlattice p-type layer) of doped superlattice, (the tenth superlattices are intrinsic for superlattices intrinsic layer
Layer), the N-type layer (third superlattices low-resistance N-type layer) of doped superlattice, the composition such as the 6th P+ conductive layer and the 6th N+ conductive layer.
For the performance requirement for reaching integrated circuit, the structure of more layers, such as n-i-p-i-n can be designed., homogeneity not only can be used
Superlattice layer, such as silicon, (heterogeneous superlattice layer, Ru Dan Arsenic gallium Ga (x) As can also be used in GaN) , Arsenic gallium (GaAs) to gallium nitride
(1-x) N, nitrogen calorize gallium Ga (x) Al (1-x) N, nitrogen gallium phosphide Ga (x) Ps (1-x) N etc., it is special to be formed using different forbidden bandwidths
Quantum Well is to promote device performance.Be respectively formed N+ and P+ conductive layer with low energy ion beam implantation technology, Ohmic electrode with etc. from
Daughter sputtering technology is formed, but plasma sputtering material by according to superlattice semiconductor layer material depending on, such as to gallium nitride
Material is generally available titanium-aluminium alloy, etc..Gate insulating layer can use silicon nitride etc..It needs to use insulator separation between device.Channel
Insulating layer can then be chemically-mechanicapolish polished and be formed with special channel ion etching technics and plus insulating materials ion sputtering.Channel
Insulating layer can also be used ion implanting and form PN junction channel insulating layer, if it is desired, can be on same superlattices integrated circuit
Maximum performance optimization is had reached using a variety of isolation methods.
N-i-p-i superlattices flash memories (superlattices flash memories) include by doping P channel n-i-p-i superlattices
Field-effect ferroelectric transistor or doping N channel n-i-p-i superlattices field-effect ferroelectric transistor.
As shown in figure 15, wherein P channel n-i-p-i superlattices field-effect ferroelectric transistor includes:
11st superlattices intrinsic layer 113 is set to 2 top of transition zone；
Superlattices low-resistance P-type layer 114 is arranged above the 11st superlattices intrinsic layer 113；
The top of the superlattices low-resistance P-type layer 114 is arranged in 12nd superlattices intrinsic layer 115；
Second superlattice n-type layer 116 is arranged above the 12nd superlattices intrinsic layer 115；
The top of the second superlattice n-type layer 116 is arranged in first ferroelectric thin film layer 117；
7th P+ conductive layer 118 the second surpasses from the upper surface of the second superlattice n-type layer 116 and to perpendicular to described
Lower surface of the direction of lattice N-type layer 116 downward through extremely the 11st superlattices intrinsic layer 113；
Tenth channel insulating layer 119, is rectangle or annular, from the upper surface of the second superlattice n-type layer 116 and to hanging down
Directly in the direction of the second superlattice n-type layer 116 downward through to the 11st superlattices intrinsic layer 113 lower surface,
The 7th P+ conductive layer 118 is arranged in the tenth channel insulating layer 119；
26th ohmic contact layer 120, be arranged above first ferroelectric thin film layer 117 and with first ferroelectricity
Film layer 117 contacts,
27th ohmic contact layer 121 is arranged above the 7th P+ conductive layer 118 and conductive with the 7th P+
Layer 118 contacts；
23rd dielectric protection layer 123, setting connect in the 26th ohmic contact layer 120 and the 27th ohm
Between contact layer 121；
121 outside of the 27th ohmic contact layer is arranged in 24th dielectric protection layer 124.
Adulterating P channel n-i-p-i superlattices field-effect ferroelectric transistor, (P channel n-i-p-i superlattices field-effect ferroelectricity is brilliant
Body pipe) by ferroelectric thin film layer, the P-type layer of the intrinsic layer (the 11st superlattices intrinsic layer) of doped superlattice, doped superlattice is (super
Lattice low-resistance P-type layer), superlattices intrinsic layer (the 12nd superlattices intrinsic layer), N-type layer (the second superlattices of doped superlattice
N-type layer), the composition such as the 7th P+ conductive layer.For the performance requirement for reaching integrated circuit, the superlattice film of different-thickness can be designed
Layer.It not only can be used homogeneity superlattice layer, such as silicon, gallium nitride (GaN) , Arsenic gallium (GaAs), can also be used heterogeneous superlattice layer,
Ru Dan Arsenic gallium Ga (x) As (1-x) N, nitrogen calorize gallium Ga (x) Al (1-x) N, nitrogen gallium phosphide Ga (x) Ps (1-x) N etc., using not
Special Quantum Well is formed with forbidden bandwidth to promote device performance.P+ conductive layer, ohm electricity are formed with low energy ion beam implantation technology
Pole is formed with plasma sputtering technology, but plasma sputtering material by according to superlattice semiconductor layer material depending on, such as
To gallium nitride material, it is generally available titanium-aluminium alloy, etc..Gate insulating layer can use silicon nitride etc..It needs to use insulating layer between device
Isolation.Channel insulating layer can then be chemically-mechanicapolish polished with special channel ion etching technics and plus insulating materials ion sputtering
It is formed.Channel insulating layer can also be used ion implanting and form PN junction channel insulating layer, if it is desired, can be in same superlattices collection
Optimize at using a variety of isolation methods to have reached maximum performance on circuit.
Equally, it can also design and manufacture doping N channel n-i-p-i superlattices field-effect ferroelectric transistor.Its principle is very
It is similar, only when adding equidirectional voltage on ferroelectric thin film, when such as adding negative voltage, adulterate P channel n-i-p-i superlattices field
Effect ferroelectric transistor will be in the open state, and adulterating N channel n-i-p-i superlattices field-effect ferroelectric transistor will be in pass
Make and break state；
As shown in figure 16, wherein N channel n-i-p-i superlattices field-effect ferroelectric transistor includes:
13rd superlattices intrinsic layer 125 is set to 2 top of transition zone；
Superlattices low-resistance N-type layer 126 is arranged above the 13rd superlattices intrinsic layer 125；
The top of the superlattices low-resistance N-type layer 126 is arranged in 14th superlattices intrinsic layer 127；
5th superlattice p-type layer 128 is arranged above the 14th superlattices intrinsic layer 127；
The top of the 5th superlattice p-type layer 128 is arranged in second ferroelectric thin film layer 129；
7th N+ conductive layer 130 five surpasses from the upper surface of the 5th superlattice p-type layer 128 and to perpendicular to described
Lower surface of the direction of lattice P-type layer 128 downward through extremely the 13rd superlattices intrinsic layer 125；
11st channel insulating layer 131, from the upper surface of the 5th superlattice p-type layer 128 and to perpendicular to described
Lower surface of the direction of five superlattice p-type layers 128 downward through extremely the 13rd superlattices intrinsic layer 125, the 7th N+
Conductive layer 130 is arranged in the 11st channel insulating layer 131；
28th ohmic contact layer 132, be arranged above second ferroelectric thin film layer 129 and with second ferroelectricity
Film layer 129 contacts,
29th ohmic contact layer 133 is arranged above the 7th N+ conductive layer 130 and conductive with the 7th N+
Layer 130 contacts；
25th dielectric protection layer 134, setting connect in the 28th ohmic contact layer 132 and the 29th ohm
Between contact layer 133；
133 outside of the 29th ohmic contact layer is arranged in 26th dielectric protection layer 135.
Above-mentioned first channel insulating layer to the 11st channel insulating layer is autonomous cooling insulating layer.
As shown in figure 17, independently cooling insulating layer 202 includes:
Temperature reducing substance accommodating cavity 201 is arranged in the autonomous cooling insulating layer 202,
First capillary pipeline 203 is arranged in the autonomous cooling insulating layer 202, and one end and the temperature reducing substance accommodate
Chamber 201 connects, and the other end is connected to the upper surface of the autonomous cooling insulating layer 202；
In the dielectric protection layer 204 above independently cooling insulating layer 202, it is also equipped with the second capillary pipeline 205, this
Two capillary pipelines 205 are connected to the first capillary pipeline 203 of autonomous cooling insulating layer 202 and second capillary pipeline 205 leans on
The upper surface portion of the nearly dielectric protection layer 204 is set as bending, make the second capillary pipeline 205 upper surface outlet with
Upper surface (can be 15 degree) at an angle, make cooling material in undergoing phase transition of heating in this way, from the second capillary pipeline
205 outlets flow on ohmic contact layer after coming out.To cool down.
By the way that autonomous cooling insulating layer is arranged, adstante febre when burning after component short circuit is autonomous to cool down in insulating layer
Temperature reducing substance it is heated phase change occurs, to absorb heat, the volume of temperature reducing substance when phase change further occurs
Increase, sprays, be sprayed on the component burnt from capillary pipeline, and then further cool down to the component burnt；In this way may be used
To prevent its destruction to component intact nearby, to reduce loss.
Above-mentioned first channel insulating layer to the 11st channel insulating layer is isolation insulating layer:
As shown in figure 18, the isolation insulating layer 211 is internally provided with cavity 212；Cooling is provided in the cavity 212
Substance.
Completely cut off insulating layer by setting, adstante febre when burning after component short circuit completely cuts off the outer layer insulation of insulating layer
Layer releases temperature reducing substance after burning, temperature reducing substance is heated to occur phase change, to absorb heat, phase further occurs
The volume of temperature reducing substance increases when variation, so that the component burnt be made to come with external intact component isolation；In this way
Its destruction to component intact nearby can be prevented, to reduce loss.
As shown in figure 18, in one embodiment, at least one connector 213, the company are provided in the cavity 212
213 one end of junctor is connect with 212 left side wall of cavity, and the other end is connect with 212 right side wall of cavity；In the connector 213
Portion's diameter is less than both ends diameter.
By the way that connector is arranged, the space in cavity is supported, keeps cavity structure stronger；It is intermediate straight by being arranged to
Diameter is less than both ends, is to make in temperature reducing substance expanded by heating, and the fracture position of connector is located at intermediate position, places when expanding pair
The intact component in side is pullled, to avoid component damage caused by pullling.
Further, the doping fluorescent substance in temperature reducing substance can be using inspection insulating layer when circuit burnout
The image of fluorescent material is to the position that faster decision circuitry is damaged and degree.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (13)
1. a kind of multi-functional superlattices super large-scale integration of novel multi-vitamin characterized by comprising
Substrate；
Transition zone, setting is on the substrate；
Component layer is arranged above the excessive layer, and component layer is using based on superlattices integrated circuit two-dimensional electron gas
The device that designs with the property of two-dimensional hole gas constructs high-performance superlattices integrated circuit.
2. the multi-functional superlattices super large-scale integration of novel multi-vitamin as described in claim 1, which is characterized in that the lining
Bottom uses silicon, germanium or compound semiconductor.
3. the multi-functional superlattices super large-scale integration of novel multi-vitamin as described in claim 1, which is characterized in that the mistake
It is one of using silica, silicon nitride and compound semiconductor layer to cross layer.
4. the multi-functional superlattices super large-scale integration of novel multi-vitamin as described in claim 1, which is characterized in that the base
In the property of superlattices integrated circuit two-dimensional electron gas and two-dimensional hole gas design device include p-type superlattices field-effect
Transistor, N-type superlattices field effect transistor, NPN type superlattices bipolar junction transistor, positive-negative-positive superlattices bipolar junction transistor,
Superlattices flash memories, superlattices capacitor and variodenser, superlattices resistance and rheostat and superlattices inductance and varinodr its
In one or more combinations.
5. the multi-functional superlattices super large-scale integration of novel multi-vitamin as described in claim 1, which is characterized in that substrate bottom
Portion is evenly distributed with multiple through-holes.
6. the multi-functional superlattices super large-scale integration of novel multi-vitamin as claimed in claim 4, which is characterized in that the N
Type superlattices field effect transistor includes:
First superlattices intrinsic layer is set to above the transition zone；
Superlattices N-type layer is arranged above the first superlattices intrinsic layer；
The top of the superlattices N-type layer is arranged in second superlattices intrinsic layer；
First superlattice p-type layer is arranged above the second superlattices intrinsic layer；
The top of the first superlattice p-type layer is arranged in first grid insulating layer；
First N+ conductive layer, from the upper surface of the first superlattice p-type layer and to perpendicular to the first superlattice p-type layer
Lower surface of the direction downward through extremely the first superlattices intrinsic layer；
First channel insulating layer is shape, such as rectangle needed for device isolation, annular, etc. from the first superlattice p-type layer
Upper surface and to the direction perpendicular to the first superlattice p-type layer downward through to the first superlattices intrinsic layer following table
Face, the first N+ conductive layer are arranged in the first channel insulating layer；
First ohmic contact layer, be arranged above the first N+ conductive layer and with the first N+ conductive layer contact；
Second ohmic contact layer is arranged above the first grid insulating layer and contacts with the first grid insulating layer,
First dielectric protection layer is arranged between first ohmic contact layer and the second ohmic contact layer；
Second dielectric protection layer is arranged on the outside of first ohmic contact layer.
7. the multi-functional superlattices super large-scale integration of novel multi-vitamin as claimed in claim 4, which is characterized in that the P
Type superlattices field effect transistor includes:
Third superlattices intrinsic layer is set to above the transition zone；
Superlattice P-type layer is arranged above the third superlattices intrinsic layer；
The superlattice P-type layer top is arranged in 4th superlattices intrinsic layer；
First superlattice n-type layer is arranged above the 4th superlattices intrinsic layer；
The top of the first superlattice n-type layer is arranged in first grid insulating layer；
First P+ conductive layer, from the upper surface of the first superlattice n-type layer and to perpendicular to the first superlattice n-type layer
Lower surface of the direction downward through the extremely third superlattices intrinsic layer；
Second channel insulating layer, from the upper surface of the first superlattice n-type layer and to perpendicular to the first superlattice n-type layer
Direction downward through to the lower surface of the third superlattices intrinsic layer, the first P+ conductive layer is arranged in second ditch
In road insulating layer；
Third ohmic contact layer, be arranged above the first P+ conductive layer and with the first P+ conductive layer contact；
4th ohmic contact layer is arranged above the second grid insulating layer and contacts with the second grid insulating layer,
Third dielectric protection layer is arranged between the third ohmic contact layer and the 4th ohmic contact layer；
4th dielectric protection layer is arranged on the outside of the third ohmic contact layer.
8. the multi-functional superlattices super large-scale integration of novel multi-vitamin as claimed in claim 4, which is characterized in that described
Positive-negative-positive superlattices bipolar transistor is divided into superlattice planes type P-N-P bipolar transistor and the bipolar crystalline substance of superlattices vertical-type P-N-P
Body pipe；
Wherein, superlattices vertical-type P-N-P bipolar transistor includes:
Superlattices collector P-type layer is arranged above the transition zone；
Superlattices base stage N-type layer is arranged above the superlattices collector P-type layer；
Superlattices emitter P-type layer is arranged above the superlattices base stage N-type layer；
2nd P+ conductive layer and the 2nd N+ conductive layer, from the upper surface of the superlattices emitter P-type layer and to perpendicular to described
Lower surface of the direction of superlattices emitter P-type layer downward through the extremely superlattices collector P-type layer；
Third channel insulating layer, from the upper surface of the superlattices emitter P-type layer and to perpendicular to the superlattices emitter P
Downward through to the lower surface of the superlattices collector P-type layer, the 2nd P+ conductive layer and the 2nd N+ are led in the direction of type layer
Electric layer is arranged in the third channel insulating layer；
5th ohmic contact layer, be arranged above the 2nd P+ conductive layer and with the 2nd P+ conductive layer contact；
6th ohmic contact layer, be arranged above the 2nd N+ conductive layer and with the 2nd N+ conductive layer contact；
7th ohmic contact layer is arranged above the superlattices emitter P-type layer and connects with the superlattices emitter P-type layer
Touching,
5th dielectric protection layer is arranged in the 7th ohmic contact layer and the 5th ohmic contact layer, the 7th Ohmic contact
Between layer and the 6th ohmic contact layer；
The 5th ohmic contact layer, the 6th ohmic contact layer outside is arranged in 6th dielectric protection layer.
7th dielectric protection layer, setting is in the superlattices emitter P-type layer and the 2nd N+ conductive layer, superlattices hair
Between emitter-base bandgap grading P-type layer and the 2nd P+ conductive layer；
Wherein, superlattice planes type P-N-P bipolar transistor includes:
Superlattice planes type P-N-P bipolar transistor includes:
Superlattices emitter p type island region is cylindrical type, is arranged above the transition zone；
Superlattices base stage N-type region 46 is arranged above the transition zone for annular and is set in the superlattices emitter p-type
On the outside of area；
Superlattices collector p type island region is arranged above the transition zone for annular and is set in setting in the superlattices base stage
46 outside of N-type region；
4th channel insulating layer is set in and is arranged on the outside of superlattices base stage p type island region for annular, also, the 4th ditch
Road insulating layer is arranged above the transition zone or is arranged above the transition zone and is embedded in institute after the transition zone
It states in substrate；
8th ohmic contact layer be circle, be arranged above superlattices emitter p type island region and with the superlattices emitter P
The contact of type area；
9th ohmic contact layer be annular, be arranged above the superlattices base stage N-type region 46 and with the superlattices base stage N-type
Area 46 contacts；
Tenth ohmic contact layer be annular, be arranged above superlattices collector p type island region and with the superlattices collector P
The contact of type area；
8th dielectric protection layer is arranged between the 8th ohmic contact layer and the 9th ohmic contact layer for annular；
9th dielectric protection layer is arranged between the 9th ohmic contact layer and the tenth ohmic contact layer for annular；
The outside of the tenth ohmic contact layer is arranged in for annular in tenth dielectric protection layer.
9. the multi-functional superlattices super large-scale integration of novel multi-vitamin as claimed in claim 4, which is characterized in that described
NPN type superlattices field effect transistor is divided into superlattices vertical-type N-P-N bipolar transistor and superlattice planes type N-P-N is bipolar
Transistor；
Wherein, superlattices vertical-type N-P-N bipolar transistor includes:
Superlattices collector N-type layer is arranged above the transition zone；
Superlattices base stage P-type layer is arranged above the superlattices collector N-type layer；
Superlattices emitter N-type layer is arranged above the superlattices base stage P-type layer；
3rd P+ conductive layer and the 3rd N+ conductive layer are from the upper surface of the superlattices emitter N-type layer and to perpendicular to described super
Lower surface of the direction of lattice emission pole N-type layer downward through the extremely superlattices collector N-type layer；
5th channel insulating layer, from the upper surface of the superlattices emitter N-type layer and to perpendicular to the superlattices emitter N
Downward through to the lower surface of the superlattices collector N-type layer, the 3rd P+ conductive layer and the 3rd N+ are led in the direction of type layer
Electric layer is arranged in the 5th channel insulating layer；
11st ohmic contact layer, be arranged above the 3rd P+ conductive layer and with the 3rd P+ conductive layer contact；
12nd ohmic contact layer, be arranged above the 3rd N+ conductive layer and with the 3rd N+ conductive layer contact；
13rd ohmic contact layer, be arranged above the superlattices emitter N-type layer and with the superlattices emitter N-type layer
Contact,
11st dielectric protection layer is arranged in the 13rd ohmic contact layer and the 11st ohmic contact layer, the described 13rd
Between ohmic contact layer and the 12nd ohmic contact layer；
The 11st ohmic contact layer, the 12nd ohmic contact layer outside is arranged in 12nd dielectric protection layer.
13rd dielectric protection layer is arranged in the superlattices emitter N-type layer and the 3rd N+ conductive layer, the superlattices
Between emitter N-type layer and the 3rd P+ conductive layer；
Wherein, superlattice planes type N-P-N bipolar transistor includes:
Superlattices emitter N-type region is cylindrical type, is arranged above the transition zone；
Superlattices base stage p type island region is arranged above the transition zone for annular and is set in the superlattices emitter N-type region
Outside；
Superlattices collector N-type region is arranged above the transition zone for annular and is set in superlattices base stage p type island region
Outside；
6th channel insulating layer is set in and is arranged on the outside of the superlattices collector N-type region for annular, also, the described 6th
Channel insulating layer is arranged above the transition zone or is arranged above the transition zone and is embedded in after the transition zone
In the substrate；
14th ohmic contact layer is circle, is arranged above the superlattices emitter N-type region and emits with the superlattices
The contact of pole N-type region；
15th ohmic contact layer be annular, be arranged above superlattices base stage p type island region and with the superlattices base stage p-type
Area's contact；
16th ohmic contact layer be annular, be arranged above the superlattices collector N-type region and with the superlattices current collection
The contact of pole N-type region；
14th dielectric protection layer is arranged between the 14th ohmic contact layer and the 15th ohmic contact layer for annular；
15th dielectric protection layer is arranged between the 15th ohmic contact layer and the 16th ohmic contact layer for annular；
The outside of the 16th ohmic contact layer is arranged in for annular in 16th dielectric protection layer.
10. the multi-functional superlattices super large-scale integration of novel multi-vitamin as claimed in claim 4, which is characterized in that described
Superlattices capacitor includes: with variodenser
5th superlattices intrinsic layer is set to above the transition zone；
Second superlattice p-type layer is arranged above the 5th superlattices intrinsic layer；
The top of the second superlattice p-type layer is arranged in 6th superlattices intrinsic layer；
First superlattices low-resistance N-type layer is arranged above the 6th superlattices intrinsic layer；
4th P+ conductive layer and the 4th N+ conductive layer, from the upper surface of the first superlattices low-resistance N-type layer and to perpendicular to institute
State lower surface of the direction downward through extremely the 5th superlattices intrinsic layer of the first superlattices low-resistance N-type layer；
7th channel insulating layer, from the upper surface of the first superlattices low-resistance N-type layer and to perpendicular to first superlattices
The direction of low-resistance N-type layer is downward through to the lower surface of the 5th superlattices intrinsic layer, the 4th P+ conductive layer and the 4th N
+ conductive layer is arranged in the 7th channel insulating layer；
17th ohmic contact layer, be arranged above the first superlattices low-resistance N-type layer and with the first superlattices low-resistance N
The contact of type layer；
18th ohmic contact layer, be arranged above the 4th N+ conductive layer and with the 4th N+ conductive layer contact；
19th ohmic contact layer, be arranged above the 4th P+ conductive layer and with the 4th P+ conductive layer contact；
17th dielectric protection layer is arranged in the 17th ohmic contact layer and the 18th ohmic contact layer, the 17th ohm
Between contact layer and the 19th ohmic contact layer；
The 18th ohmic contact layer, the 19th ohmic contact layer outside is arranged in 18th dielectric protection layer.
11. the multi-functional superlattices super large-scale integration of novel multi-vitamin as claimed in claim 4, which is characterized in that described
Superlattices resistance includes: with rheostat
7th superlattices intrinsic layer is set to above the transition zone；
Third superlattice p-type layer is arranged above the 7th superlattices intrinsic layer；
The top of the third superlattice p-type layer is arranged in 8th superlattices intrinsic layer；
Second superlattices low-resistance N-type layer is arranged above the 8th superlattices intrinsic layer；
5th P+ conductive layer and the 5th N+ conductive layer are from the upper surface of the second superlattices low-resistance N-type layer and to perpendicular to described
Lower surface of the direction of second superlattices low-resistance N-type layer downward through extremely the 7th superlattices intrinsic layer；
8th channel insulating layer, from the upper surface of the second superlattices low-resistance N-type layer and to perpendicular to second superlattices
The direction of low-resistance N-type layer is downward through to the lower surface of the 7th superlattices intrinsic layer, the 5th P+ conductive layer and the 5th N
+ conductive layer is arranged in the 8th channel insulating layer；
One the 20th ohmic contact layer, the 21st ohmic contact layer and the 22nd ohmic contact layer are one
Group shares two groups；
20th ohmic contact layer, be arranged above the second superlattices low-resistance N-type layer and with the second superlattices low-resistance N
The contact of type layer；
21st ohmic contact layer, be arranged above the 5th N+ conductive layer and with the 5th N+ conductive layer contact；
22nd ohmic contact layer, be arranged above the 5th P+ conductive layer and with the 5th P+ conductive layer contact；
19th dielectric protection layer is arranged in the 20th ohmic contact layer and the 21st ohmic contact layer, the 20th Europe
Between nurse contact layer and the 22nd ohmic contact layer；
The 21st ohmic contact layer, the 22nd ohmic contact layer outside is arranged in 20th dielectric protection layer.
12. the multi-functional superlattices super large-scale integration of novel multi-vitamin as claimed in claim 4, which is characterized in that described
Superlattices inductance includes: with varinodr
9th superlattices intrinsic layer is set to above the transition zone；
4th superlattice p-type layer is arranged above the 9th superlattices intrinsic layer；
The top of the 4th superlattice p-type layer is arranged in tenth superlattices intrinsic layer；
Third superlattices low-resistance N-type layer is arranged above the tenth superlattices intrinsic layer；
6th P+ conductive layer and the 6th N+ conductive layer are from the upper surface of the third superlattices low-resistance N-type layer and to perpendicular to described
Lower surface of the direction of third superlattices low-resistance N-type layer downward through extremely the 9th superlattices intrinsic layer；
9th channel insulating layer, from the upper surface of the third superlattices low-resistance N-type layer and to perpendicular to the third superlattices
The direction of low-resistance N-type layer is downward through to the lower surface of the 9th superlattices intrinsic layer, the 6th P+ conductive layer and the 6th N
+ conductive layer is arranged in the 9th channel insulating layer；
One the 23rd ohmic contact layer, the 24th ohmic contact layer and the 25th ohmic contact layer are one
Group shares two groups；
23rd ohmic contact layer is arranged above the third superlattices low-resistance N-type layer and super brilliant with the third
The contact of lattice low-resistance N-type layer；
24th ohmic contact layer is arranged above the 6th N+ conductive layer and connects with the 6th N+ conductive layer
Touching；
25th ohmic contact layer is arranged above the 6th P+ conductive layer and connects with the 6th P+ conductive layer
Touching；
21st dielectric protection layer is arranged in the 23rd ohmic contact layer and the 24th ohmic contact layer, second
Between 13 ohmic contact layers and the 24th ohmic contact layer；
The 24th ohmic contact layer, the 25th ohmic contact layer outside is arranged in 22nd dielectric protection layer.
13. the multi-functional superlattices super large-scale integration of novel multi-vitamin as claimed in claim 4, which is characterized in that described
Superlattices flash memories include: including by doping P channel n-i-p-i superlattices field-effect ferroelectric transistor or doping N channel
N-i-p-i superlattices field-effect ferroelectric transistor；
Wherein, P channel n-i-p-i superlattices field-effect ferroelectric transistor includes:
11st superlattices intrinsic layer is set to above the transition zone；
Superlattices low-resistance P-type layer is arranged above the 11st superlattices intrinsic layer；
The top of the superlattices low-resistance P-type layer is arranged in 12nd superlattices intrinsic layer；
Second superlattice n-type layer is arranged above the 12nd superlattices intrinsic layer；
The top of the second superlattice n-type layer is arranged in first ferroelectric thin film layer；
7th P+ conductive layer, from the upper surface of the second superlattice n-type layer and to perpendicular to the second superlattice n-type layer
Lower surface of the direction downward through extremely the 11st superlattices intrinsic layer；
Tenth channel insulating layer, from the upper surface of the second superlattice n-type layer and to perpendicular to the second superlattice n-type layer
Direction downward through to the lower surface of the 11st superlattices intrinsic layer, the 7th P+ conductive layer is arranged the described tenth
In channel insulating layer；
26th ohmic contact layer is arranged above first ferroelectric thin film layer and connects with first ferroelectric thin film layer
Touching,
27th ohmic contact layer, be arranged above the 7th P+ conductive layer and with the 7th P+ conductive layer contact；
23rd dielectric protection layer is arranged between the 26th ohmic contact layer and the 27th ohmic contact layer；
24th dielectric protection layer is arranged on the outside of the 27th ohmic contact layer；
Wherein, N channel n-i-p-i superlattices field-effect ferroelectric transistor includes:
13rd superlattices intrinsic layer is set to above the transition zone；
Superlattices low-resistance N-type layer is arranged above the 13rd superlattices intrinsic layer；
The top of the superlattices low-resistance N-type layer is arranged in 14th superlattices intrinsic layer；
5th superlattice p-type layer is arranged above the 14th superlattices intrinsic layer；
The top of the 5th superlattice p-type layer is arranged in second ferroelectric thin film layer；
7th N+ conductive layer, from the upper surface of the 5th superlattice p-type layer and to perpendicular to the 5th superlattice p-type layer
Lower surface of the direction downward through extremely the 13rd superlattices intrinsic layer；
11st channel insulating layer, from the upper surface of the 5th superlattice p-type layer and to perpendicular to the 5th superlattice p-type
The direction of layer is downward through to the lower surface of the 13rd superlattices intrinsic layer, and the 7th N+ conductive layer setting is described the
In 11 channel insulating layers；
28th ohmic contact layer is arranged above second ferroelectric thin film layer and connects with second ferroelectric thin film layer
Touching,
29th ohmic contact layer, be arranged above the 7th N+ conductive layer and with the 7th N+ conductive layer contact；
25th dielectric protection layer is arranged between the 28th ohmic contact layer and the 29th ohmic contact layer；
26th dielectric protection layer is arranged on the outside of the 29th ohmic contact layer.
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| CN202111131224.2A CN113871461B (en) | 2019-05-06 | 2019-05-06 | Superlattice very large scale integrated circuit |
| CN201910372092.9A CN110085665B (en) | 2019-05-06 | 2019-05-06 | Superlattice very large scale integrated circuit |
| CN202111131217.2A CN113871459B (en) | 2019-05-06 | 2019-05-06 | Superlattice very large scale integrated circuit |
| CN202111131222.3A CN113871460B (en) | 2019-05-06 | 2019-05-06 | Superlattice very large scale integrated circuit |
| CN202111131216.8A CN113871458B (en) | 2019-05-06 | 2019-05-06 | Superlattice very large scale integrated circuit |
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| CN202111131217.2A Division CN113871459B (en) | 2019-05-06 | 2019-05-06 | Superlattice very large scale integrated circuit |
| CN202111131216.8A Division CN113871458B (en) | 2019-05-06 | 2019-05-06 | Superlattice very large scale integrated circuit |
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| CN202111131222.3A Active CN113871460B (en) | 2019-05-06 | 2019-05-06 | Superlattice very large scale integrated circuit |
| CN202111131224.2A Active CN113871461B (en) | 2019-05-06 | 2019-05-06 | Superlattice very large scale integrated circuit |
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| EP0333997A2 (en) * | 1988-03-22 | 1989-09-27 | International Business Machines Corporation | Bipolar transistor |
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| CN101288174A (en) * | 2005-07-15 | 2008-10-15 | 梅尔斯科技公司 | Semiconductor device including a strained superlattice and overlying stress layer and related methods |
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| TW201810440A (en) * | 2016-07-01 | 2018-03-16 | 英特爾公司 | Graded channels for high frequency III-N transistors |
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| CN113871458B (en) | 2023-09-12 |
| CN113871461B (en) | 2023-09-12 |
| CN113871457A (en) | 2021-12-31 |
| CN113871459A (en) | 2021-12-31 |
| CN113871461A (en) | 2021-12-31 |
| CN113871460A (en) | 2021-12-31 |
| CN113871460B (en) | 2023-09-12 |
| CN113871459B (en) | 2023-09-12 |
| CN110085665B (en) | 2021-10-22 |
| CN113871458A (en) | 2021-12-31 |
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