CN101288174A - Semiconductor device including a strained superlattice and overlying stress layer and related methods - Google Patents

Abstract

A semiconductor device may include a strained superlattice layer (325) including a plurality of stacked groups of layers, and a stress layer above the strained superlattice layer. Each group of layers of the strained superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Description

Comprise semiconductor device of strained super lattice and overlying stress layer and associated method

Technical field

[0001] the present invention relates to semi-conductive field, relate in particular to based on energy band engineering and associated method and have enhanced propertied semiconductor.

Background technology

[0002] structure and technology have been proposed to strengthen the performance of semiconductor device, for example by strengthening the mobility of electric charge carrier.For example, the strained material layer of No. 2003/0057416, people's such as Currie U.S. Patent application open silicon, SiGe and relaxed silicon, and also comprise otherwise the free from admixture district that will cause performance degradation.The biaxial strain that produces in top silicon layer change carrier mobility allows more speed and/or low power devices more.People's such as Fitzgerald the U.S. Patent application of delivering discloses a kind of same CMOS inverter based on similar strained silicon technology for No. 2003/0034529.

[0003] United States Patent (USP) 6,472 of Takagi discloses a kind of semiconductor device 685B2 number, comprises the silicon and the carbon-coating that are clipped between the silicon layer, makes the conduction band of second silicon layer and valence band receive elongation strain.The electronics that has less effective mass and caused by the electric field that is applied to gate electrode is limited in second silicon layer, thereby asserts that n passage MOSFET is to have higher mobility.

[0004] people's such as Ishibashi United States Patent (USP) discloses a kind of superlattice for 4,937, No. 204, wherein is less than eight individual layers, and comprises a plurality of layers of alternate epitaxial growth of fragment or Binary compound semiconductor layer.The direction of principal current is perpendicular to the layer of superlattice.

[0005] people's such as Wang United States Patent (USP) discloses a kind of Si-Ge short period superlattice that is diffused in the high mobility that the alloy in the superlattice realizes by minimizing that has for 5,357, No. 119.According to as the method, the United States Patent (USP) 5 of Candelaria, a kind of enhancing mobility MOSFET that comprises channel layer is disclosed for 683, No. 934, channel layer comprise silicon with channel layer is placed percentage under the tensile stress alternatively be present in the alloy of second metal of silicon crystal lattice.

[0006] United States Patent (USP) of Tsu discloses a kind of quantum well structure 5,216, No. 262, comprises two barrier regions and is clipped in thin epitaxially grown semiconductor layer between the potential barrier.Each barrier region comprises SiO ₂The alternating layer of/Si, thickness are usually in the scope of two to six individual layers.Thicker silicon partly is clipped between the potential barrier.

[0007] be equally Tsu's and on September 6th, 2000 by Applied Physics and material science; Handle online deliver, title discloses a kind of silicon and oxygen for the paper of " Phenomena in siliconnanostructure devices (phenomenon in the silicon nanostructure device) " the semiconductor atom superlattice (SAS) of pp.391-402.Be disclosed in Si/O superlattice useful in silicon quantum and the luminescent device.Especially, structure and test green electroluminescent diode structure.Electric current in the diode structure is vertical, just, and perpendicular to the layer of SAS.Disclosed SAS can comprise by the adsorbing species semiconductor layer of oxygen atom and CO molecular separation for example.Silicon growth outside the oxygen individual layer of absorption is described as having the epitaxial growth of relative fabricating low-defect-density.A SAS structure comprises the silicon part that 1.1nm is thick, promptly about eight silicon atom layers, and another structure has the twice of this silicon thickness.At physical comment bulletin, Vol.89, people's such as that No.7 delivered in (on August 12nd, 2002), Luo title further discuss the luminous SAS structure of Tsu for the paper of " ChemicalDesign of Direct-Gap Light-Emitting Silicon (chemical design of the luminous silicon of direct band gap) ".

[0008] the open International Application No. WO 02/103 of Wang, Tsu and Lofgren, 767A1 discloses a kind of potential barrier of being made by thin silicon and oxygen, carbon, nitrogen, phosphorus, antimony, arsenic or hydrogen and makes up piece, crosses the electric current of lattice more than four orders of magnitude thereby reduce vertical current.Insulating barrier/barrier layer allows the epitaxial silicon of low defective to nestle up insulating barrier and deposits.

[0009] people's such as Mears open UK Patent Application 2,347,520 is open, and the principle of aperiodic photonic band-gap (APBG) structure goes for the electronic band gap engineering.Especially, this application openly can the designing material parameter, for example new material aperiodic that can have expectation band structure feature with generation with the position of minimum value, effective mass etc.Other parameters, for example conductivity, thermal conductivity and dielectric constant or magnetic permeability are disclosed as also and can be designed in the material.

[0010] although makes great efforts in a large number still to exist for bigger improved demand to increase the mobility of electric charge carrier in the semiconductor device about material engineering.Bigger mobility can increase device speed and/or reduce device power consumption.Have bigger mobility, also can keep device performance, although to moving continuously than gadget and new unit structure.

Summary of the invention

[0011] considers aforementioned background, therefore, the object of the present invention is to provide a kind of operating characteristic of enhancing semiconductor device that has.

[0012] should be provided by a kind of semiconductor device with other purposes, feature and advantage according to of the present invention, it can comprise the strained superlattice layer that comprises a plurality of stacked groups of layers, and is positioned at the stressor layers above the strained superlattice layer.More particularly, each of strained superlattice layer layer group can comprise a plurality of stacked base semiconductor monolayer that limits base semiconductor portion, and intracell at least one monolayer that is limited in the adjacent foundation semiconductor portions.

[0013] more particularly, semiconductor device can also comprise adjacent with strained superlattice layer, be positioned at the Semiconductor substrate on the relative side with stressor layers.In addition, semiconductor device also can comprise and makes electric charge carrier transport the zone by strained superlattice layer on the parallel direction with respect to stacked groups of layers.

[0014] strained superlattice layer can have compression and/or elongation strain.Strained superlattice layer also can have common energy band structure therein.As an example, each base semiconductor portion can comprise and is selected from IV family semiconductor, the semi-conductive base semiconductor of III-V family semiconductor and II-VI family.More particularly, each base semiconductor portion can comprise silicon.And each monolayer can comprise the non-semiconductor that is selected from oxygen, nitrogen, fluorine and carbon-oxygen.And stressor layers can comprise silicon and nitrogen.

[0015] the adjacent foundation semiconductor portions of strained superlattice layer can chemically combine.And each monolayer can be single single monolayer thick, and each base semiconductor portion can be less than eight single monolayer thick.Strained superlattice layer also can have DIRECT ENERGY band gap basically.Strained superlattice layer also can comprise the base semiconductor cap rock that is positioned at above top group.In some embodiments, all base semiconductor portion can be the single monolayer thick of similar number.As selection, at least some of base semiconductor portion can be the single monolayer thick of different numbers.

[0016] method of the present invention aspect relates to the manufacturing semiconductor device.This method can comprise that formation comprises the superlattice layer of a plurality of stacked groups of layers, and forms stressor layers to cause strain therein on superlattice layer.In addition, each of superlattice layer layer group can comprise a plurality of stacked base semiconductor monolayer that limits base semiconductor portion, and intracell at least one monolayer that is limited in the adjacent foundation semiconductor portions.

Description of drawings

[0017] Fig. 1 is according to the present invention includes stressor layers and the schematic cross-sectional view that is positioned at the semiconductor device of the strained super lattice above the stressor layers.

[0018] Fig. 2 is the very amplification schematic cross-sectional view of superlattice shown in Fig. 1.

[0019] Fig. 3 is the perspective schematic atomic diagram of the part of superlattice shown in Fig. 1.

[0020] Fig. 4 is the very amplification schematic cross-sectional view of the another embodiment of the superlattice that can use in the device of Fig. 1.

[0021] Fig. 5 A is for body silicon of the prior art, and for the 4/1Si/O superlattice shown in Fig. 1-3, the figure of the band structure of calculating from gamma point (G).

[0022] Fig. 5 B is for body silicon of the prior art, and for the 4/1Si/O superlattice shown in Fig. 1-3, the figure of the band structure of calculating from the Z point.

[0023] Fig. 5 C is for body silicon of the prior art, and for the 5/1/3/1Si/O superlattice shown in Fig. 4, the figure of the band structure of calculating from gamma and Z point.

[0024] Fig. 6 and 7 is schematic cross-sectional view of alternative embodiment of the semiconductor device of Fig. 1.

[0025] Fig. 8 is the schematic cross-sectional view that comprises the another kind of semiconductor device embodiment of superlattice according to the present invention between the stressed zone at a pair of interval.

[0026] Fig. 9 is according to the schematic cross-sectional view that the present invention includes superlattice and be positioned at another semiconductor device embodiment of the stressor layers above the superlattice.

[0027] Figure 10 is according to the schematic cross-sectional view that the present invention includes the MOSFET of monolayer.

[0028] Figure 11 is the emulation chart of the degree of depth of the density contrast monolayer at the interface of Figure 10.

Embodiment

[0029] describes the present invention hereinafter more fully referring now to appended drawings, wherein show the preferred embodiments of the invention.But the present invention can many different forms implement, and should not be interpreted as being confined to embodiments set forth here.On the contrary, provide these embodiments, make the disclosure content, and scope of the present invention is fully conveyed to those skilled in the art detailed and complete.Same numeral spreads all over and refers to same element in full, and uses to add and cast aside and the like that repeatedly adds in the left-falling stroke symbol indication alternative embodiment.

[0030] the present invention relates to control the character of semi-conducting material, so that realize the raising performance in the semiconductor device at atom or molecule rank.And, the present invention relates to identification, generation and the use of the improvement material that in the conductive path of semiconductor device, uses.

[0031] applicant theorizes, and does not wish to be confined to this theory, reduces the effective mass of electric charge carrier as certain superlattice described herein, and this causes higher charge carrier mobility thus.Effective mass uses the various definition in the document to describe.As the improved measurement of effective mass, the applicant uses " conductivity-reciprocal effective mass tensor ", M _e ^-1And M _h ^-1, for electronics and hole, be defined as respectively:

For electronics:

$M_{e,\mathrm{ij}}^{-1}(E_F,T)=\frac{\underset{E>E_F}{\mathrm{\Σ}}\underset{B.Z.}{\∫}{\left({\▿}_{k}E(k,n)\right)}_i{\left({\▿}_{k}E(k,n)\right)}_j\frac{\∂f(E(k,n),E_F,T)}{\∂E}{d}^{3}k}{\underset{E>E_F}{\mathrm{\Σ}}\underset{B.Z.}{\∫}f(E(k,n),E_F,T)d^{3}k}$

And for the hole:

$M_{h,\mathrm{ij}}^{-1}(E_F,T)=\frac{-\underset{E<E_F}{\mathrm{\&Sigma;}}\underset{B.Z.}{\&Integral;}{\left({\&dtri;}_{k}E(k,n)\right)}_i{\left({\&dtri;}_{k}E(k,n)\right)}_j\frac{\&PartialD;f(E(k,n),E_F,T)}{\&PartialD;E}{d}^{3}k}{\underset{E<E_F}{\mathrm{\&Sigma;}}\underset{B.Z.}{\&Integral;}(1-f(E(k,n),E_F,T))d^{3}k}$

Wherein f is that Fermi's dirac distributes E _FIt is Fermi energy, T is a temperature, E (k, n) be with wave vector k and n can be with the energy of electronics in the corresponding state, subscript i and j refer to Cartesian coordinate x, y and z, integration carries out on Brillouin zone (B.Z.), and summation is carried out above and below being with of Fermi energy at energy for electronics and hole respectively.

[0032] applicant is such for the definition of conductivity-reciprocal effective mass tensor, and promptly the component of tensor of conductivity of electrolyte materials is bigger for the higher value of the respective component of conductivity-reciprocal effective mass tensor.Once more, the applicant theorizes, and does not wish to be confined to this theory, and superlattice described herein are provided with the value of conductivity-reciprocal effective mass tensor so that the conduction property of reinforcing material, for example preferred orientations that typically transports for electric charge carrier.Suitably the inverse of tensor element is called the conductivity effective mass.In other words, for characterize semiconductor material structures, use as mentioned above and the conductivity effective mass of the electrons/ calculated on expection carrier transport direction is distinguished improved material.

[0033] uses above-mentioned measurement, can select to have the material that improves band structure for specific purpose.Strained super lattice 25 materials that a kind of this example will be a channel region in the MOSFET device.At first describe according to the planar MOSFET 20 that the present invention includes strained super lattice 25 now with reference to figure 1.But, it will be understood by those skilled in the art that the material of identification can use here in many dissimilar semiconductor device, for example discrete device and/or integrated circuit.As an example, it is among the FINFET that another kind that strained super lattice 25 can use is therein used, as transfers and further describe in this assignee's the U. S. application sequence number 11/426,969, quotes its full content as a reference at this.

[0034] MOSFET 20 that illustrates comprises substrate 21, the stressor layers 26 on the substrate, and the semiconductor region 27,28 on the stressor layers, and strained superlattice layer 25 is on the stressor layers between the semiconductor region.More particularly, stressor layers 26 can be graded semiconductor layer, for example graded silicon Germanium layer.And semiconductor region 26,27 can be for example silicon or silicon Germanium regions.Be injected with to semiconductor region 26,27 illustratives dopant, with source electrode and the drain region 22,23 that MOSFET 20 is provided, as being appreciated by those skilled in the art.

[0035] the various superlattice structures that can use in MOSFET 20 are further discussed below.Under the situation of silicon-oxygen superlattice, the spacing of lattice of superlattice layer 25 will be usually less than silicon Germanium stress layer 26.But the stressor layers 26 in this example causes elongation strain in superlattice layer 25, and this for example can be used to provide among the N passage FET further that mobility strengthens.As selection, can select the composition of superlattice layer 25 and stressor layers 26, make superlattice will have the big spacing of lattice of specific stress layer in addition.This will advantageously cause compression strain in superlattice layer 25, this can advantageously provide, and the further mobility of superlattice strengthens in the P passage FET device for example.

[0036] in the embodiment of explanation, stressor layers is the graded semiconductor layer of classification in vertical direction, and strained super lattice 25 stacked vertical are on graded semiconductor layer.In alternative embodiment illustrated in fig. 6, MOSFET 20 ' further comprise graded semiconductor layer 26 ' and strained superlattice layer 425 ' between unassorted basically semiconductor layer 42 '.Just, the consistent basically semi-conducting material of unassorted basically semiconductor layer 42 ' have everywhere from the top to the bottom is formed (for example SiGe), and provide stressor layers 26 ' and superlattice layer 425 ' between buffering.More particularly, unassorted basically semiconductor layer 42 ' can have the composition substantially the same with the semi-conducting material that is positioned at stressor layers 42 ' top.Can be about the more information of the classification of covering semiconductor layer (for example silicon) strain on making and the not use of hierarchical layer No. 2005/0211982, people's such as Lei U.S. Patent Publication, No. 2005/0054175 of Bauer, No. 2005/0224800 of people such as Lindert, and find in No. 2005/0051795 of people such as Arena, quote its full content as a reference at this.

[0037] covers above the source/ drain regions 22,23 to source/ drain silicide layers 30,31 and source/ drain contact 32,33 illustratives, as be appreciated by those skilled in the art.The adjacent gate insulator 37 of passage that comprises to grid 35 illustratives and provide by strained superlattice layer 25, and be positioned at gate electrode layer 36 on the gate insulator.Sidewall spacers 40,41 also is provided among the MOSFET 20 of explanation.

[0038] theorize equally, the MOSFET 20 that semiconductor device for example illustrates will enjoy than otherwise will exist higher based on charge carrier mobility than the low conductivity effective mass.In some embodiments, and result as energy band engineering, superlattice 25 can further have DIRECT ENERGY band gap basically, this is for for example opto-electronic device possibility advantageous particularly, for example at the common pending application of title for " INTERGRATED CIRCUIT COMPRISING ANACTIVE OPTICAL DEVICE HAVING AN ENERGY BANDENGINEERED SUPERLATTIC (comprising integrated circuit) " with the active optics device that can be with the design superlattice, transfer this assignee's U.S. Patent Application Serial Number 10/936, those of stating in 903 are quoted its full content as a reference at this.

[0039] as being appreciated by those skilled in the art, the source/drain regions 22 of MOSFET 20,23 and grid 35 can regard as and make electric charge carrier on parallel direction, transport zone by strained superlattice layer 25 with respect to stacked groups of layers 45a-45n, as will be discussed further below.Just, the passage of device is limited in the superlattice 25.Other this zones are also considered by the present invention.

[0040] in certain embodiments, superlattice 25 can be advantageously used for the interface of gate dielectric layer 37.For example, channel region can be limited in the bottom of superlattice 25 (though some of passage also can be limited in the semi-conducting material below the superlattice), and its top isolates passage and dielectric layer 37.In another embodiment, passage can be limited in the stressed zone 26 individually, and strained superlattice layer 25 can only comprise as insulation/interface layer.

[0041] superlattice 25 as dielectric interface layer may be under the situation of using relative high-K gate dielectric substance particularly suitable.Superlattice 25 can provide the diffusion of minimizing with respect to the prior art insulating barrier that typically is used for the high-k dielectrics interface (for example silica), thus the mobility that strengthens.And superlattice 25 can cause advantages of small integral thickness as the insulator for the application of using high-k dielectrics, thus the device capacitor that improves.This be because superlattice 25 can be relatively little thickness form, and still provide the insulating property (properties) of expectation, as further discussing in this assignee's the common unsettled U. S. application sequence number 11/136,881 transferring, quote its full content as a reference at this.

[0042] applicant has discerned the improvement material or the structure of the channel region of MOSFET 20.More specifically, the applicant discerned have electronics and/or hole suitable conductivity effective mass basically less than the material or the structure of the band structure of the analog value of silicon.

[0043] now in addition with reference to figure 2 and 3, material or structure are the forms of superlattice 25, and its structure controls and can use known atom or molecular layer deposition technique to form at atom or molecule rank.Superlattice 25 comprise a plurality of layers of group 45a-45n that arrange with stacked relation, as perhaps specifically with reference to the schematic cross-sectional view best understanding of figure 2.And, as transfer the intermediate annealing process of describing in this assignee's the common unsettled U. S. application sequence number 11/136,834 and also can be used for advantageously reducing defective and cover surface being provided during manufacture, quote its full content as a reference at this.

[0044] each layer of superlattice 25 group 45a-45n illustrative ground comprises and limits a plurality of stacked base semiconductor monolayer 46 of base semiconductor portion 46a-46n separately, with and on can be with modification layers 50.Clear in order to illustrate, can be with modification layer 50 in Fig. 2, to indicate by strokes and dots.

[0045] can be with modification layer 50 illustrative ground to comprise an intracell monolayer that is limited in the adjacent foundation semiconductor portions.Just, the relative base semiconductor monolayer 46 among the adjacent groups of layers 45a-45n chemically combines.For example, under the situation of silicon single-layer 46, the top of individual layer group 46a or some silicon atoms in the top semiconductor monolayer will with the group bottom of 46b or the silicon atom covalent bond in the individual layer of bottom, as seeing among Fig. 3.This allows lattice continuously by layer group, although the existence of monolayer (for example, oxygen individual layer).Certainly, to there be complete or pure covalent bond between the relative silicon layer 46 of adjacent set 45a-45n, because some silicon atoms in each of these layers will be attached to non-semiconductor atom (just, the oxygen in this example), as being appreciated by those skilled in the art.

[0046] in other embodiments, be possible more than a this individual layer.Should be noted that and mentioning of non-semiconductor or semiconductor monolayer meaned that the material that is used for individual layer will be non-semiconductor or semiconductor if form with bulk here.Just, the single individual layer of material, semiconductor for example is if may not necessarily show the identical character that it will show when forming with block or thick relatively layer, as being appreciated by those skilled in the art.

[0047] applicant theorizes, and do not wish to be confined to this theory, can be with revise layer 50 and adjacent foundation semiconductor portions 46a-46n make superlattice 25 have than otherwise the suitable conductivity effective mass of electric charge carrier on the lower parallel layers direction that will exist.Another kind method considers that this parallel direction is perpendicular to stacked direction.The energy band is revised layer 50 also can be so that superlattice 25 have common energy band structure.

[0048] theorize equally, the MOSFET 20 that semiconductor device for example illustrates enjoy than otherwise will exist higher based on charge carrier mobility than the low conductivity effective mass.In some embodiments, and as the result of the energy band engineering of being realized by the present invention, superlattice 25 can further have DIRECT ENERGY band gap basically, and this may advantageous particularly for opto-electronic device for example, and is as will be described in further detail below.Certainly, the whole above-mentioned character of superlattice 25 need not used in each is used.For example, in some applications, superlattice 25 may be only use because of its dopant blocking/insulating property (properties) or its enhancing mobility, and perhaps in other were used, it may use because of the two, as being appreciated by those skilled in the art.

[0049] in some embodiments, may reside in to be with more than a monolayer and revise in the layer 50.As an example, can be with the number of revising monolayer in the layer 50 can be preferably less than about five individual layers, thus expectation is provided can be with modification character.

[0050] superlattice 25 also comprise to illustrative the cap rock 52 that is positioned on the upper layer group 45n.Cap rock 52 can comprise a plurality of base semiconductor monolayer 46.Cap rock 52 can have 2-100 individual layer of base semiconductor, more preferably, and 10-50 individual layer.

[0051] each base semiconductor portion 46a-46n can comprise and is selected from IV family semiconductor, the semi-conductive base semiconductor of III-V family semiconductor and II-VI family.Certainly, term IV family semiconductor also comprises IV-IV family semiconductor, as being appreciated by those skilled in the art.More particularly, base semiconductor can comprise at least a of for example silicon and germanium.

[0052] each can comprise and be selected from for example non-semiconductor of oxygen, nitrogen, fluorine and carbon-oxygen with revising layer 50.Non-semiconductor is also expected by the deposition of following one deck thermally-stabilised, thereby is convenient to make.In other embodiments, non-semiconductor can be another kind of inorganic or organic element or the compound with given semiconductor processes compatibility, as being appreciated by those skilled in the art.

[0053] should be noted that term mono-layer means comprises single atomic layer and individual molecule layer.Should be noted that equally the modification layer 50 of being with that is provided by single individual layer also means the individual layer that comprises that not all possible position is all occupied, as mentioned above.For example, with reference to the atomic diagram of figure 3,, 4/1 repetitive structure is described especially for as the silicon of base semiconductor material with as being with the oxygen of revising material.The possible position of oxygen only half is occupied.

[0054] in other embodiments and/or use different materials, this half occupy with not necessarily setting up, as being appreciated by those skilled in the art.In fact, even can see in this schematic diagram that each oxygen atom in the given individual layer is not accurately aimed at the plane, as what will understand by the technical staff in atomic deposition field.As an example, preferably occupy scope and be possible oxygen position full up 1/8th to half, though other numerals can be used in certain embodiments.

[0055] silicon and oxygen are current is extensive use of in conventional semiconductor processes, and therefore, manufacturer will readily be able to use these materials as describing ground here.Atom or monolayer deposition also are extensive use of now.Therefore, can easily adopt and realize comprising the semiconductor device of superlattice 25, as being appreciated by those skilled in the art.

[0056] theorize, and the applicant does not wish to be confined to this theory, for superlattice Si/O superlattice for example, the number of silicon single-layer should desirably be seven or still less, makes being with of superlattice common or even relatively everywhere, to realize desired advantages.Certainly, can use in some embodiments more than seven silicon layers.Shown in the simulation drawing 2 and 3 for 4/1 repetitive structure of Si/O enhancing mobility with electronics and hole on the indication directions X.For example, the electronic conductivity effective mass of calculating (for body silicon isotropism) is 0.26, and for 4/1 SiO superlattice on the directions X, it is 0.12, causes 0.46 ratio.Similarly, the calculating in hole produces 0.36 value and produces 0.16 value for 4/1 Si/O superlattice for body silicon, causes 0.44 ratio.

[0057] though this direction preferred feature may expect that in some semiconductor device other devices may be benefited from the more even increase of mobility on any direction parallel with layer group.This may also be of value to have for electronics and hole the two, perhaps only a kind of increase mobility of the electric charge carrier of these types will be as being appreciated by those skilled in the art.

[0058] 4/1 Si/O embodiment of superlattice 25 than the low conductivity effective mass may less than otherwise with 2/3rds of the conductivity effective mass that takes place, and this is applicable to electronics and hole.Certainly, superlattice 25 can also comprise the conductivity dopant of at least a type, as also being appreciated by those skilled in the art.If superlattice will provide passage some or all, at least a portion of doped superlattice 25 may be suitable especially.But superlattice 25 or its part also can keep not mixing basically in some embodiments, as further describing in this assignee's the U. S. application sequence number 11/136,757 transferring, quote its full content as a reference at this.

[0059] now in addition with reference to figure 4, describe now have of different nature according to superlattice 25 of the present invention ' another embodiment.In this embodiment, 3/1/5/1 repeat patterns is described.More particularly, lowest base semiconductor portion 46a ' has three individual layers, and inferior bottom base semiconductor portion 46b ' has five individual layers.This pattern is in superlattice 25 ' repetition everywhere.Energy band modification layer 50 ' each can comprise single individual layer.For this superlattice 25 that comprise Si/O ', the enhancing of charge carrier mobility and the orientation in the layer plane are irrelevant.Other elements of those that specifically do not mention among Fig. 4 with discuss in the above with reference to figure 2 those are similar, do not need here further to discuss.

[0060] in some device embodiments, all base semiconductor portion of superlattice can be the single monolayer thick of similar number.In other embodiments, at least some of base semiconductor portion can be the single monolayer thick of different numbers.In other embodiments again, all base semiconductor portion all may be the single monolayer thick of different numbers.

[0061] in Fig. 5 A-5C, shows the band structure of using density functional theory (DFT) to calculate.Well known in the art, DFT underestimates the absolute value of band gap.Therefore, all of band gap top can be with being moved by suitable " cutting out correction ".But the shape that can be with is known more reliable.In this connection, should explain vertical energy axes.

[0062] Fig. 5 A shows for body silicon (being represented by solid line) with for 4/1 Si/O superlattice 25 (being illustrated by the broken lines) shown in Fig. 1-3, from the band structure of gamma point (G) calculating.Direction refers to the unit cell of 4/1 Si/O structure rather than refers to the conventional unit cell of Si, though therefore (001) direction among the figure shows the desired locations of Si conduction band minimum really corresponding to (001) direction of the conventional unit cell of Si.(100) among the figure and (010) direction are corresponding to (110) and (110) direction of conventional Si unit cell.It will be understood by those skilled in the art that being with of Si on the figure folds to represent that they are positioned on the suitable reciprocal lattice direction of 4/1 Si/O structure.

Can see that [0063] conduction band minimum of 4/1 Si/O structure is positioned at gamma point, with body silicon (Si) contrast, yet valence band minimum appears at the edge of Brillouin zone on (001) direction, and we are called the Z point.Can note equally, compare, the perturbation that the more deep camber of the conduction band minimum of 4/1 Si/O structure is introduced owing to the other oxygen layer of reason and cause can be with division with the curvature of the conduction band minimum of Si.

[0064] Fig. 5 B shows for body silicon (solid line) with for 4/1 Si/O superlattice 25 (dotted line), from the band structure of Z point calculating.The enhancing curvature of valence band on this figure explanation (100) direction.

[0065] Fig. 5 C show for body silicon (solid line) and for the superlattice 25 of Fig. 4 ' 5/1/3/1 Si/O structure (dotted line), from the band structure of gamma and the calculating of Z point.Because the symmetry of 5/1/3/1 Si/O structure, the band structure of calculating on (100) and (010) direction is of equal value.Therefore, conductivity effective mass and mobility are desirably in parallel with layer, isotropism in promptly vertical with (001) stacked direction plane.Notice that in 5/1/3/1 Si/O example, conduction band minimum and valence band maximum are all near Z point or Z point.

[0066] though the curvature that increases is the indication of the effective mass that reduces, can carry out suitable comparison and differentiation via conductivity-reciprocal effective mass tensor computation.This further theorizes applicant guiding, i.e. 5/1/3/1 superlattice 25 ' should be direct band gap basically.As being appreciated by those skilled in the art, the suitable matrix element of optical transition is another index of distinguishing between direct and the indirect band gap behavior.

[0067] turns to Fig. 7-9 in addition, describe the other embodiment of each MOSFET that comprises strained superlattice layer 120,220 and 320 now.In the embodiment that illustrates, pass through 100 incremental representation (for example, the substrate 121,221 and 321 that shows respectively among Fig. 7-9 is similar to substrate 21) with the zone with top those similar each layers of discussing with reference to figure 1.

[0068] in MOSFET 120, stressor layers is provided by the strain inducing post 144 at a plurality of intervals on (bottom surface just) on the back side that is arranged in substrate 121 with side by side relationship.As an example, if the expectation compression strain, then pillar 144 can comprise plasma-enhanced chemical vapor deposition (PECVD) silicon nitride (SiN), metal, perhaps in being deposited on substrate 121 back sides in the groove of etching the time or the other materials of the compression that becomes afterwards.And if the expectation elongation strain, then pillar can comprise the SiN material or low-pressure chemical vapor deposition (LPCVD) the SiN material of for example thermosetting.Certainly, also can use other suitable materials well known by persons skilled in the art.The more details of arranging about back side strain inducing post can find in No. 2005/0263753, people's such as Pelella U.S. Patent Publication, quote its full content as a reference at this.

[0069] and, insulating barrier 143 (clear, use strokes and dots show), for example SiO in order to illustrate ₂Layer also can be to provide the semiconductor-on-insulator embodiment between stressor layers 125 and strained superlattice layer, as shown, though insulating barrier need all not use in all embodiments.Provide transferring in this assignee's the common unsettled U. S. application sequence number 11/381,835 about the more details that on semiconductor-on-insulator substrate, form superlattice structure as mentioned above, quote its full content as a reference at this.Certainly, use in other embodiments that semiconductor-on-insulator is realized here discussing.

[0070] with reference to figure 8, in MOSFET 20, zone 327,328 limits the stressed zone at a pair of interval, is used for causing strain at therebetween superlattice layer 125.More particularly, one of the stressed zone or whole two can be included in the material that causes the expectation strain on the superlattice layer 225.Use above-mentioned example, for silicon-oxygen superlattice layer 225, one or whole two of zone 327,328 can comprise SiGe., yet in MOSFET 20, when below being positioned at superlattice layer 25, SiGe causes elongation strain, and in the time of when a side that is positioned at superlattice layer 225 or all on the both sides, SiGe has opposite effect and compression superlattice.

[0071] therefore, in the embodiment of explanation, the SiGe in the stressed zone 227,228 realizes it will being favourable for the P passage, because it causes compression strain.As selection, elongation strain can advantageously cause in the superlattice layer 225 of N passage device by the composition of suitably selecting superlattice and stressed zone 227,228, and is as discussed above.Should be noted that in some embodiments stressed zone 227,228 does not at interval need to comprise identical materials.Just, strain can be at a stressed zone with respect to " pushing away " as another of anchor or causing when " drawing ".

[0072] in the above-described embodiment, mix this counter stress district 227,228 so that source electrode and drain region 222,223 to be provided.And, comprise to stressed zone 227,228 illustratives inclined surface adjacent or facet 245,246 with the relative part of strained super lattice.Inclined surface 245,246 can be produced by the etching technics that is used for superlattice 225 are formed pattern, makes stress induced material can be adjacent deposition.But surface 245,246 need all not tilt in all embodiments.The more details of strained channel device that have strain inducing source electrode and drain region about manufacturing are at people's such as Yu United States Patent (USP) 6,495, open in No. 2005/0142768, people's such as No. 402 and Lindert the U.S. Patent Publication, at this full content of quoting the two as a reference.

[0073], comprises to MOSFET 320 illustratives the stressor layers 347 that is positioned on the strained superlattice layer 325 with reference to figure 9.As an example, stressor layers can be the source electrode that is deposited on MOSFET320, the SiN floor in the drain and gate district, and it causes strain in comprising the bottom semi-conducting material of superlattice layer 325.As mentioned above, depend on the deformation type of expectation in the superlattice layer 325, can use to stretch or compressive nitride material.Certainly, other suitable materials also can be used for stressor layers 347, and can use a plurality of stressor layers in some embodiments.And in certain embodiments, superlattice layer 325 can " be remembered " strain that is caused by overlying stress layer 347, and after this can remove stressor layers, as being appreciated by those skilled in the art.Can in No. 2005/0247926 of people such as people's such as Chau No. 2005/0145894, U.S. Patent Publication and Sun, find about the more details that produce strain in the semiconductor region that covers stressor layers in the use, as a reference at this full content of quoting the two.

[0074] for example first method aspect of MOSFET20 that is used for producing the semiconductor devices according to the present invention is described now.This method comprises formation stressor layers 26, and forms strained superlattice layer 25 on stressor layers.Another method aspect is used for producing the semiconductor devices, and for example MOSFET 220, and it comprises formation superlattice layer 225, and forms at least one pair of stressed zone 227,228 at interval so that cause strain therein on the opposite side of superlattice layer.Another method aspect is used for producing the semiconductor devices, and for example MOSFET 320, and it comprises formation superlattice layer 325, and forms stressor layers 347 so that cause strain therein on strained superlattice layer.Various additive method steps and aspect will be appreciated by those skilled in the art from aforementioned description, therefore not need further here to discuss.

Should be noted that in the above-described embodiment that [0075] strained layer does not need superlattice 25 always.On the contrary, strained layer can only comprise a plurality of base semiconductor portion 46a-46n, and (just the adjacent foundation semiconductor portions chemically combines, as mentioned above) to be limited in intracell one or more monolayer 50 of adjacent foundation semiconductor portions.In this embodiment, base semiconductor portion 46a-46n does not need to comprise a plurality of semiconductor monolayer, and just, each semiconductor portions can comprise for example single layer or a plurality of individual layer.

[0076] MOSFET 80 that comprises to illustrative semiconductor monolayer 81 illustrates to show in Figure 10, wherein semiconductor monolayer below laying respectively at monolayer and above part 82a, among the 82b.Be positioned on the passage 85 to gate-dielectric 83 illustratives, and gate electrode 84 is positioned on the gate-dielectric.Area limiting interface 86 between the top of the bottom of gate-dielectric 83 and passage 85.The position will be laterally adjacent with passage 85 for source electrode and drain electrode (not showing), as being appreciated by those skilled in the art.

[0077] can be based on the individual layer of MOSFET design alternative non-semiconductor material 81 the degree of depth, as being appreciated by those skilled in the art apart from interface 86.For example, the about degree of depth of 4-100 individual layer, and the about degree of depth of 4-30 individual layer more preferably can be selected for the oxygen layer in the silicon passage for typical MOSFET 86.At least one individual layer of this of non-semiconductor material can comprise the one or more individual layers that do not spread all over all available positions fully, as mentioned above.

[0078] as discussed above, non-semiconductor can be selected from for example oxygen, nitrogen, fluorine and carbon-oxygen.At least one individual layer of non-semiconductor material 81 for example can use the technique for atomic layer deposition deposition, similarly, as described above and as being appreciated by those skilled in the art.Other depositions and/or method for implanting also can be used for forming passage 85 with at adjacent semiconductor layer 82a, comprise this at least one non-semiconductor material layer 81 in the lattice of 82b.

[0079] density contrast at the interface is that the emulation chart 90 of the oxygen layer depth of unit shows in Figure 11 with the dust.As being appreciated by those skilled in the art, in the MOSFET 80 that embodiment for example illustrates, do not need to use the repeating groups of superlattice, yet this at least one monolayer 81 still can provide the enhancing to mobility.In addition, the applicant also theorizes, and does not wish to be confined to this theory, and as the result who reduces amplitude of interface 86 place's wave functions, these embodiments also will have lower tunnel effect gate leakage.Theorize equally, more desired characters of these embodiments comprise the energy spacing that increases between sub can being with, and the sub spatial separation that can be with, can be with diffusion thereby reduce son.

[0080] certainly in other embodiments, this at least one individual layer 81 also can use in conjunction with the bottom superlattice, as being appreciated by those skilled in the art.In addition, the many modifications of the present invention and other embodiments with benefit of the instruction that proposes in aforementioned description and relevant drawings will be expected by those skilled in the art easily.Therefore, should be appreciated that the present invention is not limited to disclosed specific embodiments, and modification and embodiment are expected.

Claims (25)

1. semiconductor device comprises:

The strained superlattice layer that comprises a plurality of stacked groups of layers; And

Be positioned at the stressor layers above the described strained superlattice layer;

Each of described strained superlattice layer layer group comprises a plurality of stacked base semiconductor monolayer that limits base semiconductor portion, and intracell at least one monolayer that is limited in the adjacent foundation semiconductor portions.

2. according to the semiconductor device of claim 1, wherein said stressor layers comprises silicon and nitrogen.

3. according to the semiconductor device of claim 1, also comprise making electric charge carrier on parallel direction, transport zone by described strained superlattice layer with respect to stacked groups of layers.

4. according to the semiconductor device of claim 1, also comprise adjacent with described strained superlattice layer, be positioned at the Semiconductor substrate on the relative side with described stressor layers.

5. according to the semiconductor device of claim 1, wherein each base semiconductor portion comprises and is selected from IV family semiconductor, the semi-conductive base semiconductor of III-V family semiconductor and II-VI family; And wherein each monolayer comprises the non-semiconductor that is selected from oxygen, nitrogen, fluorine and carbon-oxygen.

6. according to the semiconductor device of claim 1, wherein the adjacent foundation semiconductor portions chemically combines.

7. according to the semiconductor device of claim 1, wherein each monolayer is single single monolayer thick.

8. semiconductor device comprises:

Comprise a plurality of stacked base semiconductor portion and the strained layer that is limited in intracell at least one monolayer of adjacent foundation semiconductor portions; And

Be positioned at the stressor layers above the described strained layer.

9. semiconductor device according to Claim 8, wherein said stressor layers comprises silicon and nitrogen.

10. semiconductor device according to Claim 8 also comprises making electric charge carrier transport the zone by described strained layer on the parallel direction with respect to stacked groups of layers.

11. semiconductor device according to Claim 8, also comprise adjacent with described strained layer, be positioned at the Semiconductor substrate on the relative side with described stressor layers.

12. semiconductor device according to Claim 8, wherein the adjacent foundation semiconductor portions chemically combines.

13. a method of making semiconductor device comprises:

Formation comprises the superlattice layer of a plurality of stacked groups of layers; And

On superlattice layer, form stressor layers to cause strain therein;

Each of superlattice layer layer group comprises a plurality of stacked base semiconductor monolayer that limits base semiconductor portion, and intracell at least one monolayer that is limited in the adjacent foundation semiconductor portions.

14., also comprise the removal stressor layers according to the method for claim 13.

15. according to the method for claim 13, wherein stressor layers comprises silicon and nitrogen.

16., also comprise forming making electric charge carrier on parallel direction, transport zone by strained superlattice layer with respect to stacked groups of layers according to the method for claim 13.

17., wherein form superlattice layer and be included in and form superlattice layer on the Semiconductor substrate according to the method for claim 13; And wherein form stressor layers and be included on the side relative above the superlattice layer and form stressor layers with Semiconductor substrate.

18. according to the method for claim 13, wherein each base semiconductor portion comprises and is selected from IV family semiconductor, the semi-conductive base semiconductor of III-V family semiconductor and II-VI family; And wherein each monolayer comprises the non-semiconductor that is selected from oxygen, nitrogen, fluorine and carbon-oxygen.

19. according to the method for claim 13, wherein the adjacent foundation semiconductor portions chemically combines.

20. a method of making semiconductor device comprises:

Formation comprises a plurality of stacked base semiconductor portion and the strained layer that is limited in intracell at least one monolayer of adjacent foundation semiconductor portions; And

On strained layer, form stressor layers to cause strain therein.

21., also comprise the removal stressor layers according to the method for claim 20.

22. according to the method for claim 20, wherein stressor layers comprises silicon and nitrogen.

23., also comprise forming making electric charge carrier on parallel direction, transport zone by strained layer with respect to stacked groups of layers according to the method for claim 20.

24., wherein form strained layer and be included in and form strained layer on the Semiconductor substrate according to the method for claim 20; And wherein form stressor layers and be included on the side relative above the strained layer and form stressor layers with Semiconductor substrate.

25. according to the method for claim 20, wherein the adjacent foundation semiconductor portions chemically combines.

Images