CN114258593A

CN114258593A - Semiconductor device having hyperabrupt junction regions with spaced superlattices and related methods

Info

Publication number: CN114258593A
Application number: CN202080058845.XA
Authority: CN
Inventors: R·伯顿; M·海塔; R·J·米尔斯
Original assignee: Atomera Inc
Current assignee: Atomera Inc
Priority date: 2019-07-17
Filing date: 2020-07-15
Publication date: 2022-03-29
Also published as: EP4000101A1; TW202105727A; WO2021011635A1; TWI747378B

Abstract

A semiconductor device may include a substrate and a hyperabrupt junction region carried by the substrate. The super mutation region may include a first semiconductor layer having a first conductive type, a first superlattice layer on the first semiconductor layer, a second semiconductor layer on the first superlattice layer and having a second conductive type different from the first conductive type, and a second superlattice layer on the second semiconductor layer. The semiconductor device may further include a gate dielectric layer on the second superlattice layer of the hyperabrupt junction region, a gate electrode on the gate dielectric layer, and spaced apart source and drain regions adjacent the hyperabrupt junction region.

Description

Semiconductor device having hyperabrupt junction regions with spaced superlattices and related methods

Technical Field

The present disclosure relates generally to semiconductor devices and, more particularly, to semiconductor devices including hyperabrupt junctions and related methods.

Background

Structures and techniques have been proposed to enhance the performance of semiconductor devices, such as by enhancing the mobility of charge carriers. For example, U.S. patent application No.2003/0057416 to Currie et al discloses strained material layers of silicon, silicon germanium, and relaxed silicon, and also includes impurity-free regions (which would otherwise cause performance degradation). The resulting biaxial strain in the upper silicon layer modifies carrier mobility, thereby enabling higher speed and/or lower power devices. Published U.S. patent application No.2003/0034529 to Fitzgerald et al discloses a CMOS inverter that is also based on similar strained silicon technology.

U.S. patent No.6,472,685b2 to Takagi discloses a semiconductor device including silicon and a carbon layer sandwiched between silicon layers such that the conduction and valence bands of the second silicon layer receive a tensile strain. Electrons that are of smaller effective mass and that have been induced by an electric field applied to the gate electrode are confined in the second silicon layer, thus asserting that the n-channel MOSFET has a higher mobility.

U.S. patent No.4,937,204 to Ishibashi et al discloses a superlattice in which a plurality of layers, less than eight monolayers therein and containing fractional or binary compound semiconductor layers, are alternately and epitaxially grown. The direction of main current flow is perpendicular to the layers of the superlattice.

U.S. patent No.5,357,119 to Wang et al discloses Si-Ge short period superlattices with higher mobility obtained by reducing alloy scattering in the superlattice. Along these lines, U.S. patent No.5,683,934 to Candelaria discloses an enhanced mobility MOSFET including a channel layer comprising a silicon alloy alternating with a second material in a silicon lattice at a percentage that places the channel layer under tensile strain.

U.S. patent No.5,216,262 to Tsu discloses a quantum well structure comprising two barrier regions and an epitaxially grown thin semiconductor layer sandwiched between the barriers. Each barrier region is composed of alternating layers of SiO2/Si, typically ranging in thickness from two to six monolayers. A much thicker portion of silicon is sandwiched between barrier layers.

Also published by Tsu on-line at Applied Physics and Materials Science & Processing, page 391-402 in 2000, 9/6.T., an article entitled "Phenomena in silicon nanostructured devices" discloses a Semiconductor Atomic Superlattice (SAS) of silicon and oxygen. Si/O superlattices are disclosed as being useful in silicon quantum and light emitting devices. In particular, a green electroluminescent diode structure was constructed and tested. The current flow in the diode structure is vertical, i.e. perpendicular to the layers of the SAS. The disclosed SAS may include semiconductor layers separated by adsorbed species such as oxygen atoms and CO molecules. Silicon growth beyond the adsorbed monolayer of oxygen is described as epitaxial growth with a fairly low defect density. One SAS structure included a 1.1nm thick silicon portion that was approximately an eight atomic layer of silicon, while the other structure had twice the thickness of silicon. An article entitled "Chemical Design of Direct-Gap Light-Emitting Silicon" by Luo et al, published in Physical Review Letters, Vol.89, No.7 (8/12 2002), further discusses the Light-Emitting SAS structure of Tsu.

U.S. patent No.7,105,895 to Wang et al discloses a barrier layer building block formed of thin silicon and oxygen, carbon, nitrogen, phosphorus, antimony, arsenic or hydrogen, whereby more than four orders of magnitude further reduces the current flowing vertically through the lattice. The insulating layer/barrier layer allows low defect epitaxial silicon to be deposited alongside the insulating layer.

Published british patent application 2,347,520 to Mears et al discloses that the principles of Aperiodic Photonic Bandgap (APBG) structures can be applied to electronic bandgap engineering. In particular, this application discloses that material parameters (e.g., location of band minima, effective mass, etc.) can be tailored to produce novel aperiodic materials with desirable band structure characteristics. It is also disclosed that other parameters such as electrical conductivity, thermal conductivity and dielectric constant or magnetic permeability may also be designed into the material.

Further, U.S. patent No.6,376,337 to Wang et al discloses a method for producing an insulating or barrier layer for a semiconductor device, the method comprising depositing a silicon layer and at least one additional element on a silicon substrate, whereby the deposited layer is substantially defect-free, such that epitaxial silicon substantially defect-free can be deposited on the deposited layer. Alternatively, a monolayer of one or more elements (preferably including oxygen) is absorbed on the silicon substrate. A plurality of insulating layers sandwiched between the epitaxial silicon form a barrier composite.

Despite the existence of such approaches, further enhancements may be desirable to improve the performance of semiconductor devices using advanced semiconductor materials and processing techniques.

Disclosure of Invention

According to an example embodiment, the spaced apart source and drain regions may have the second conductivity type. Further, the first and second semiconductor layers and the first and second superlattice layers may be parallel to an underlying portion of the substrate. According to another example embodiment, the first and second semiconductor layers and the first and second superlattice layers may be U-shaped.

As an example, the first semiconductor layer and the second semiconductor layer may each have a thickness in a range of 50nm to 300 nm. Also by way of example, the base semiconductor monolayer may comprise at least one of silicon and germanium, and the at least one non-semiconductor monolayer may comprise at least one of oxygen, nitrogen, fluorine, carbon, and carbon-oxygen.

A method for fabricating a semiconductor device may include forming a hyperabrupt junction region over a substrate and including a first semiconductor layer having a first conductivity type, a first superlattice layer on the first semiconductor layer, a second semiconductor layer on the first superlattice layer and having a second conductivity type different from the first conductivity type, and a second superlattice layer on the second semiconductor layer. The method may also include forming a gate dielectric layer on the second superlattice layer of the hyperabrupt junction region, forming a gate electrode on the gate dielectric layer, and forming spaced apart source and drain regions adjacent the hyperabrupt junction region. The first and second superlattices each may include a plurality of stacked groups of layers, each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

More particularly, the spaced apart source and drain regions may have the second conductivity type. In one example embodiment, the first and second semiconductor layers and the first and second superlattice layers may be parallel to an underlying portion of the substrate. According to another example embodiment, the first and second semiconductor layers and the first and second superlattice layers may be U-shaped.

Drawings

Fig. 1 is a greatly enlarged schematic cross-sectional view of a superlattice for use in a semiconductor device in accordance with an example embodiment.

Fig. 2 is a perspective atomic schematic of a portion of the superlattice shown in fig. 1.

Fig. 3 is a greatly enlarged schematic cross-sectional view of another embodiment of a superlattice in accordance with an example embodiment.

Fig. 4A is a graph of the calculated band structure from the gamma point (G) for both bulk silicon in the prior art and for the 4/1Si/O superlattice as shown in fig. 1-2.

Fig. 4B is a graph of the calculated band structure from the Z point for both bulk silicon in the prior art and for the 4/1Si/O superlattice as shown in fig. 1-2.

Fig. 4C is a graph of the calculated band structure from the gamma and Z points for both bulk silicon in the prior art and for the 5/1/3/1Si/O superlattice as shown in fig. 3.

Fig. 5 is a schematic cross-sectional view of a JFET including a hyperabrupt junction incorporated into a superlattice according to an example embodiment.

Fig. 6 is a schematic cross-sectional view of an IGFET including a hyperabrupt junction incorporated into a superlattice, according to an example embodiment.

Fig. 7 is a schematic cross-sectional view of another IGFET including a hyperabrupt junction incorporating a single superlattice, according to an example embodiment.

Fig. 8 is a schematic cross-sectional view of a varactor including a hyperabrupt junction incorporated into a superlattice, according to an example embodiment.

Fig. 9A and 9B are schematic cross-sectional views of other varactors including a hyperabrupt junction incorporating a single superlattice according to example embodiments.

Fig. 10 is a flow diagram illustrating method aspects associated with fabrication of the device of fig. 5-7.

Fig. 11 is a flow diagram illustrating method aspects associated with the fabrication of the device of fig. 8-9.

Detailed Description

Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which example embodiments are shown. Embodiments may, however, be embodied in many different forms and should not be construed as limited to the specific examples set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. Like numbers refer to like elements throughout, and prime and multiple prime notation are used to indicate similar elements in different embodiments.

The present disclosure relates generally to devices having enhanced semiconductor superlattices therein. In the present disclosure and the accompanying drawings, the enhanced semiconductor superlattice is also referred to as the "MST" layer or "MST technique".

More particularly, MST technology relates to advanced semiconductor materials, such as the superlattice 25 as further described below. Applicants theorize without wishing to be bound thereto that certain superlattices as described herein reduce the effective mass of charge carriers and that this results in higher charge carrier mobility. Effective masses are defined variously in the literature. As a measure to improve the effective mass, applicants use the "conductivity reciprocal effective mass tensor", and for electrons and holes

And

for electrons are defined as:

and for the hole locations:

where f is a Fermi-Dirac (Fermi-Dirac) distribution, EF is Fermi energy, T is temperature, E (k, n) is the energy of an electron in a state corresponding to wave vector k and the nth band, indices i and j refer to cartesian coordinates x, y and z, the integration is taken over the Brillouin region (B.Z.), and the sum is taken over bands of electrons and holes with energies above and below the Fermi energy, respectively.

Applicants' definition of the reciprocal effective mass conductivity tensor is such that a tensor component of the electrical conductivity of the material is greater for greater values of the corresponding component of the reciprocal effective mass conductivity tensor. Without wishing to be bound by this, applicants theorize again that the superlattices described herein set the values of the conductivity reciprocal effective mass tensor so as to enhance the conductive properties of the material, such as typically for a preferred direction of charge carrier transport. The inverse of the appropriate tensor element is referred to as the conductivity effective mass. In other words, for characterizing the semiconductor material structure, the conductivity effective mass of electrons/holes as described above and calculated in the direction of expected carrier transport is used to distinguish improved materials.

Applicants have identified improved materials or structures for use in semiconductor devices. More specifically, applicants have identified materials or structures having band structures for which the appropriate conductivity effective mass for electrons and/or holes is substantially less than the corresponding value for silicon. In addition to the enhanced mobility characteristics of these structures, they may also be formed or used in a manner that provides piezoelectric, pyroelectric, and/or ferroelectric properties that are advantageous for use in a variety of different types of devices, as will be discussed further below.

Referring now to fig. 1 and 2, the material or structure is in the form of a superlattice 25 whose structure is controlled at the atomic or molecular level and may be formed using known techniques of atomic or molecular layer deposition. The superlattice 25 includes a plurality of layer groups 45a-45n arranged in stacked relation, as may be best understood with specific reference to the schematic cross-sectional view of fig. 1.

Each group of layers 45a-45n of the superlattice 25 illustratively includes a plurality of stacked base semiconductor monolayers 46 defining a respective base semiconductor portion 46a-46n and an energy band-modifying layer 50 thereon. For clarity of illustration, the energy band-modifying layer 50 is indicated by a dot-dash line in fig. 1.

The energy band-modifying layer 50 illustratively comprises a non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. By "constrained within the crystal lattice of adjacent base semiconductor portions" it is meant that at least some of the semiconductor atoms from the opposing base semiconductor portions 46a-46n are chemically bonded together by the non-semiconductor monolayer 50 therebetween, as seen in fig. 2. In general, this configuration is made possible by controlling the amount of non-semiconductor material deposited on the semiconductor portions 46a-46n by atomic layer deposition techniques such that not all (i.e., less than full or 100% coverage) of the available semiconductor bonding sites are filled with bonds to non-semiconductor atoms, as will be discussed further below. Thus, when an additional monolayer 46 of semiconductor material is deposited on or over the non-semiconductor monolayer 50, the newly deposited semiconductor atoms will fill the remaining vacant bonding sites of semiconductor atoms under the non-semiconductor monolayer.

In other embodiments, it is possible that there may be more than one such non-semiconductor monolayer. It should be noted that reference herein to a non-semiconductor or semiconductor monolayer means that if the material for the monolayer is formed in bulk, it will be non-semiconductor or semiconductor. That is, as one skilled in the art will recognize, a single monolayer of a material (such as silicon) does not necessarily exhibit the same characteristics as if formed in bulk or in a relatively thick layer.

Without wishing to be limited thereto, applicants theorize that the energy band-modifying layer 50 and the adjacent base semiconductor portions 46a-46n cause the superlattice 25 to have a lower appropriate conductivity effective mass for charge carriers in the parallel layer direction than would otherwise be present. Considered another way, this parallel direction is orthogonal to the stacking direction. The energy band-modifying layers 50 may also cause the superlattice 25 to have a common energy band structure while also advantageously acting as an insulator between layers or regions vertically above and below the superlattice.

Moreover, such a superlattice structure may also advantageously act as a barrier to dopant and/or material diffusion between layers vertically above and below the superlattice 25. These characteristics may thus advantageously allow the superlattice 25 to provide an interface for the high-K dielectric that not only reduces diffusion of the high-K material into the channel region, but may also advantageously reduce undesirable scattering effects and improve device mobility, as will be appreciated by those skilled in the art.

It is also theorized that semiconductor devices incorporating the superlattice 25 may enjoy a higher charge carrier mobility based upon the lower conductivity effective mass than would otherwise be present. In some embodiments, and as a result of the band design achieved by the present invention, the superlattice 25 may also have a substantially direct energy bandgap, which may be particularly advantageous for optoelectronic devices, for example.

The superlattice 25 also illustratively includes a cap layer 52 on an upper layer group 45 n. The cap layer 52 may include a plurality of base semiconductor monolayers 46. The cap layer 52 may have 2 to 100 monolayers of the base semiconductor, and more preferably 10 to 50 monolayers.

Each base semiconductor portion 46a-46n may comprise a base semiconductor selected from group IV semiconductors, group III-V semiconductors, and group II-VI semiconductors. Of course, as will be appreciated by those skilled in the art, the term "group IV semiconductor" also includes group IV-IV semiconductors. More particularly, for example, the base semiconductor may include at least one of silicon and germanium.

Each energy band-modifying layer 50 may include, for example, a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, carbon, and carbon-oxygen. It is also desirable to thermally stabilize the non-semiconductor by depositing the next layer, thereby facilitating fabrication. In other embodiments, the non-semiconductor may be another inorganic or organic element or compound that is compatible with a given semiconductor process, as will be appreciated by those skilled in the art. More particularly, for example, the base semiconductor may include at least one of silicon and germanium.

It should be noted that the term monolayer is meant to include a single atomic layer as well as a single molecular layer. It should also be noted that the energy band-modifying layer 50 provided by a single monolayer is also meant to include monolayers in which not all possible sites are occupied (i.e., less than full or 100% coverage). For example, referring specifically to the atomic diagram of FIG. 2, an 4/1 repeating structure is illustrated, with silicon as the base semiconductor material and oxygen as the energy band-modifying material. In the example shown, only half of the possible sites for oxygen are occupied.

In other embodiments and/or for different materials, as those skilled in the art will recognize, this half occupation would not necessarily be the case. Indeed, even in this schematic diagram it can be seen that the individual atoms of oxygen in a given monolayer are not precisely aligned along a flat plane, as will be appreciated by those skilled in the art of atomic deposition. For example, a preferred occupancy range is approximately one-eighth to one-half of the possible oxygen site fill, although other numbers may be used in certain embodiments.

Silicon and oxygen are currently widely used in conventional semiconductor processing, and thus manufacturers will be readily able to use these materials described herein. Atomic or monolayer deposition is also now widely used. Thus, semiconductor devices incorporating the superlattice 25 in accordance with the invention may be readily adopted and implemented, as will be appreciated by those skilled in the art.

Without wishing to be bound by this, applicants theorize that, for example, for superlattices (such as Si/O superlattices), the number of silicon monolayers should desirably be seven or less, so that the energy bands of the superlattices are always common or relatively uniform to achieve the desired advantages. For Si/O, the 4/1 repeat structure shown in fig. 1 and 2 has been modeled to indicate enhanced mobility of electrons and holes in the X direction. For example, the calculated conductivity effective mass is 0.26 for electrons (isotropy for bulk silicon) and 0.12 for the 4/1SiO superlattice in the X direction, resulting in a ratio of 0.46. Similarly, for bulk silicon, the calculated value for holes is 0.36 and for the 4/1Si/O superlattice is 0.16, resulting in a ratio of 0.44.

While such directionally preferential features may be desirable in some semiconductor devices, other devices may benefit from a more uniform increase in mobility in any direction parallel to the groups of layers. As will be appreciated by those skilled in the art, it may also be beneficial to have increased mobility for both electrons and holes, or only one of these types of charge carriers.

The lower conductivity effective mass of the 4/1Si/O embodiment of the superlattice 25 may be less than two-thirds of that which would otherwise occur, and this applies to both electrons and holes. Of course, the superlattice 25 may further comprise at least one type of conductivity dopant therein as will also be appreciated by those skilled in the art.

Indeed, referring now additionally to fig. 3, another embodiment of a superlattice 25' in accordance with the invention having different properties is now described. In this embodiment, a repeating pattern of 3/1/5/1 is shown. More particularly, the lowermost base semiconductor portion 46a 'has three monolayers, and the second lowermost base semiconductor portion 46b' has five monolayers. This pattern repeats throughout the superlattice 25'. The energy band-modifying layers 50' may each comprise a single monolayer. For such superlattices 25' including Si/O, the enhancement of charge carrier mobility is independent of the orientation of the layers in the plane. Those other elements not specifically mentioned in fig. 3 are similar to those discussed above with reference to fig. 1 and need no further discussion herein.

In some device embodiments, all of the base semiconductor portions of the superlattice may be as thick as the same number of monolayers. In other embodiments, at least some of the base semiconductor portions may be as thick as a different number of monolayers. In other embodiments, all of the base semiconductor portions may be as thick as a different number of monolayers.

In fig. 4A-4C, the band structure calculated using Density Functional Theory (DFT) is presented. It is well known in the art that DFT underestimates the absolute value of the bandgap. Thus, all bands above the gap can be shifted by appropriate "scissor correction". However, the shape of the energy bands is known to be much more reliable. The vertical energy axis should be interpreted in this angle.

Fig. 4A shows the calculated band structure from the gamma point (G) for both the bulk silicon (represented by continuous lines) and for the 4/1Si/O superlattice 25 shown in fig. 1 (represented by dotted lines). These directions relate to the unit cell of the 4/1Si/O structure, not the conventional unit cell of Si, but the (001) direction in the figure does correspond to the (001) direction of the conventional unit cell of Si, thus showing the expected location of the Si conduction band minimum. The (100) and (010) directions in the figure correspond to the (110) and (-110) directions of the conventional Si unit cell. Those skilled in the art will recognize that the energy bands of Si on the figure are folded to represent them in the appropriate reciprocal lattice direction for the 4/1Si/O structure.

It can be seen that the conduction band minimum for the 4/1Si/O structure is located at the gamma point compared to bulk silicon (Si), while the valence band minimum occurs at the edge of the brillouin zone in the (001) direction, which we refer to as the Z point. It may also be noted that the conduction band minimum for the 4/1Si/O structure has a greater curvature than the curvature of the conduction band minimum for Si due to band splitting caused by the perturbation introduced by the additional oxygen layer.

Fig. 4B shows the calculated band structure from the Z point for both bulk silicon (continuous lines) and the 4/1Si/O superlattice 25 (dotted lines). This figure illustrates the enhanced curvature of the valence band in the (100) direction.

Fig. 4C shows the calculated band structure from both the gamma and Z points for both the bulk silicon (continuous lines) and the 5/1/3/1Si/O structure for the superlattice 25' of fig. 3 (dotted lines). The calculated band structures in the (100) and (010) directions are equivalent due to the symmetry of the 5/1/3/1Si/O structure. Thus, the conductivity effective mass and mobility are expected to be isotropic in the plane parallel to the layers (i.e., perpendicular to the (001) stacking direction). Note that in the 5/1/3/1Si/O example, both the conduction band minimum and the valence band maximum are at or near the Z-point.

Although an increase in curvature indicates a decrease in effective mass, appropriate comparisons and determinations can be made via the conductivity reciprocal effective mass tensor calculation. This has led applicants further to the theory that 5/1/3/1 the superlattice 25' should be substantially a direct bandgap. As will be understood by those skilled in the art, a suitable matrix element for optical transition is another indicator of the distinction between direct bandgap behavior and indirect bandgap behavior.

Referring now to fig. 5, the superlattice structure described above may be advantageously used to provide a hyperabrupt junction in various semiconductor devices. In a typical super-junction or super-junction device, thin (e.g., 50nm-300nm) P and N layers are grown adjacent to each other to form a super-junction channel. However, a problem with this configuration is that the adjacent thin P and N layers will tend to compensate for each other by diffusion and will limit the mobility and amount of charge that can be effectively incorporated into the layers without degradation.

In example embodiments presented herein, one or more diffusion barrier superlattice layers, such as the MST superlattice layers discussed above, are advantageously incorporated into the hyperabrupt junction stack. The superlattice layer advantageously blocks interdiffusion and thus correspondingly increases the available charge with higher mobility due to less ionized impurity scattering. According to a first example, JFET 100 illustratively includes a semiconductor substrate 101 having a back gate 102 therein. Spaced apart source and drain

regions

104, 105 with

respective contacts

106, 107 are formed on the back gate 102 and a hyperabrupt junction region 108 is also formed on the back gate between the source and drain regions. Further, a back gate punch-through region 109 having a contact 110 is coupled to the back gate 102, and an isolation region 111 (e.g., oxide) separates the back gate punch-through region from the

source drain regions

104, 105. It should be noted that in some embodiments, the back gate punch-through region 109 may instead extend from the back side of the substrate 101 rather than from the top/front side as shown, in which case the contact(s) 110 would be on the back side of the substrate.

More particularly, the hyperabrupt junction region 108 illustratively includes a first semiconductor layer 112 having a first conductivity type (N or P), a first superlattice layer 125a on the first semiconductor layer, a second semiconductor layer 113 on the first semiconductor layer and having a second conductivity type (P or N) different from the first conductivity type, and a second superlattice layer 125b on the second semiconductor layer. Further, a gate overlies (overlap) the second superlattice layer 125b and illustratively includes a gate electrode 115, which will typically be of the same conductivity type (i.e., first conductivity type) as the back gate 102 and the first semiconductor layer 112, while the semiconductor layer 113 and the source/

drain regions

104, 105 will be of the same conductivity type (here, second conductivity type). The second semiconductor layer 113 of the hyperabrupt junction region 108 defines the hyperabrupt channel of the JFET 100. The

superlattice layers

125a, 125b effectively block interdiffusion and thus increase the available charge in the channel with higher mobility due to less ionized impurity scattering.

Referring additionally to the flow chart 120 of fig. 10, beginning at block 121, at block 122 the semiconductor layers 112, 113 and

superlattices

125a, 125b may be formed in an alternating manner as blanket layers (blanket layers) across the substrate 101, or selectively at desired locations on the substrate to form the hyperabrupt junction regions 108. In the example shown, the

superlattices

125a, 125b extend into the source and drain

regions

104, 105 and into the back gate punch-through region 109, but the superlattices may in some embodiments be constrained only within the channel region if desired. Then at block 123, a gate electrode layer 115 may be formed over the superlattice 125b, followed by a gate contact 116. At block 125, the source and drain

regions

106, 107 may be formed by doping with an appropriate conductivity type dopant (P-type for the P-channel, or vice versa), and the back gate punch-through region 109 may be similarly formed. Isolation regions 117 are also formed to isolate the source and

drain contacts

106, 107 from the gate contact. The method of fig. 10 illustratively ends at block 126.

Turning to fig. 6, the techniques described above may also be used to fabricate other FET structures, such as IGFET 200. IGFET200 illustratively includes a substrate 201 and a semiconductor layer 202 on the substrate. The hyperabrupt junction region 208 is located within the semiconductor layer 202 and extends partially into the substrate 201. The hyperabrupt junction region 208 illustratively includes a first semiconductor layer 212 having a first conductivity type (N or P), a first superlattice layer 225a on the first semiconductor layer, a second semiconductor layer 213 on the first superlattice layer and having a conductivity type (P or N) different from the first conductivity type, and a second superlattice layer 225b on the second semiconductor layer. Furthermore, the hyperabrupt junction region 208 is U-shaped and may be formed as a filled trench structure by successively depositing the above layers within a trench extending through the semiconductor layer 202 into the substrate 201.

Overlying the hyperabrupt junction region 208 is a drain extension region 230 and a dielectric layer 228. Furthermore, a gate electrode layer 215 overlies the dielectric layer 228 and is surrounded by the gate dielectric layer 214. The body region 233 surrounds the gate dielectric layer and defines a conductive channel 240 adjacent to the gate dielectric layer 232. Overlying the body region 233 is a source region 234 and overlying the source region and the gate are first and second

dielectric layers

235, 236. In addition, a source contact layer 237 (e.g., a semiconductor) may be formed over the top side of the device 200 (i.e., overlying the gate structure and the semiconductor layer 202), and a drain contact layer 238 (e.g., a metal layer) may be formed on the back side of the substrate 201.

Turning now to fig. 7, in accordance with another exemplary embodiment of IGFET200 ', hyperabrupt junction region 208' illustratively includes a single superlattice layer 225 '. More particularly, in this example, the hyperabrupt junction region 208' illustratively includes a first semiconductor layer 212' having a first conductivity type (N or P), a superlattice layer 225', a second semiconductor layer 213' having a second conductivity type (P or N) opposite the first conductivity type, and an optional intrinsic semiconductor layer 239 '. The remaining components of IGFET 200' may be similar to those described above with respect to fig. 6.

Turning now to the flow chart 130 of fig. 8 and 11, a varactor 300 incorporating a hyperabrupt junction layer 308 and associated method of fabrication are now described. The varactor 300 illustratively includes a substrate 301 having a cathode layer 302 and a collector layer 303 on the cathode layer. Beginning at block 131, a hyperabrupt junction region 308 can be grown on a collector layer 303 of a substrate 301 (block 132). More particularly, the hyperabrupt junction region 308 illustratively includes a first semiconductor layer 312 having a first conductivity type (P or N), a first superlattice 325a on the first semiconductor layer, a second semiconductor layer 313 on the first superlattice layer having a second conductivity type (N or P) different (i.e., opposite) from the first conductivity type, and a second superlattice layer 325b on the second semiconductor layer.

Further, at block 133, an anode region 340 and an associated metal layer 341 (i.e., a first contact) are formed on the hyperabrupt junction region 308. In addition, (block 134) a reach-through implant 342 and an associated metal layer 343 (i.e., a second contact) are also formed to contact the cathode layer 302 of the substrate 301 (it should be noted that this may instead be formed as a backside contact, if desired, in some embodiments). The punch-through implants 342 are laterally spaced from the hyperabrupt junction 308 and extend from the surface of the collector layer 303 to the cathode layer 302. More particularly, the reach-through implants 342 may have a conductivity type opposite to that of the cathode layer 302 and the collector layer 303, and the collector layer and the first semiconductor layer 312 may have the same conductivity type. Furthermore, an isolation region 311 (e.g., a dielectric) may be formed around the hyperabrupt junction region 308 and the reach-through implant 342. The method of fig. 11 ends at block 135.

Another similar varactor 330' is now described with reference to fig. 9A, in which the hyperabrupt junction 308' illustratively includes a single semiconductor layer 325 '. More particularly, the hyperabrupt junction 308' illustratively includes a first semiconductor layer 312', a superlattice 325', an intrinsic semiconductor layer 339', and a second semiconductor layer 340' (which also serves as an anode region). Yet another similar varactor 330 "is shown in fig. 9B, where all components are the same as in varactor 330', except that intrinsic layer 339" is below, rather than above, superlattice layer 325 ". The remaining components of the varactors 330', 330 "may be similar to those described above with respect to fig. 8.

Further details regarding JFET, IGFET and varactor structures may be found in U.S. patent nos. 7,825,441 to Eshun et al; U.S. publication No.2007/0278565 to Tu et al; and U.S. patent No.7,183,628 to Coolbaugh et al, which is hereby incorporated by reference in its entirety.

Many modifications and other embodiments of the invention will come to the mind of one skilled in the art having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the inventions are not to be limited to the specific embodiments disclosed and that modifications and embodiments are intended to be included within the scope of the appended claims.

Claims

1. A semiconductor device, comprising:

a substrate;

a hyperabrupt junction region carried by a substrate, comprising:

a first semiconductor layer having a first conductivity type,

a first superlattice layer on the first semiconductor layer,

a second semiconductor layer on the first superlattice layer and having a second conductivity type different from the first conductivity type, and

a second superlattice layer on the second semiconductor layer;

a gate dielectric layer on the second superlattice layer in the hyperabrupt junction region;

a gate electrode on the gate dielectric layer; and

spaced apart source and drain regions adjacent to the hyperabrupt junction region;

the first and second superlattices each comprise a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

2. The semiconductor device of claim 1, wherein the spaced apart source and drain regions are of the second conductivity type.

3. The semiconductor device according to claim 1, wherein the first and second semiconductor layers and the first and second superlattice layers are parallel to an underlying portion of the substrate.

4. The semiconductor device according to claim 1, wherein the first and second semiconductor layers and the first and second superlattice layers are U-shaped.

5. The semiconductor device according to claim 1, wherein the first semiconductor layer and the second semiconductor layer each have a thickness in a range of 50nm to 300 nm.

6. The semiconductor device of claim 1, wherein said base semiconductor monolayer comprises a silicon monolayer.

7. The semiconductor device of claim 1, wherein said at least one non-semiconductor monolayer comprises oxygen.

8. The semiconductor device of claim 1, wherein said base semiconductor monolayer comprises germanium.

9. The semiconductor device of claim 1, wherein said at least one non-semiconductor monolayer comprises at least one of oxygen, nitrogen, fluorine, carbon, and carbon-oxygen.

10. A method for manufacturing a semiconductor device, comprising:

forming a hyperabrupt junction region over a substrate, and including

A first semiconductor layer having a first conductivity type,

a first superlattice layer on the first semiconductor layer,

a second superlattice layer on the second semiconductor layer;

forming a gate dielectric layer on the second superlattice layer of the hyperabrupt junction region;

forming a gate electrode on the gate dielectric layer; and

forming spaced apart source and drain regions adjacent to the hyperabrupt junction region;

11. The method of claim 10 wherein the spaced apart source and drain regions are of the second conductivity type.

12. The method of claim 10, wherein the first and second semiconductor layers and the first and second superlattice layers are parallel to an underlying portion of the substrate.

13. The method of claim 10, wherein the first and second semiconductor layers and the first and second superlattice layers are U-shaped.

14. The method of claim 10, wherein the first and second semiconductor layers each have a thickness in a range of 50nm to 300 nm.

15. The method of claim 10 wherein the base semiconductor monolayer comprises a silicon monolayer.

16. The method of claim 10, wherein the at least one non-semiconductor monolayer comprises oxygen.

17. The method of claim 10 wherein the base semiconductor monolayer comprises germanium.

18. The method of claim 10, wherein the at least one non-semiconductor monolayer comprises at least one of oxygen, nitrogen, fluorine, carbon, and carbon-oxygen.