JP2009500874A - Semiconductor device including channel having non-semiconductor monolayer and method for manufacturing the same - Google Patents

Abstract

  The semiconductor device includes a semiconductor substrate and at least one MOSFET thereon. The MOSFET includes a source region and a drain region that are spatially separated, a channel between the source region and the drain region, and a gate located on the channel and defining an interface with the channel. The gate includes a gate dielectric overlying the channel and a gate electrode overlying the gate dielectric. The channel also includes a plurality of stacked base semiconductor monolayers and at least one non-semiconductor monolayer constrained within the crystal lattice of adjacent base semiconductor monolayers. The at least one non-semiconductor monolayer is positioned approximately 4-100 monolayers deep relative to the interface between the channel and the gate dielectric.

Description

  The present invention relates to the semiconductor field, and more specifically to a semiconductor with improved characteristics based on energy band engineering and a method for manufacturing the same.

  For example, a structure and a technique for improving the performance of a semiconductor device by increasing the mobility of charge carriers has been proposed. For example, Patent Document 1 discloses a strained material layer group including a region made of silicon, silicon germanium, and relaxed silicon, which may otherwise cause performance degradation, and also includes an impurity-free region. The biaxial strain obtained in the upper silicon layer changes the carrier mobility, allowing for faster and / or lower power devices. Patent Document 2 also discloses a CMOS inverter based on the same strained silicon technology.

  Patent Document 3 discloses a semiconductor device including a silicon and carbon layer sandwiched between silicon layers such that the conduction band and valence band of the second silicon layer are subjected to tensile strain. Electrons having a smaller effective mass induced by the electric field applied to the gate electrode are confined in the second silicon layer, thereby placing the n-channel MOSFET in a more mobile state.

  Patent Document 4 discloses a superlattice in which a single substance having a fraction of 8 atomic layers or less including a fraction or a plurality of layers which are binary compound semiconductor layers are alternately epitaxially grown. The direction of the main current is perpendicular to the superlattice layer group.

  Patent Document 5 discloses a Si—Ge short period superlattice in which higher mobility is realized by suppressing alloy scattering in the superlattice. In line with this policy, U.S. Pat. No. 6,057,049 includes a channel layer having a second metal and silicon alloy present in the silicon lattice at a rate that substantially places the channel layer under tensile stress. Discloses an improved MOSFET.

Patent Document 7 discloses a quantum well structure having two barrier regions and a thin epitaxially grown semiconductor layer sandwiched between the barrier regions. Each barrier region consists of alternating SiO ₂ / Si layers having a thickness generally in the range of 2 to 6 atomic layers. A much thicker silicon part is sandwiched between these barriers.

  Non-Patent Document 1 discloses a silicon-oxygen semiconductor-atomic superlattice (SAS). This Si / O superlattice is disclosed as being useful for silicon quantum light emitting devices. In particular, green electroluminescent diode structures have been prototyped and tested. The current in the diode structure is vertical, ie perpendicular to the SAS layer group. The disclosed SAS can include a group of semiconductor layers separated by absorbed species such as oxygen atoms and CO molecules. Silicon growth beyond the absorbed oxygen monolayer has been described as epitaxial with a fairly low defect density. One SAS structure includes a 1.1 nm thick silicon portion, which is approximately an 8-atomic layer of silicon, and another structure has twice this thickness of silicon. Non-Patent Document 2 further discusses the light-emitting SAS structure of Non-Patent Document 1.

  U.S. Pat. No. 6,057,077 discloses thin silicon and oxygen, carbon, nitrogen, phosphorus, antimony, arsenic, or hydrogen barrier building blocks that reduce the current flowing in the longitudinal direction of the lattice by more than four orders of magnitude. The insulating layer / barrier layer allows low defect epitaxial silicon to be deposited next to the insulating layer.

  U.S. Patent No. 6,057,031 discloses that the principle of an aperiodic photonic bandgap (APBG) structure can be applied to electronic bandgap engineering. In particular, this patent document 9 discloses that material parameters such as the position of the band minimum and effective mass can be adjusted to produce new aperiodic materials with desirable band structure characteristics. . It is disclosed that other parameters such as conductivity, thermal conductivity, and dielectric constant or permeability can also be designed into the material.

Despite considerable efforts in materials engineering to increase charge carrier mobility in semiconductor devices, still further improvements are desired. Higher mobility may speed up the device and / or reduce the power consumption of the device. Also, due to higher mobility, device performance can be maintained even with continued migration to even finer devices and new device configurations.
US Patent Application Publication No. 2003/057416 US Patent Application Publication No. 2003/034529 US Pat. No. 6,472,685 US Pat. No. 4,937,204 US Pat. No. 5,357,119 US Pat. No. 5,683,934 US Pat. No. 5,216,262 International Publication No. 02/103767 Brochure UK Patent Application No. 2347520 Tsu, “Phenomena in silicon nanostructure devices”, Applied Physics and Materials Science & Processing, September 6, 2000, p.391-402 Luo et al., “Chemical Design of Direct-Gap Light-Emitting Silicon”, Physical Review Letters, Vol. 89, No. 7, August 12, 2002

  In view of the above background, an object of the present invention is to provide a method for manufacturing a semiconductor device with improved operating characteristics.

  These and other objects, features and advantages in accordance with the present invention are provided by a semiconductor device including a semiconductor substrate and at least one metal oxide semiconductor field effect transistor (MOSFET) thereon. More specifically, the MOSFET includes a source region and a drain region that are spatially separated, a channel between the source region and the drain region, and a gate that is located on the channel and defines an interface with the channel. Contains. The gate includes a gate dielectric overlying the channel and a gate electrode overlying the gate dielectric. The channel also includes a plurality of stacked base semiconductor monolayers and at least one non-semiconductor monolayer constrained within the crystal lattice of adjacent base semiconductor monolayers. Further, the at least one non-semiconductor monolayer is positioned at a depth of approximately 4 to 100 monolayers relative to the interface between the channel and the gate dielectric.

  More specifically, the at least one non-semiconductor monolayer may be positioned at a depth of approximately 4 to 30 monolayers relative to the interface between the channel and the gate dielectric. Each base semiconductor monolayer may include a base semiconductor selected from the group consisting of a group IV semiconductor, a group III-V semiconductor, and a group II-VI semiconductor. As an example, each base semiconductor monolayer may include silicon.

  The at least one non-semiconductor monolayer may comprise a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen. The at least one non-semiconductor monolayer may include a single non-semiconductor monolayer. Further, adjacent base semiconductor monolayers on opposing surfaces of the at least one non-semiconductor monolayer may be chemically bonded.

  A method aspect is for manufacturing a semiconductor device. The method includes forming at least one metal oxide semiconductor field effect transistor (MOSFET) on a semiconductor substrate, the at least one MOSFET comprising a spatially separated source and drain region, and a source A channel between the region and the drain region; The channel has a plurality of stacked base semiconductor monolayers and at least one non-semiconductor monolayer constrained within the crystal lattice of adjacent base semiconductor monolayers. The MOSFET further includes a gate positioned over the channel and defining an interface with the channel, the gate including a gate dielectric positioned over the channel, and a gate electrode positioned over the gate dielectric. Have Furthermore, the at least one non-semiconductor monolayer is positioned at a depth of approximately 4 to 100 monolayers relative to the channel and gate dielectric interface.

  The present invention will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Throughout, similar reference numbers refer to similar elements, and one or more dash notation refers to similar elements in alternative embodiments.

  The present invention relates to controlling the properties of semiconductor materials at the atomic or molecular level to improve performance in semiconductor devices. Furthermore, the invention relates to the identification, creation and application of improved materials used in the conduction path of semiconductor devices.

Although not to be bound by theory, it is here theorized that certain superlattices described herein reduce the effective mass of charge carriers and thereby provide higher charge carrier mobility. To do. Effective mass is literally described using various definitions. As an indicator of effective mass improvement, here, for a "conductivity reciprocal effective mass tensor", ie, electrons and holes, respectively, Me _e ^-1 and M _h ^-1 are defined as follows: Use:
For electrons,

正孔に対して、

For holes,

ただし、fはフェルミ−ディラック分布関数、E_Fはフェルミ準位、Tは温度、E(ベクトルk,n)は波数ベクトルｋ及びｎ番目のエネルギー帯に対応する状態にある電子のエネルギーであり、添字i及びjはデカルト座標x、y及びzを参照するものである。また、積分はブリルアン領域（Ｂ．Ｚ．）全体で取られ、和は電子及び正孔に対して、それぞれ、フェルミ準位より高いエネルギー及び低いエネルギーを有するバンドの全体で取られる。

However, f is the Fermi - Dirac distribution function, E _F is the Fermi level, T is the temperature, E (vector k, n) electron energy in the state corresponding to wave vector k and the n th energy band, Subscripts i and j refer to Cartesian coordinates x, y and z. Also, the integral is taken over the entire Brillouin region (B.Z.), and the sum is taken over the entire band having energies above and below the Fermi level for electrons and holes, respectively.

  According to the definition of the conductivity inversion effective mass tensor here, the tensor component of the conductivity of the material increases as the value of the corresponding component of the conductivity inversion effective mass tensor increases. Again, not to be bound by theory, the superlattice described here is a value of the conductivity inversion effective mass tensor to enhance the conduction properties of the material, for example, typically in the preferred charge carrier transport direction. Theorizing that The reciprocal of the appropriate tensor element is called the conductivity effective mass. In other words, improved materials are identified by using the above-described electron / hole conductivity effective mass calculated in the intended carrier transport direction to characterize the structure of the semiconductor material.

  Using the above indicators, materials with improved band structures can be selected for specific purposes. One example is a strained superlattice 25 material for the channel region of a MOSFET device. First, a planar MOSFET 20 including a strained superlattice 25 according to the present invention will be described with reference to FIG. However, as will be appreciated by those skilled in the art, the materials identified herein can also be used in many different types of semiconductor devices such as, for example, discrete devices and / or integrated circuits. As an example, in another application, strained superlattice 25 may be used in a FINFET, as further described in US patent application Ser. No. 11 / 426,969. The entirety of this document is incorporated herein by reference.

  The illustrated MOSFET 20 includes a substrate 21, a stress layer 26 on the substrate, and semiconductor regions 27, 28 on the stress layer, with a strained superlattice layer 25 on the stress layer between the semiconductor regions. More specifically, the stress layer 26 may be a graded semiconductor layer, such as a graded silicon germanium layer. Further, the semiconductor regions 26, 27 can be, for example, silicon or silicon germanium regions. As will be appreciated by those skilled in the art, the semiconductor regions 26, 27 are illustratively ion implanted with dopants to form the source and drain regions 22, 23 of the MOSFET 20.

  Various superlattice structures that can be used in MOSFET 20 are further described. In the case of a silicon-oxygen superlattice, the lattice spacing of the superlattice layer 25 is typically smaller than the lattice spacing of the silicon germanium stress layer 26. However, the stress layer 26 in this example induces a tensile strain in the superlattice layer 25 that can be used to further increase mobility, for example, in an N-channel FET. In other examples, the composition of the superlattice layer 25 and the stress layer 26 may be selected so that the superlattice has a lattice spacing that is otherwise larger than the stress layer. This advantageously induces a compressive strain in the superlattice layer 25 that can effectively lead to further enhancement of the superlattice mobility, for example in P-channel FET devices.

  In the illustrated embodiment, the stress layer is a gradient semiconductor layer having a concentration gradient in the vertical direction, and a strained superlattice 25 is stacked in the vertical direction on the gradient semiconductor layer. In an alternative embodiment illustrated in FIG. 6, MOSFET 20 ′ further includes a substantially ungraded semiconductor layer 42 ′ disposed between graded semiconductor layer 26 ′ and strained superlattice layer 425 ′. Contains. That is, the substantially non-tilted semiconductor layer 42 ′ has a semiconductor material (eg, silicon germanium) having a substantially identical composition from the top to the bottom, and has a stress layer 26 ′ and a superlattice. Provide a buffer layer (buffer) between layers 425 '. More specifically, the substantially non-tilted semiconductor layer 42 'may have substantially the same composition as the semiconductor material at the top of the stress layer 26'. For more information on using graded and non-graded layers to strain an overlying semiconductor layer (eg, silicon), see Lei et al., US 2005/0211982, Bauer. US Patent Application Publication No. 2005/0054175, Lindert et al. US Patent Application Publication No. 2005/0224800, and Arena et al. US Patent Application Publication No. 2005/0051795. The entirety of these documents is incorporated herein by reference.

  As will be appreciated by those skilled in the art, by way of example, there are source / drain silicide layers 30, 31 and source / drain contacts 32, 33 over the source / drain regions 22, 23. The gate 35 illustratively includes a gate insulating layer 37 adjacent to the channel provided by the strained superlattice layer 25 and a gate electrode layer 36 on the gate insulating layer. In the illustrated MOSFET 20, side wall spacers 40 and 41 are also provided.

  It is also theorized that semiconductor devices, such as the illustrated MOSFET 20, for example, benefit from higher charge carrier mobility based on a lower conductivity effective mass than would otherwise exist. . In some embodiments, as a result of band engineering, the superlattice 25 is further described, for example, in co-pending US patent application Ser. No. 10/936903. Can have a substantial direct energy band gap that can be particularly advantageous for optoelectronic devices such as This document is incorporated herein in its entirety by reference.

  As will be appreciated by those skilled in the art, the source / drain regions 22, 23 and the gate 35 of the MOSFET 20 are oriented in a direction parallel to the group of stacked groups 45a-45n described below within the strained superlattice layer 25. It can be considered that this is a region that causes charge carrier transport. That is, the channel of the device is defined in the superlattice 25. Other such areas are also contemplated by the present invention.

  In certain embodiments, the superlattice 25 advantageously acts as an interface for the gate dielectric layer 37. For example, a channel region is defined in the lower part of the superlattice 25 (although part of the channel is also defined in the semiconductor material below the superlattice) and the upper part of the superlattice 25 is the channel. Is insulated from the dielectric layer 37. In yet another embodiment, the channel may be defined only within the stress layer 26 and the strained superlattice layer 25 may be included solely as an insulating / interface layer.

  The use of superlattice 25 as a dielectric interface layer can be particularly suitable when relatively high dielectric constant (high-k) gate dielectric materials are used. The superlattice 25 advantageously suppresses scattering and thus can provide a higher mobility than conventional insulating layers (eg, silicon oxide) commonly used for high-k dielectric interfaces. Furthermore, the use of superlattice 25 as an insulator applied with a high-k dielectric can result in a thinner overall thickness and thus improved device capacitance. Because, as further described in co-pending US patent application Ser. No. 11 / 136,881, superlattice 25 is formed with a relatively thin thickness, it still provides the desired insulating properties. Because you get. This document is incorporated herein in its entirety by reference.

  Applicants have identified an improved material or structure for the channel region of MOSFET 20. More specifically, a material or structure has been identified that has an energy band structure where the appropriate conductivity effective mass for electrons and / or holes is substantially less than the corresponding value of silicon.

  Referring also to FIGS. 2 and 3, this material or structure is in the form of a superlattice 25 whose structure is controlled at the atomic or molecular level and can be formed using known atomic or molecular layer deposition techniques. Superlattice 25 includes a plurality of layer groups 45a-45n arranged in a stacked relationship, perhaps as best understood with reference to the schematic cross-sectional view of FIG. An intermediate annealing process described in co-pending US patent application Ser. No. 11 / 136,834 is also used to effectively reduce defects during manufacturing and provide a smoother layer surface. obtain. The entirety of this document is incorporated herein by reference.

  Each of the layer groups 45a-45n of the superlattice 25 illustratively includes a plurality of stacked base semiconductor monolayers 46 defining respective base semiconductor portions 46a-46n and an energy band changing layer 50 thereon. Contains. The energy band changing layer 50 is shown as a dot pattern in FIG. 2 for the sake of clarity.

  The energy band changing layer 50 illustratively includes one non-semiconductor monolayer constrained within the crystal lattice of the adjacent base semiconductor portion. That is, the opposing base semiconductor monolayer groups in adjacent layer groups 45a-45n are chemically bonded. For example, in the case of the silicon monolayer 46, as shown in FIG. 3, some of the silicon atoms in the upper or top semiconductor monolayer of the monolayer group 46a are located in the lower or bottom monolayer of the group 46b. It is covalently bonded to the silicon atom. This allows the crystal lattice to continue across multiple layers regardless of the presence of non-semiconductor monolayers (eg, oxygen monolayers). Of course, as will be appreciated by those skilled in the art, between opposing silicon layers 46 of adjacent groups 45a-45n, some of the silicon atoms in each of these layers are non-semiconductor atoms (i.e., in this example). There will be no complete or pure covalent bond.

  In other embodiments, it is possible to include a plurality of such non-semiconductor monolayers. Note that the non-semiconductor or semiconductor monolayer referred to here means that if the material used for the monolayer is formed in a bulk shape, it becomes a non-semiconductor or semiconductor. That is, as will be appreciated by those skilled in the art, a single monolayer of material such as a semiconductor need not necessarily exhibit the same properties as when it is formed as a bulk or relatively thick layer.

  Although not to be bound by theory, here the superlattice 25 would otherwise exist for parallel charge carriers due to the energy band changing layer 50 and the adjacent base semiconductor portions 46a-46n. It is theorized to have a lower appropriate conductivity effective mass. From another viewpoint, the parallel direction is a direction perpendicular to the stacking direction. The energy band changing layer 50 may also have a common energy band structure for the superlattice 25.

  It is also theorized that semiconductor devices, such as the illustrated MOSFET 20, for example, benefit from higher charge carrier mobility based on a lower conductivity effective mass than would otherwise exist. . In some embodiments, as a result of the band engineering achieved by the present invention, the superlattice 25 further has a substantial direct energy band gap that can be particularly advantageous, for example, for optoelectronic devices as further described below. Can have. Of course, not all of the above properties of the superlattice 25 need be utilized in every application. For example, as will be appreciated by those skilled in the art, the superlattice 25 may be used only for dopant blocking / insulating properties, or improved mobility in some applications, and in other embodiments these may be used. It may be used for both.

  In some embodiments, multiple non-semiconductor monolayers may be present in the energy band changing layer 50. As an example, the number of non-semiconductor monolayers in the energy band changing layer 50 is preferably less than about 5 monolayers to obtain the desired energy band changing characteristics.

  The superlattice 25 also illustratively includes a cap layer 52 on the upper layer group 45n. The cap layer 52 may have a plurality of base semiconductor monolayers 46. The cap layer 52 may have a base semiconductor monolayer between 2 and 100 layers, more preferably between 10 and 50 layers.

  Each base semiconductor portion 46a-46n may comprise a base semiconductor selected from the group consisting of a group IV semiconductor, a group III-V semiconductor, and a group II-VI semiconductor. As will be appreciated by those skilled in the art, the term group IV semiconductor naturally includes group IV-IV semiconductors. More specifically, for example, the base semiconductor material may include at least one of silicon and germanium.

  Each energy band changing layer 50 may comprise a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine and carbon-oxygen. Also, the non-semiconductor is desirably thermally stable throughout the deposition of subsequent layers to facilitate manufacturing. In other embodiments, the non-semiconductor may have other inorganic or organic elements or compounds that are compatible with a given semiconductor process, as will be appreciated by those skilled in the art.

  The term monolayer includes a monoatomic layer and a monomolecular layer. Also, the energy band changing layer 50 provided by a single monolayer includes monolayers that do not occupy all possible sites, as described above. For example, referring to the atomic diagram of FIG. 3, a 4/1 repetitive structure is illustrated for silicon as the base semiconductor and oxygen as the energy band changing material. Only half of the possible sites for oxygen are occupied.

  In other embodiments and / or when using different materials, this half occupation is not necessarily true, as will be appreciated by those skilled in the art. In fact, even in this schematic, the individual oxygen atoms within a given monolayer are not precisely aligned along a flat surface, as will also be appreciated by those skilled in atomic deposition. By way of example, a suitable occupancy range is about 1/8 to 1/2 of the oxygen sites that can be satisfied, although other numbers may be used in certain embodiments.

  Since silicon and oxygen are now widely used in conventional semiconductor processes, manufacturers can easily use these materials as described herein. Atomic deposition or monolayer deposition is also widely used today. Accordingly, as will be appreciated by those skilled in the art, a semiconductor device incorporating a superlattice 25 can be readily employed and implemented.

  While not to be bound by theory, for a superlattice such as, for example, a Si / O superlattice, in order to achieve the desired benefits, it is desirable that the superlattice energy band be uniform or relatively uniform throughout. It is theorized that the number of silicon monolayers should be 7 or less. Of course, in some embodiments, more than 7 silicon layers may be used. To indicate that electron and hole mobility is increased in the X direction, the 4/1 repetitive structure for Si / O shown in FIGS. 2 and 3 was modeled. For example, the calculated electron conductivity effective mass (isotropic in bulk silicon) is 0.26 in the X direction of 0.26, 4/1 Si / O superlattice, giving a ratio of 0.46. Similarly, the calculation for holes was 0.36 for bulk silicon and 0.16 for 4/1 Si / O superlattice, giving a ratio of 0.44.

  While such direction-selective features are desirable in certain semiconductor devices, other devices may benefit from more uniformly increased mobility in any direction parallel to the layers. . As will be appreciated by those skilled in the art, it may also be beneficial to increase mobility for both electrons or holes, or only for one of these types of charge carriers.

  The reduced effective conductivity mass for the 4/1 Si / O superlattice 25 embodiment can be less than 2/3 of the effective conductivity mass that would occur without it, and this is This is true for both electrons and holes. Of course, as will be appreciated by those skilled in the art, the superlattice 25 may further include at least one conductivity type dopant. If the superlattice provides part or all of the channel, it may be particularly preferred to dope at least part of the superlattice 25. However, the superlattice 25 or portions thereof may also be left substantially undoped in some embodiments, as further described in US patent application Ser. No. 11 / 136,757. Good. The entirety of this document is incorporated herein by reference.

  Referring also to FIG. 4, a superlattice 25 'having different characteristics according to another embodiment according to the present invention will be described. In this embodiment, a 3/1/5/1 repeating pattern is shown. More specifically, the lowermost base semiconductor portion 46a 'has three monolayers, and the second lowermost base semiconductor portion 46b' has five monolayers. This pattern is repeated throughout the superlattice 25 '. Each of the energy band changing layers 50 'may include a single monolayer. For such a superlattice 25 'containing Si / O, the increase in charge carrier mobility is independent of the in-plane direction of the layer group. The components of FIG. 4 that are not specifically mentioned are similar to those described above with reference to FIG. 2, and need no further explanation here.

  In some device embodiments, all of the base semiconductor portions of the superlattice may be the same number of monolayer thicknesses. In other embodiments, at least a portion of the base semiconductor portion may be a different number of monolayer thicknesses. In yet other embodiments, all of the base semiconductor portions may have different numbers of monolayer thicknesses.

  5A-5C show band structures calculated using Density Functional Theory (DFT). It is well known in the art that DFT estimates the absolute value of the band gap low. Thus, all bands above the gap may be shifted by appropriate “scissors correction”. However, the band shape is known to be much more reliable. The energy on the vertical axis should be interpreted from this perspective.

  FIG. 5A shows the gamma point (both for the bulk silicon (represented by the solid line) and the 4/1 Si / O superlattice 25 (represented by the dotted line) shown in FIGS. 1-3. The band structure calculated from G) is shown. The direction refers to a 4/1 Si / O unit cell instead of the conventional Si unit cell, but the (001) direction in the figure corresponds to the (001) direction of the conventional Si unit cell. Therefore, the position of the minimum point of the expected conduction band of Si is shown. The (100) and (010) directions in the figure correspond to the (110) and (−110) directions of the conventional Si unit cell. As will be appreciated by those skilled in the art, the Si band on the figure is folded to represent a band on the appropriate reciprocal lattice direction of the 4/1 Si / O structure.

  Unlike the bulk silicon (Si), the minimum point of the conduction band of the 4/1 Si / O structure is at the gamma point, but the maximum point of the valence band is herein referred to as the Z point (001) direction. It can be seen that it occurs at the end of the Brillouin region. Also, the curvature of the minimum point of the conduction band of the 4/1 Si / O structure is compared with the curvature of the minimum point of the conduction band of Si due to band splitting due to perturbations introduced by the added oxygen layer. And big.

  FIG. 5B shows the band structure calculated from the Z point for both bulk silicon (solid line) and 4/1 Si / O superlattice 25 (dotted line). This figure illustrates the increase in curvature of the valence band in the (100) direction.

  FIG. 5C was calculated from both the gamma point and the Z point for both bulk silicon (solid line) and the 5/1/3/1 Si / O structure (dotted line) of the superlattice 25 ′ of FIG. The band structure is shown. Due to the symmetry of the 5/1/3/1 Si / O structure, the band structures calculated in the (100) and (010) directions are equal. Therefore, the effective conductivity mass and mobility are expected to be isotropic in a plane parallel to the layers, ie in a plane perpendicular to the (001) stacking direction. In the example of 5/1/3/1 Si / O, the minimum point of the conduction band and the maximum point of the valence band are both at or near the Z point.

  The increased curvature indicates that the effective mass has been reduced, and appropriate comparison and differentiation can be made by calculating the conductivity inversion effective mass tensor. This provides further theorization that the 5/1/3/1 superlattice 25 'is a substantial direct band gap. As will be appreciated by those skilled in the art, an appropriate matrix element for optical transitions is another indicator for distinguishing direct and indirect band gap behavior.

  Subsequently, with reference to FIGS. 7-9, MOSFETs 120, 220 and 320 according to further embodiments each including a strained superlattice layer will be described. In the illustrated embodiment, various layers and regions that are equivalent to those already described with reference to FIG. 1 are represented by reference numbers incremented by 100 (eg, in each of FIGS. 7-9, respectively). The substrates 121, 221 and 321 shown are equivalent to the substrate 21).

  In MOSFET 120, the stress layer is provided by a plurality of spatially separated strain-inducing pillars 144 arranged in side-by-side relationship on the back surface (ie, bottom) of substrate 121. As an example, if compressive strain is desired, the pillar 144 can be used during or after deposition in plasma-enhanced chemical vapor deposition (PECVD) silicon nitride (SiN), metal, or a trench etched in the backside of the substrate 121. Other materials to be compressed may be included. Also, if tensile strain is desired, the pillar may include, for example, a thermally formed SiN material or a SiN material by low pressure chemical vapor deposition (LPCVD). Of course, other suitable materials known to those skilled in the art may be used. Further details on backside strain-inducing pillar structures are described in Pelella et al., US Patent Application Publication No. 2005/0263353. The entirety of this document is incorporated herein by reference.

Further, an insulating layer 143 (shown by a hatched region for clarity of illustration) such as a SiO ₂ layer may be disposed between the stress layer and the strained superlattice layer 125. This insulating layer is intended to provide a semiconductor-on-insulator embodiment as shown, but need not be used in all embodiments. Further details on forming such a superlattice structure on a semiconductor-on-insulator substrate are presented in co-pending US patent application Ser. No. 11 / 38,835. The entirety of this document is incorporated herein by reference. Of course, the semiconductor-on-insulator implementation may also be used in other embodiments described herein.

  Referring to FIG. 8, regions 227 and 228 in MOSFET 220 define a pair of spatially separated stress regions for inducing strain in superlattice layer 225 located therebetween. More specifically, one or both of these stress regions includes a material that induces a desired strain in superlattice layer 225. Using the example described above for the silicon-oxygen superlattice layer 225, one or both of the regions 227, 228 may include silicon germanium. In the MOSFET 20, silicon germanium is placed under the superlattice layer 25 to induce tensile strain, but when placed on one or both sides of the superlattice layer 225, silicon germanium has the opposite effect and causes the superlattice to Compress.

  Therefore, in the illustrated embodiment, silicon germanium in the stress regions 227, 228 induces compressive strain, which is advantageous for the P-channel type implementation. In another example, tensile strain can be effectively induced in the superlattice layer 225 of the N-channel device by appropriately selecting the composition of the superlattice and stress regions 227 and 228 as described above. is there. It should be noted that in some embodiments, the spatially separated stress regions 227, 228 need not include the same material. That is, strain may be induced when one stress region “pushes” or “pulls” against the other acting as an anchor.

  In the embodiment described above, the pair of stress regions 227, 228 is doped to provide source and drain regions 222, 223. Further, the stress regions 227, 228 illustratively include beveled surfaces or facets 245, 246 adjacent to opposite portions of the strained superlattice. The beveled surfaces 245, 246 are obtained by patterning the superlattice 225 using an etching process, whereby stress-inducing material is deposited adjacent to the superlattice. However, the surfaces 245, 246 need not be beveled in all embodiments. Further details on forming strained channel devices with strain-induced source and drain regions can be found in Yu et al. US Pat. No. 6,495,402 and Lindert et al. US Pat. App. Pub. No. 2005/0142768. It is disclosed. All of these documents are incorporated herein by reference in their entirety.

  Referring to FIG. 9, MOSFET 320 illustratively includes a stress layer 347 above strained superlattice layer 325. This stress layer can be, for example, a SiN layer that is deposited over the source, drain, and gate regions of MOSFET 320 and induces strain in the underlying semiconductor material including superlattice layer 325. As noted above, tensile or compressible nitride materials can be used depending on the type of strain desired for the superlattice layer 325. Of course, other suitable materials may be used for the stress layer 347, and in some embodiments, multiple stress layers may be used. Also, as will be appreciated by those skilled in the art, in certain embodiments, the superlattice layer 325 may “remember” the strain induced by the overlying stress layer 347, after which the stress layer It may be removed. For further details on creating strain in a semiconductor region using an overlying stress layer, see Chau et al. US Patent Application Publication No. 2005/0145894 and Sun et al. US Patent Application Publication No. 2005/0247926. It is described in the specification. All of these documents are incorporated herein by reference in their entirety.

  Subsequently, aspects of the first method according to the present invention for manufacturing a semiconductor device such as MOSFET 20 will be described. The method includes forming a stress layer 26 and forming a strained superlattice layer 25 on the stress layer. Another method aspect is for manufacturing a semiconductor device, such as MOSFET 220, for example, forming a superlattice layer 225, and forming a superlattice layer to induce strain in the superlattice layer. Forming at least a pair of spatially separated stress regions 227, 228 on opposite sides. Yet another method aspect is for manufacturing a semiconductor device, such as MOSFET 320, for example, forming a superlattice layer 325, and strained superlattice to induce strain in the superlattice layer. Forming a stress layer 347 above the layer. Since the above description recognizes various other method steps and aspects to those skilled in the art, no further description is required here.

  In the above-described embodiment, the strained layer is not necessarily the superlattice 25. Rather, the strained layer is simply a plurality of base semiconductor portions 46a-46n and one or more non-semiconductor monolayers 50 (ie, as described above, contiguous within the crystal lattice of adjacent base semiconductor portions). The matching base semiconductor portion may include chemically bonded). In this embodiment, the base semiconductor portions 46a-46n need not include multiple semiconductor monolayers. That is, each semiconductor portion can include, for example, a single layer or multiple monolayers.

  FIG. 10 schematically shows a MOSFET 80 that illustratively includes a non-semiconductor monolayer 81. The semiconductor monolayer is in portions 82a, 82b that are respectively below and above the non-semiconductor monolayer. A gate dielectric 83 is illustrated on the channel 85 and a gate electrode 84 is on the gate dielectric. The region between the lower portion of gate dielectric 83 and the upper portion of channel 85 defines interface 86. As will be appreciated by those skilled in the art, the source and drain (not shown) are laterally adjacent to the channel 85.

  The depth of the monolayer 81 of non-semiconductor material from the interface 86 can be selected based on the design of the MOSFET, as will be appreciated by those skilled in the art. For example, in a typical MOSFET for an oxygen layer in a silicon channel, a depth of approximately 4-100 monolayers, more preferably a depth of 4-30 monolayers, can be selected. The at least one monolayer of non-semiconductor material may include one or more monolayers, as described above, where not all possible sites are fully occupied.

  As described above, the non-semiconductor can be selected from the group consisting of, for example, oxygen, nitrogen, fluorine, and carbon-oxygen. The at least one monolayer of non-semiconductor material 81 can also be deposited using, for example, atomic layer deposition techniques, as described above and as will be appreciated by those skilled in the art. Other deposition and / or ion implantation methods may be used to form the channel 85 to include at least one non-semiconductor material layer 81 within the crystal lattice of adjacent semiconductor layer groups 82a, 82b. .

  A simulation result 90 of the density at the interface with respect to the depth of the oxygen layer in angstrom units is plotted in FIG. As will be appreciated by those skilled in the art, in embodiments such as the illustrated MOSFET 80, repetitive superlattice groups need not be used, and even at least one non-semiconductor monolayer 81 can provide improved mobility. Can bring. Also, not to be bound by theory, it is theorized that these embodiments also have lower tunnel gate leakage as a result of the reduced wave function amplitude at interface 86. It is theorized that further desirable features of these embodiments include increased energy separation between subbands and spatial separation of subband groups, thereby suppressing subband scattering.

  Of course, in other embodiments, at least one monolayer 81 may be used in combination with the underlying superlattice, as will be appreciated by those skilled in the art. Those skilled in the art who have benefited from the teachings presented in the foregoing description and the accompanying drawings will envision numerous modifications and other embodiments of the invention. Accordingly, the invention is not limited to the specific embodiments disclosed herein, but such modifications and embodiments are intended to be included within the scope of the appended claims.

1 is a cross-sectional view schematically illustrating a semiconductor device according to the present invention including a stress layer and a strained superlattice thereon. FIG. It is sectional drawing which expands and shows the superlattice shown by FIG. 1 greatly. FIG. 2 is a perspective view of an atomic arrangement showing a part of the superlattice shown in FIG. 1. FIG. 2 is a cross-sectional view, greatly enlarged, illustrating another embodiment of a superlattice that can be used in the device of FIG. 1. 4 is a graph showing the calculated band structure from the gamma point (G) for both the prior art bulk silicon and the 4/1 Si / O superlattice shown in FIGS. 1-3. FIG. FIG. 4 is a graph showing the calculated band structure from the Z point for both prior art bulk silicon and the 4/1 Si / O superlattice shown in FIGS. 1-3. FIG. 5 is a graph showing the calculated band structure from both the gamma point and the Z point for both the prior art bulk silicon and the 5/1/3/1 Si / O superlattice shown in FIG. . FIG. 2 is a cross-sectional view schematically illustrating an alternative embodiment of the semiconductor device of FIG. FIG. 2 is a cross-sectional view schematically illustrating an alternative embodiment of the semiconductor device of FIG. FIG. 6 is a cross-sectional view schematically illustrating one embodiment of another semiconductor device according to the present invention, including a superlattice between a pair of spatially separated stress regions. FIG. 6 is a cross-sectional view schematically illustrating one embodiment of still another semiconductor device according to the present invention, including a superlattice and a stress layer thereon. 1 is a cross-sectional view schematically illustrating a MOSFET including a non-semiconductor monolayer according to the present invention. FIG. 11 is a graph plotting density at the simulated interface versus depth for the non-semiconductor monolayer of FIG.

Claims (16)

A semiconductor substrate; and at least one MOSFET thereon;
Spatially separated source and drain regions,
A channel between the source region and the drain region, comprising a plurality of stacked base semiconductor monolayers and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor monolayers; A gate located above the channel and defining an interface with the channel, the gate having a gate dielectric located on the channel and a gate electrode located on the gate dielectric;
A MOSFET having
A semiconductor device having:
The semiconductor device, wherein the at least one non-semiconductor monolayer is positioned at a depth of approximately 4 to 100 monolayers relative to an interface between the channel and the gate dielectric.   The semiconductor device of claim 1, wherein the at least one non-semiconductor monolayer is positioned at a depth of approximately 4 to 30 monolayers relative to an interface between the channel and the gate dielectric. .   The semiconductor device of claim 1, wherein each base semiconductor monolayer comprises silicon.   The semiconductor device of claim 1, wherein each base semiconductor monolayer comprises a base semiconductor selected from the group consisting of a group IV semiconductor, a group III-V semiconductor, and a group II-VI semiconductor.   The semiconductor device of claim 1, wherein the at least one non-semiconductor monolayer comprises oxygen.   The semiconductor device of claim 1, wherein the at least one non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.   The semiconductor device of claim 1, wherein adjacent base semiconductor monolayers on opposite sides of the at least one non-semiconductor monolayer are chemically bonded.   The semiconductor device of claim 1, wherein the at least one non-semiconductor monolayer comprises a single non-semiconductor monolayer. On the semiconductor substrate,
Spatially separated source and drain regions,
A channel between the source region and the drain region, comprising a plurality of stacked base semiconductor monolayers and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor monolayers; A gate located above the channel and defining an interface with the channel, the gate having a gate dielectric located on the channel and a gate electrode located on the gate dielectric;
Forming at least one MOSFET having:
A method for manufacturing a semiconductor device comprising:
The method wherein the at least one non-semiconductor monolayer is positioned at a depth of approximately 4 to 100 monolayers relative to an interface between the channel and the gate dielectric.   The method of claim 9, wherein the at least one non-semiconductor monolayer is positioned at a depth of approximately 4 to 30 monolayers relative to an interface between the channel and the gate dielectric.   The method of claim 9, wherein each base semiconductor monolayer comprises silicon.   The method of claim 9, wherein each base semiconductor monolayer comprises a base semiconductor selected from the group consisting of a group IV semiconductor, a group III-V semiconductor, and a group II-VI semiconductor.   The method of claim 9, wherein the at least one non-semiconductor monolayer comprises oxygen.   The method of claim 9, wherein the at least one non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.   The method of claim 9, wherein adjacent base semiconductor monolayers on opposite sides of the at least one non-semiconductor monolayer are chemically bonded.   The method of claim 9, wherein the at least one non-semiconductor monolayer comprises a single non-semiconductor monolayer.

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