CN113871459B

CN113871459B - Superlattice very large scale integrated circuit

Info

Publication number: CN113871459B
Application number: CN202111131217.2A
Authority: CN
Inventors: 林和
Original assignee: Individual
Current assignee: Individual
Priority date: 2019-05-06
Filing date: 2019-05-06
Publication date: 2023-09-12
Anticipated expiration: 2039-05-06
Also published as: CN113871461A; CN110085665B; CN113871458B; CN113871457B; CN113871461B; CN113871459A; CN113871457A; CN113871458A; CN113871460A; CN110085665A; CN113871460B

Abstract

The invention provides a superlattice ultra-large scale integrated circuit, which comprises: a substrate; a transition layer disposed over the substrate; and the component layer is arranged above the transition layer, and the component layer is a device designed by utilizing the special performance based on the two-dimensional electron gas and the two-dimensional hole gas of the superlattice integrated circuit to construct the superlattice integrated circuit. The super-lattice integrated circuit is built by utilizing a device designed based on the special performance of the two-dimensional electron gas and the two-dimensional hole gas of the super-lattice integrated circuit above the transition layer, and the super-lattice super-large scale integrated circuit (MDMFSL-ULSI: multi-Dimension Multi-Functional Superlattice Ultra-Large Scale Integrated Circuit) is designed based on the super-lattice and the quantum well of the two-dimensional electron gas and the two-dimensional hole gas and has the characteristics of ultrahigh speed, high reliability, radiation resistance, high temperature resistance, low temperature resistance and the like, and has the advantages of high design efficiency, short manufacturing process period and low cost, and greatly improves the defects of the traditional silicon and compound integrated circuit.

Description

Superlattice very large scale integrated circuit

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a superlattice ultra-large scale integrated circuit.

Background

At present, very large scale integrated circuit components and processes based on silicon materials are approaching quantum limit, not only the device performance is limited, but also the manufacturing process is very complex and the manufacturing cost is high. High-speed development of large data, artificial intelligence and comprehensive data intelligent markets are in urgent need of novel very large scale integrated circuits with high reliability and acceptable cost. More importantly, silicon very large scale integrated circuit components are increasingly difficult to meet the special requirements of artificial intelligence and space age on ultra-high speed, high and low temperature resistance, radiation resistance and the like.

Disclosure of Invention

The invention provides a super-lattice super-large scale integrated circuit (MDMFSL-ULSI: multi-Dimension Multi-Functional Superlattice Ultra-Large Scale Integrated Circuit), which is based on a two-dimensional electron gas and two-dimensional hole gas super lattice and a quantum well, has the characteristics of super-high speed, high reliability, radiation resistance, high temperature resistance and the like, has high design efficiency, short manufacturing process period and low cost, and greatly improves the defects of the traditional silicon and compound integrated circuit.

The invention provides a superlattice very large scale integrated circuit, comprising:

a substrate;

a transition layer disposed over the substrate;

And the component layer is arranged above the transition layer, and the component layer is used for constructing the superlattice integrated circuit by utilizing a device designed based on the special performance of the two-dimensional electron gas and the two-dimensional hole gas of the superlattice integrated circuit. The component layer can be constructed by a homogeneous superlattice layer, such as intrinsic gallium nitride (GaN), N-type gallium nitride (GaN), P-type gallium nitride (GaN) and the like, or a heterogeneous superlattice layer, such as intrinsic gallium aluminum nitride Ga (x) Al (1-x) N, N-type gallium aluminum nitride Ga (x) Al (1-x) N, P-type gallium aluminum nitride Ga (x) Al (1-x) N and the like.

In one embodiment, the substrate is silicon, germanium or a compound semiconductor.

In one embodiment, the transition layer is one of silicon dioxide, silicon nitride and a compound semiconductor layer.

In one embodiment, the component layer is a device designed to utilize the special properties of two-dimensional electron gas and two-dimensional hole gas based on the superlattice integrated circuit to construct the superlattice integrated circuit.

In one embodiment, the devices designed based on the specific properties of the two-dimensional electron gas and the two-dimensional hole gas of the superlattice integrated circuit include one or more of P-type superlattice field effect transistors, N-type superlattice field effect transistors, NPN-type superlattice bipolar transistors, PNP-type superlattice bipolar transistors, superlattice flash memories, superlattice capacitors and varactors, superlattice resistors and varistors, and superlattice inductors and varistors.

In one embodiment, the substrate bottom is uniformly distributed with a plurality of through holes.

The multidimensional structure of the superlattice ultra-large scale integrated circuit isolates each special functional block by a channel insulating layer according to the requirement of device performance and adopts special processes (such as ion implantation, rapid high temperature thermal annealing and the like) to form a plurality of carrier (electron or hole) channels.

In one embodiment, an N-type superlattice field effect transistor includes:

the first superlattice intrinsic layer is arranged above the transition layer;

a superlattice N-type layer disposed above the first superlattice intrinsic layer;

a second superlattice intrinsic layer disposed above the superlattice N-type layer;

a first superlattice P-type layer disposed above the second superlattice intrinsic layer;

the first grid insulation layer is arranged above the first superlattice P-type layer;

the first N+ conductive layer penetrates downwards from the upper surface of the first superlattice P-type layer to the lower surface of the first superlattice intrinsic layer in a direction perpendicular to the first superlattice P-type layer;

the first channel insulating layer is annular, penetrates downwards from the upper surface of the first superlattice P-type layer to the lower surface of the first superlattice intrinsic layer in the direction perpendicular to the first superlattice P-type layer, and the first N+ conducting layer is arranged in the first channel insulating layer;

A first ohmic contact layer disposed over and in contact with the first n+ conductive layer;

a second ohmic contact layer disposed over and in contact with the first gate insulating layer,

a first dielectric protection layer disposed between the first ohmic contact layer and the second ohmic contact layer;

and the second dielectric protection layer is arranged outside the first ohmic contact layer.

The device configuration described above is only a simple combination of many combinations of N-type superlattice field effect transistors.

In one embodiment, a P-type superlattice field effect transistor includes:

the third superlattice intrinsic layer is arranged above the transition layer;

a superlattice P-type layer disposed above the third superlattice intrinsic layer;

a fourth superlattice intrinsic layer disposed above the superlattice P-type layer;

the first superlattice N-type layer is arranged above the fourth superlattice intrinsic layer;

the second grid insulating layer is arranged above the first superlattice N-type layer;

the first P+ conducting layer penetrates downwards from the upper surface of the first superlattice N-type layer to the lower surface of the third superlattice intrinsic layer in a direction perpendicular to the first superlattice N-type layer;

A second channel insulating layer of a desired shape for device isolation, comprising: rectangular, annular, etc. closed shapes. The first P+ conducting layer is arranged in the second channel insulating layer;

a third ohmic contact layer disposed over and in contact with the first p+ conductive layer;

a fourth ohmic contact layer disposed over and in contact with the second gate insulating layer,

a third dielectric protection layer disposed between the third ohmic contact layer and the fourth ohmic contact layer;

and a fourth dielectric protection layer arranged outside the third ohmic contact layer.

The above device configuration is only one simple combination of the various combinations of P-type superlattice field effect transistors.

In one embodiment, PNP superlattice bipolar transistors are classified into superlattice planar type P-N-P bipolar transistors and superlattice vertical type P-N-P bipolar transistors;

wherein the superlattice vertical type P-N-P bipolar transistor comprises:

the superlattice collector P-type layer is arranged above the transition layer;

The superlattice base N-type layer is arranged above the superlattice collector P-type layer;

the superlattice emitter P-type layer is arranged above the superlattice base N-type layer;

the second P+ conductive layer and the second N+ conductive layer penetrate downwards from the upper surface of the superlattice emitter P-type layer to the lower surface of the superlattice collector P-type layer in a direction perpendicular to the superlattice emitter P-type layer;

a third channel insulating layer having a shape required for device isolation, such as a rectangle, a ring, etc.; the second P+ conducting layer and the second N+ conducting layer are arranged in the third channel insulating layer;

a fifth ohmic contact layer disposed over and in contact with the second p+ conductive layer;

a sixth ohmic contact layer disposed over and in contact with the second n+ conductive layer;

a seventh ohmic contact layer disposed over and in contact with the superlattice emitter P-type layer,

a fifth dielectric protection layer disposed between the seventh and fifth ohmic contact layers, and the seventh and sixth ohmic contact layers;

And a sixth dielectric protection layer, wherein the fifth ohmic contact layer and the outer side of the sixth ohmic contact layer are arranged.

A seventh dielectric protection layer disposed between the superlattice emitter P-type layer and the second n+ conductive layer, the superlattice emitter P-type layer and the second p+ conductive layer;

wherein the superlattice planar P-N-P bipolar transistor comprises:

the superlattice planar P-N-P bipolar transistor includes:

the superlattice emitter P-type region is cylindrical and is arranged above the transition layer;

the superlattice base N-type region 46 is annular, is arranged above the transition layer and is sleeved outside the superlattice emitter P-type region;

the superlattice collector P-type region is annular, is arranged above the transition layer and is sleeved outside the superlattice base N-type region 46;

the fourth channel insulating layer is annular and sleeved outside the P-type region of the superlattice base electrode, and is arranged above the transition layer or arranged above the transition layer and embedded into the substrate after penetrating through the transition layer;

the eighth ohmic contact layer is round, is arranged above the superlattice emitter P-type region and is in contact with the superlattice emitter P-type region;

The ninth ohmic contact layer is annular, is arranged above the superlattice base N-type region 46 and is in contact with the superlattice base N-type region 46;

the tenth ohmic contact layer is annular, is arranged above the superlattice collector P-type region and is in contact with the superlattice collector P-type region;

an eighth dielectric protection layer which is annular and is arranged between the eighth ohmic contact layer and the ninth ohmic contact layer;

a ninth dielectric protection layer which is annular and is arranged between the ninth ohmic contact layer and the tenth ohmic contact layer;

and the tenth dielectric protection layer is annular and is arranged outside the tenth ohmic contact layer.

In one embodiment, NPN superlattice bipolar transistors are classified into superlattice vertical type N-P-N bipolar transistors and superlattice planar type N-P-N bipolar transistors;

wherein the superlattice vertical type N-P-N bipolar transistor comprises:

the superlattice collector N-type layer is arranged above the transition layer;

the superlattice base P-type layer is arranged above the superlattice collector N-type layer;

the superlattice emitter N-type layer is arranged above the superlattice base P-type layer;

a third p+ conductive layer and a third n+ conductive layer penetrating from the upper surface of the superlattice emitter N-type layer downward to the lower surface of the superlattice collector N-type layer in a direction perpendicular to the superlattice emitter N-type layer;

A fifth channel insulating layer having a shape required for device isolation, such as a rectangle, a ring, etc., penetrating downward from the upper surface of the superlattice emitter N-type layer to the lower surface of the superlattice collector N-type layer in a direction perpendicular to the superlattice emitter N-type layer, wherein the third p+ conductive layer and the third n+ conductive layer are disposed in the fifth channel insulating layer;

an eleventh ohmic contact layer disposed over and in contact with the third p+ conductive layer;

a twelfth ohmic contact layer disposed over and in contact with the third n+ conductive layer;

a thirteenth ohmic contact layer disposed over and in contact with the superlattice emitter N-type layer,

an eleventh dielectric protection layer disposed between the thirteenth and eleventh ohmic contact layers, the thirteenth and twelfth ohmic contact layers;

and a twelfth dielectric protection layer arranged outside the eleventh ohmic contact layer and the twelfth ohmic contact layer.

A thirteenth dielectric protection layer disposed between the superlattice emitter N-type layer and the third n+ conductive layer, the superlattice emitter N-type layer and the third p+ conductive layer;

Wherein the superlattice planar type N-P-N bipolar transistor comprises:

the superlattice emitter N-type region is cylindrical and is arranged above the transition layer;

the superlattice base electrode P-type region is annular, is arranged above the transition layer and is sleeved outside the superlattice emitter electrode N-type region;

the superlattice collector N-type region is annular, is arranged above the transition layer and is sleeved outside the superlattice base P-type region;

the sixth channel insulating layer is annular and sleeved outside the N-type region of the superlattice collector, and is arranged above the transition layer or arranged above the transition layer and embedded into the substrate after penetrating through the transition layer;

the fourteenth ohmic contact layer is round, is arranged above the superlattice emitter N-type region and is in contact with the superlattice emitter N-type region;

the fifteenth ohmic contact layer is annular, is arranged above the superlattice base electrode P-type region and is in contact with the superlattice base electrode P-type region;

the sixteenth ohmic contact layer is annular, is arranged above the superlattice collector N-type region and is in contact with the superlattice collector N-type region;

a fourteenth dielectric protective layer, which is annular and is arranged between the fourteenth ohmic contact layer and the fifteenth ohmic contact layer;

A fifteenth dielectric protective layer which is annular and is arranged between the fifteenth ohmic contact layer and the sixteenth ohmic contact layer;

the sixteenth dielectric protection layer is annular and is arranged outside the sixteenth ohmic contact layer.

In one embodiment, the superlattice capacitor and varactor includes:

a fifth superlattice intrinsic layer disposed above the transition layer;

a second superlattice P-type layer disposed above the fifth superlattice intrinsic layer;

a sixth superlattice intrinsic layer disposed above the second superlattice P-type layer;

the first superlattice low-resistance N-type layer is arranged above the sixth superlattice intrinsic layer;

the fourth P+ conductive layer and the fourth N+ conductive layer penetrate downwards from the upper surface of the first superlattice low-resistance N-type layer to the lower surface of the fifth superlattice intrinsic layer in a direction perpendicular to the first superlattice low-resistance N-type layer;

a seventh channel insulating layer having a shape required for device isolation, such as a rectangle, a ring, etc., penetrating downward from the upper surface of the first superlattice low-resistance N-type layer to the lower surface of the fifth superlattice intrinsic layer in a direction perpendicular to the first superlattice low-resistance N-type layer, wherein the fourth p+ conductive layer and the fourth n+ conductive layer are disposed in the seventh channel insulating layer;

A seventeenth ohmic contact layer disposed over and in contact with the first superlattice low-resistance N-type layer;

an eighteenth ohmic contact layer disposed over and in contact with the fourth n+ conductive layer;

a nineteenth ohmic contact layer disposed over and in contact with the fourth p+ conductive layer;

a seventeenth dielectric protective layer disposed between the seventeenth and eighteenth ohmic contact layers, the seventeenth and nineteenth ohmic contact layers;

an eighteenth dielectric protection layer is arranged outside the eighteenth ohmic contact layer and the nineteenth ohmic contact layer.

In one embodiment, the superlattice resistor and varistor includes:

a seventh superlattice intrinsic layer disposed above the transition layer;

a third superlattice P-type layer disposed over the seventh superlattice intrinsic layer;

an eighth superlattice intrinsic layer disposed above the third superlattice P-type layer;

the second superlattice low-resistance N-type layer is arranged above the eighth superlattice intrinsic layer;

the fifth P+ conductive layer and the fifth N+ conductive layer penetrate downwards from the upper surface of the second superlattice low-resistance N-type layer to the lower surface of the seventh superlattice intrinsic layer in a direction perpendicular to the second superlattice low-resistance N-type layer;

An eighth channel insulating layer having a shape required for device isolation, such as a rectangle, a ring, etc., penetrating downward from the upper surface of the second superlattice low-resistance N-type layer to the lower surface of the seventh superlattice intrinsic layer in a direction perpendicular to the second superlattice low-resistance N-type layer, wherein the fifth p+ conductive layer and the fifth n+ conductive layer are disposed in the eighth channel insulating layer;

a twenty-first ohmic contact layer, a twenty-second ohmic contact layer, and a twenty-first ohmic contact layer;

the twenty-first ohmic contact layer is arranged above the first superlattice low-resistance N-type layer and is in contact with the first superlattice low-resistance N-type layer;

a twenty-first ohmic contact layer disposed over and in contact with the fifth n+ conductive layer;

a twenty-second ohmic contact layer disposed over and in contact with the fifth p+ conductive layer;

a nineteenth dielectric protective layer disposed between the twenty-first ohmic contact layer and the twenty-first ohmic contact layer, and the twenty-second ohmic contact layer;

and a twenty-first ohmic contact layer and a twenty-second ohmic contact layer are arranged outside the twenty-first dielectric protective layer.

In one embodiment, the superlattice inductor and the inductor include:

a ninth superlattice intrinsic layer disposed above the transition layer;

a fourth superlattice P-type layer disposed above the ninth superlattice intrinsic layer;

a tenth superlattice intrinsic layer disposed above the fourth superlattice P-type layer;

the third superlattice low-resistance N-type layer is arranged above the tenth superlattice intrinsic layer;

the sixth P+ conductive layer and the sixth N+ conductive layer penetrate downwards from the upper surface of the third superlattice low-resistance N-type layer to the lower surface of the ninth superlattice intrinsic layer in a direction perpendicular to the third superlattice low-resistance N-type layer;

a ninth channel insulating layer having a shape required for device isolation, such as a rectangle, a ring, etc., penetrating downward from the upper surface of the third superlattice low-resistance N-type layer to the lower surface of the ninth superlattice intrinsic layer in a direction perpendicular to the third superlattice low-resistance N-type layer, the sixth p+ conductive layer and the sixth n+ conductive layer being disposed in the ninth channel insulating layer;

a twenty-third ohmic contact layer, a twenty-fourth ohmic contact layer, and a twenty-fifth ohmic contact layer, which are a group, and two groups;

A twenty-third ohmic contact layer disposed over and in contact with the third superlattice low-resistance N-type layer;

a twenty-fourth ohmic contact layer disposed over and in contact with the sixth n+ conductive layer;

a twenty-fifth ohmic contact layer disposed over and in contact with the sixth p+ conductive layer;

a twenty-first dielectric protective layer disposed between the twenty-third and twenty-fourth ohmic contact layers, the twenty-third and twenty-fourth ohmic contact layers;

and a twenty-second dielectric protective layer, wherein the twenty-fourth ohmic contact layer and the twenty-fifth ohmic contact layer are arranged outside.

In one embodiment, a superlattice flash memory includes: the method comprises the steps of doping a P channel N-i-P-i superlattice field effect ferroelectric transistor or doping an N channel N-i-P-i superlattice field effect ferroelectric transistor;

wherein the P-channel n-i-P-i superlattice field effect ferroelectric transistor comprises:

an eleventh superlattice intrinsic layer disposed above the transition layer;

a superlattice low-resistance P-type layer disposed above the eleventh superlattice intrinsic layer;

a twelfth superlattice intrinsic layer disposed above the superlattice low-resistance P-type layer;

A second superlattice N-type layer disposed above the twelfth superlattice intrinsic layer;

the first ferroelectric film layer is arranged above the second superlattice N-type layer;

a seventh p+ conductive layer penetrating from the upper surface of the second superlattice N-type layer and downward to the lower surface of the eleventh superlattice intrinsic layer in a direction perpendicular to the second superlattice N-type layer;

a tenth channel insulating layer having a shape required for device isolation, such as a rectangle, a ring, etc., penetrating downward from the upper surface of the second superlattice N-type layer to the lower surface of the eleventh superlattice intrinsic layer in a direction perpendicular to the second superlattice N-type layer, the seventh p+ conductive layer being disposed in the tenth channel insulating layer;

a twenty-sixth ohmic contact layer disposed over and in contact with the first ferroelectric thin film layer,

a twenty-seventh ohmic contact layer disposed over and in contact with the seventh p+ conductive layer;

a twenty-third dielectric protective layer disposed between the twenty-sixth ohmic contact layer and the twenty-seventh ohmic contact layer;

a twenty-fourth dielectric protective layer disposed outside the twenty-seventh ohmic contact layer;

Wherein the N-channel N-i-p-i superlattice field effect ferroelectric transistor comprises:

a thirteenth superlattice intrinsic layer disposed over the transition layer;

a superlattice low-resistance N-type layer disposed above the thirteenth superlattice intrinsic layer;

a fourteenth superlattice intrinsic layer disposed above the superlattice low-resistance N-type layer;

a fifth superlattice P-type layer disposed above the fourteenth superlattice intrinsic layer;

the second ferroelectric film layer is arranged above the fifth superlattice P-type layer;

a seventh n+ conductive layer penetrating from the upper surface of the fifth superlattice P-type layer and downward to the lower surface of the thirteenth superlattice intrinsic layer in a direction perpendicular to the fifth superlattice P-type layer;

an eleventh channel insulating layer having a shape required for device isolation, such as a rectangle, a ring, etc., penetrating downward from an upper surface of the fifth superlattice P-type layer to a lower surface of the thirteenth superlattice intrinsic layer in a direction perpendicular to the fifth superlattice P-type layer, the seventh n+ conductive layer being disposed in the eleventh channel insulating layer;

a twenty-eighth ohmic contact layer disposed over and in contact with the second ferroelectric thin film layer,

A twenty-ninth ohmic contact layer disposed over and in contact with the seventh n+ conductive layer;

a twenty-fifth dielectric protective layer disposed between the twenty-eighth ohmic contact layer and the twenty-ninth ohmic contact layer;

and a twenty-sixth dielectric protective layer arranged outside the twenty-ninth ohmic contact layer.

The superlattice ultra-large scale integrated circuit has the following advantages:

1. superhigh speed: the speed is 10 to hundreds times higher than that of conventional large-scale integrated circuits. In the gigahertz (THz) range.

2. Various field effect transistors, bipolar transistors (vertical and planar) and special function devices can be fully utilized, such as: superlattice flash memory, superlattice capacitor and varactor, superlattice resistor and varistor and superlattice inductor and inductor, etc.

3. High reliability: the high-low temperature resistance and the radiation resistance are greatly superior to those of the traditional silicon and compound integrated circuits.

4. Design flexibility: the superlattice integrated circuit can be designed and manufactured into various integrated circuits such as linear integrated circuits, analog integrated circuits, linear and analog hybrid integrated circuits, central Processing Units (CPU) and the like by utilizing the special performances and special devices of the two-dimensional electron gas and the two-dimensional hole gas.

5. The process is simplified, the production period is short, and the cost is reasonable: because the special performances of the two-dimensional electron gas and the two-dimensional hole gas of the superlattice integrated circuit are utilized to design the integrated circuit components required by industrial application, the process steps can be greatly simplified, for example, the number of photoetching templates and the corresponding process steps can be reduced by thirty percent, and the production period and the cost can be greatly optimized.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims thereof as well as the appended drawings.

The technical scheme of the invention is further described in detail through the drawings and the embodiments.

Drawings

The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, serve to explain the invention. In the drawings:

fig. 1 is a schematic diagram of a superlattice very large scale integrated circuit in accordance with an embodiment of the invention;

fig. 2 is a schematic cross-sectional view of an N-type superlattice field effect transistor in accordance with an embodiment of the invention;

Fig. 3 is a schematic cross-sectional view of a P-type superlattice field effect transistor in accordance with an embodiment of the invention;

fig. 4 is a schematic cross-sectional view of a superlattice vertical type P-N-P bipolar transistor in accordance with an embodiment of the invention;

fig. 5 is a schematic cross-sectional view of a superlattice planar P-N-P bipolar transistor in accordance with an embodiment of the invention;

fig. 6 is a top view of a superlattice planar P-N-P bipolar transistor in accordance with an embodiment of the invention;

fig. 7 is a schematic cross-sectional view of a superlattice vertical type N-P-N bipolar transistor in accordance with an embodiment of the invention;

fig. 8 is a schematic cross-sectional view of a superlattice planar N-P-N bipolar transistor in accordance with an embodiment of the invention;

fig. 9 is a top view of a superlattice planar N-P-N bipolar transistor in accordance with an embodiment of the invention;

fig. 10 is a schematic cross-sectional view of a superlattice capacitor and varactor in accordance with an embodiment of the invention;

fig. 11 is a schematic cross-sectional view of a superlattice resistor and varistor in accordance with an embodiment of the invention;

fig. 12 is a top view of a superlattice resistor and varistor in accordance with an embodiment of the invention;

fig. 13 is a schematic cross-sectional view of a superlattice inductor and a transformer in accordance with an embodiment of the invention;

fig. 14 is a top view of a superlattice inductor and a transformer in accordance with an embodiment of the invention;

FIG. 15 is a schematic cross-sectional view of a P-channel n-i-P-i superlattice field effect ferroelectric transistor in accordance with an embodiment of the invention;

FIG. 16 is a schematic cross-sectional view of an N-channel N-i-p-i superlattice field effect ferroelectric transistor in accordance with an embodiment of the invention;

FIG. 17 is a schematic diagram of an insulating layer with autonomous temperature reduction in an embodiment of the invention

Fig. 18 is a schematic view of an insulating layer according to an embodiment of the invention.

Detailed Description

The preferred embodiments of the present invention will be described below with reference to the accompanying drawings, it being understood that the preferred embodiments described herein are for illustration and explanation of the present invention only, and are not intended to limit the present invention.

The embodiment of the invention provides a superlattice very large scale integrated circuit, as shown in fig. 1, comprising:

a substrate 1;

a transition layer 2 disposed over the substrate 1;

and the component layer 3 is arranged above the transition layer 2, and the component layer 3 is used for constructing the superlattice integrated circuit by utilizing a device designed based on the special performance of the two-dimensional electron gas and the two-dimensional hole gas of the superlattice integrated circuit.

The superlattice ultra-large scale integrated circuit has the working principle and beneficial effects that:

the superlattice integrated circuit is built by utilizing a device designed based on the special performances of the two-dimensional electron gas and the two-dimensional hole gas of the superlattice integrated circuit above the transition layer, and the superlattice ultra-large scale integrated circuit (MDMFSL-ULSI) is designed based on the two-dimensional electron gas and the two-dimensional hole gas superlattice and the quantum well and has the characteristics of high speed, high reliability, radiation resistance, high temperature resistance, low temperature resistance and the like, and the design efficiency is high, the manufacturing process period is short, the cost is low, and the defects of the traditional silicon and compound integrated circuit are greatly improved.

In one embodiment, the substrate is silicon or germanium or a compound semiconductor.

In order to realize that the component layers form the superlattice ultra-large scale integrated circuit, in one embodiment, the devices designed based on the special performances of the two-dimensional electron gas and the two-dimensional hole gas of the superlattice integrated circuit comprise one or more of P-type superlattice field effect transistors, N-type superlattice field effect transistors, NPN-type superlattice bipolar transistors, PNP-type superlattice bipolar transistors, superlattice flash memories, superlattice capacitors and varactors, superlattice resistors and varistors and superlattice inductors and varistors.

To make heat dissipation faster, in one embodiment, the substrate bottom is uniformly distributed with a plurality of through holes. Through the densely distributed small holes, heat generated by circuit operation can be dissipated more quickly.

In one embodiment, as shown in fig. 2, an N-type superlattice field effect transistor includes:

a first superlattice intrinsic layer 11 disposed above the transition layer 2;

a superlattice N-type layer 12 disposed above the first superlattice intrinsic layer 11;

a second superlattice intrinsic layer 13 disposed above the superlattice N-type layer 12;

A first superlattice P-type layer 14 disposed above the second superlattice intrinsic layer 13;

a first gate insulating layer 15 disposed over the first superlattice P-type layer 14;

a first n+ conductive layer 20 penetrating from the upper surface of the first superlattice P-type layer 14 and down to the lower surface of the first superlattice intrinsic layer 11 in a direction perpendicular to the first superlattice P-type layer 14;

a first channel insulating layer 19 having a shape required for device isolation, such as a rectangle, a ring, etc., penetrating from the upper surface of the first superlattice P-type layer 14 downward to the lower surface of the first superlattice intrinsic layer 11 in a direction perpendicular to the first superlattice P-type layer 14, the first n+ conductive layer 20 being disposed inside the first channel insulating layer 19;

a first ohmic contact layer 18 disposed over the first n+ conductive layer 20 and in contact with the first n+ conductive layer 20;

a second ohmic contact layer 17 disposed over the first gate insulating layer 15 and in contact with the first gate insulating layer 15,

a first dielectric protection layer 16 disposed between the first ohmic contact layer 18 and the second ohmic contact layer 17;

a second dielectric protection layer 21 is disposed outside of the first ohmic contact layer 18.

The first N+ conductive layer can be arranged into an annular band shape or two or more independent N+ conductive layers in other shapes; when the first n+ conductive layer is in a shape of an annular band, the first ohmic contact layer may be arranged in a shape of an annular band simultaneously, or may be arranged as two or more independent n+ conductive layers of other shapes.

The principle and beneficial effects of the N-type superlattice field effect transistor are as follows:

the N-type superlattice field effect transistor is composed of an intrinsic layer of a doped superlattice (first superlattice intrinsic layer), an N-type layer of a doped superlattice (superlattice N-type layer), an intrinsic layer of a superlattice (second superlattice intrinsic layer), a P-type layer of a doped superlattice (first superlattice P-type layer), a first n+ conductive layer, and the like. To meet the performance requirements of integrated circuits, more layers of repeating structures, such as p-i-n-i-p-i-n-i-p-i, may be designed. . . . . . The device can be prepared from homogeneous superlattice layers such As silicon, gallium nitride (GaN), gallium arsenide (GaAs), heterogeneous superlattice layers such As gallium arsinide Ga (x) As (1-x) N, gallium arsinide Ga (x) Al (1-x) N, gallium arsinide Ga (x) Ps (1-x) N, and the like, and special quantum wells can be formed by utilizing different forbidden band widths to improve the device performance. The p+ conductive layer is formed by low energy ion implantation and the ohmic electrode is formed by plasma sputtering, but the plasma sputtered material will depend on the material of the superlattice semiconductor layer, such as gallium nitride material, titanium aluminum alloy, etc. The gate insulating layer may be silicon nitride or the like. The devices are isolated by an insulating layer (first channel insulating layer). The channel insulating layer can be formed by a special channel ion etching process and by adding insulating material ion sputtering and then chemical mechanical polishing. The channel insulating layer can also be formed by ion implantation, and if necessary, the maximum performance optimization can be achieved by adopting a plurality of isolation modes on the same superlattice integrated circuit.

As shown in fig. 3, the P-type superlattice field effect transistor includes:

a third superlattice intrinsic layer 22 disposed above the transition layer 2;

a superlattice P-type layer 23 disposed above the third superlattice intrinsic layer 22;

a fourth superlattice intrinsic layer 24 disposed above the superlattice P-type layer 23;

a first superlattice N-type layer 25 disposed above the fourth superlattice intrinsic layer 24;

a second gate insulating layer 26 disposed over the first superlattice N-type layer 25;

a first p+ conductive layer 27 penetrating from the upper surface of the first superlattice N-type layer 25 and down to the lower surface of the third superlattice intrinsic layer 22 in a direction perpendicular to the first superlattice N-type layer 25;

a second channel insulating layer 28 having a rectangular or annular shape penetrating from the upper surface of the first superlattice N-type layer 25 and downward to the lower surface of the third superlattice intrinsic layer 22 in a direction perpendicular to the first superlattice N-type layer 25, the first p+ conductive layer 27 being disposed within the second channel insulating layer 28;

a third ohmic contact layer 30 disposed over the first p+ conductive layer 27 and in contact with the first p+ conductive layer 27;

a fourth ohmic contact layer 32 disposed over the second gate insulating layer 26 and in contact with the second gate insulating layer 26,

A third dielectric protection layer 31 disposed between the third ohmic contact layer 30 and the fourth ohmic contact layer 32;

a fourth dielectric protection layer 29 disposed outside the third ohmic contact layer 30.

The principle and beneficial effects of the P-type superlattice field effect transistor are as follows:

consists of an intrinsic layer (a third superlattice intrinsic layer) doped with a superlattice, a P-type layer (a superlattice P-type layer) doped with a superlattice, an intrinsic layer (a fourth superlattice intrinsic layer) doped with an N-type layer (a first superlattice N-type layer) doped with a superlattice, a first P+ conductive layer and the like. To meet the performance requirements of integrated circuits, more layers of repeating structures, such as n-i-p-i-n-i, may be designed. . . . . . The device can be prepared from homogeneous superlattice layers such As silicon, gallium nitride (GaN), gallium arsenide (GaAs), heterogeneous superlattice layers such As gallium arsinide Ga (x) As (1-x) N, gallium arsinide Ga (x) Al (1-x) N, gallium arsinide Ga (x) Ps (1-x) N, and the like, and special quantum wells can be formed by utilizing different forbidden bandwidths to improve the device performance. The p+ conductive layer is formed by low energy ion implantation and the ohmic electrode is formed by plasma sputtering, but the plasma sputtered material will depend on the material of the superlattice semiconductor layer, for example, for gallium nitride materials, titanium aluminum alloys and the like can be generally used. The gate insulating layer may be silicon nitride or the like. The devices need to be isolated by an insulating layer. The channel insulating layer can be formed by a special channel ion etching process and by adding insulating material ion sputtering deposition and then chemical mechanical polishing. The channel insulating layer can also be formed by ion implantation, and if necessary, multiple isolation modes can be adopted on the same superlattice integrated circuit to achieve maximum performance optimization.

PNP type superlattice bipolar transistor is divided into superlattice planar P-N-P bipolar transistor and superlattice vertical P-N-P bipolar transistor, NPN type superlattice bipolar transistor is divided into superlattice vertical N-P-N bipolar transistor and superlattice planar N-P-N bipolar transistor.

As shown in fig. 4, the superlattice vertical type P-N-P bipolar transistor includes:

a superlattice collector P-type layer 33 disposed above the transition layer 2;

a superlattice base N-type layer 34 disposed above the superlattice collector P-type layer 33;

a superlattice emitter P-type layer 35 disposed over the superlattice base N-type layer 34;

a second p+ conductive layer 37 and a second n+ conductive layer 36 penetrating from the upper surface of the superlattice emitter P-type layer 35 and downward to the lower surface of the superlattice collector P-type layer 33 in a direction perpendicular to the superlattice emitter P-type layer 35;

a third channel insulating layer 38 having a rectangular or annular shape penetrating from the upper surface of the superlattice emitter P-type layer 35 and downward to the lower surface of the superlattice collector P-type layer 33 in a direction perpendicular to the superlattice emitter P-type layer 35, the second p+ conductive layer 37 and the second n+ conductive layer 36 being disposed within the third channel insulating layer 38;

A fifth ohmic contact layer 39 disposed over the second p+ conductive layer 37 and in contact with the second p+ conductive layer 3;

a sixth ohmic contact layer 40 disposed over the second n+ conductive layer 36 and in contact with the second n+ conductive layer 36;

a seventh ohmic contact layer 41 disposed over the superlattice emitter P-type layer 35 and in contact with the superlattice emitter P-type layer 35,

a fifth dielectric protection layer 42 disposed between the seventh ohmic contact layer 41 and the fifth ohmic contact layer 39, and between the seventh ohmic contact layer 41 and the sixth ohmic contact layer 40;

and a sixth dielectric protective layer 43 disposed outside the fifth ohmic contact layer 39 and the sixth ohmic contact layer 40.

A seventh dielectric protection layer 44 is disposed between the superlattice emitter P-type layer 35 and the second n+ conductive layer 36, and the superlattice emitter P-type layer 35 and the second p+ conductive layer 37.

The superlattice vertical type P-N-P bipolar transistor consists of a collector P type layer doped with a superlattice (a superlattice collector P type layer), a base N type layer doped with a superlattice (a superlattice base N type layer), an emitter P type layer doped with a superlattice (a superlattice emitter P type layer), a second P+ conductive layer, a second N+ conductive layer and the like. To meet the performance requirements of bipolar transistor integrated circuits, more layers of structures, such as p-i-n-i-p, may be designed. . . . . . The device can be prepared from homogeneous superlattice layers such As silicon, gallium nitride (GaN), gallium arsenide (GaAs), heterogeneous superlattice layers such As gallium arsinide Ga (x) As (1-x) N, gallium arsinide Ga (x) Al (1-x) N, gallium arsinide Ga (x) Ps (1-x) N, and the like, and special quantum wells can be formed by utilizing different forbidden band widths to improve the device performance. The n+ and p+ conductive layers are formed by low energy ion implantation techniques, respectively, and the ohmic electrode is formed by plasma sputtering techniques, but the plasma sputtered material will depend on the material of the superlattice semiconductor layer, such as for gallium nitride materials, typically titanium aluminum alloys, and the like. The gate insulating layer may be silicon nitride or the like. The devices need to be isolated by an insulating layer. The channel insulating layer can be formed by a special channel ion etching process and by adding insulating material ion sputtering and then chemical mechanical polishing. The channel insulating layer can also be formed by ion implantation, and if necessary, the maximum performance optimization can be achieved by adopting a plurality of isolation modes on the same superlattice integrated circuit.

As shown in fig. 5 and 6, the superlattice planar type P-N-P bipolar transistor includes:

the superlattice emitter P-type region 45 is cylindrical and is arranged above the transition layer;

the superlattice base N-type region 46 is annular, is arranged above the transition layer and is sleeved outside the superlattice emitter P-type region 45;

the superlattice collector P-type region 47 is annular, is arranged above the transition layer and is sleeved outside the superlattice base N-type region 46;

the fourth channel insulating layer 48 is annular and sleeved outside the P-type region of the superlattice base, and the fourth channel insulating layer 48 is arranged above the transition layer or above the transition layer and embedded in the substrate after penetrating through the transition layer;

the eighth ohmic contact layer 49 is circular, is disposed over the superlattice emitter P-type region 45 and contacts the superlattice emitter P-type region 45;

the ninth ohmic contact layer 51 is annular, is disposed above the superlattice base N-type region 46 and contacts the superlattice base N-type region 46;

the tenth ohmic contact layer 53 is annular, is disposed over the superlattice collector P-type region 47 and contacts the superlattice collector P-type region 47;

An eighth dielectric protection layer 50 having a ring shape and disposed between the eighth ohmic contact layer 49 and the ninth ohmic contact layer 51;

a ninth dielectric protection layer 52 having a ring shape and disposed between the ninth ohmic contact layer 51 and the tenth ohmic contact layer 53;

the tenth dielectric protection layer 54 is annular and is disposed outside the tenth ohmic contact layer 53.

The superlattice planar P-N-P bipolar transistor consists of a collector P-type region (superlattice collector P-type region) doped with a superlattice, a base N-type region (superlattice base N-type region 46) doped with a superlattice, a P-type region (superlattice emitter P-type region) doped with a superlattice emitter, a P-type ohmic contact layer, an N-type ohmic contact layer and the like. To meet the performance requirements of bipolar transistor integrated circuits, more layers of structures, such as p-i-n-i-p, may be designed. . . . . . The device can be prepared from homogeneous superlattice layers such As silicon, gallium nitride (GaN), gallium arsenide (GaAs), heterogeneous superlattice layers such As gallium arsinide Ga (x) As (1-x) N, gallium arsinide Ga (x) Al (1-x) N, gallium arsinide Ga (x) Ps (1-x) N, and the like, and special quantum wells can be formed by utilizing different forbidden band widths to improve the device performance. The superlattice collector P-type region, the doped superlattice base N-type region 46, the doped superlattice emitter P-type region, and the like are respectively formed using a low-energy ion implantation technique. The ohmic electrode is formed by plasma sputtering techniques, but the plasma sputtered material will depend on the material of the superlattice semiconductor layer, such as for gallium nitride materials, titanium aluminum alloys, etc. are generally available. The gate insulating layer may be silicon nitride or the like. The devices need to be isolated by an insulating layer. The channel insulating layer can be formed by a special channel ion etching process and by adding insulating material ion sputtering and then chemical mechanical polishing. The channel insulating layer can also be formed by ion implantation, and if necessary, the maximum performance optimization can be achieved by adopting a plurality of isolation modes on the same superlattice integrated circuit.

As shown in fig. 7, the superlattice vertical type N-P-N bipolar transistor includes:

a superlattice collector N-type layer 65 disposed above the transition layer 2;

a superlattice base P-type layer 66 disposed above the superlattice collector N-type layer 65;

a superlattice emitter N-type layer 67 disposed over the superlattice base P-type layer 66;

a third p+ conductive layer 68 and a third n+ conductive layer 69 penetrating from the upper surface of the superlattice emitter N-type layer 67 and downward to the lower surface of the superlattice collector N-type layer 65 in a direction perpendicular to the superlattice emitter N-type layer 67;

a fifth channel insulating layer 70 having a ring shape penetrating from the upper surface of the superlattice emitter N-type layer 67 and downward to the lower surface of the superlattice collector N-type layer 65 in a direction perpendicular to the superlattice emitter N-type layer 67, the third p+ conductive layer 68 and the third n+ conductive layer 69 being disposed within the fifth channel insulating layer 70;

an eleventh ohmic contact layer 72 disposed above the third p+ conductive layer 68 and in contact with the third p+ conductive layer 68;

a twelfth ohmic contact layer 71 disposed over the third n+ conductive layer 69 and in contact with the third n+ conductive layer 69;

a thirteenth ohmic contact layer 73 disposed on the superlattice emitter N-type layer 67 and in contact with the superlattice emitter N-type layer 67,

An eleventh dielectric protection layer 74 disposed between the thirteenth and eleventh ohmic contact layers 73 and 72 and between the thirteenth and twelfth ohmic contact layers 73 and 71;

a twelfth dielectric protective layer 75 disposed outside the eleventh ohmic contact layer 72 and the twelfth ohmic contact layer 71.

A thirteenth dielectric protection layer 76 is disposed between the superlattice emitter N-type layer 67 and the third n+ conductive layer 69, and the superlattice emitter N-type layer 67 and the third p+ conductive layer 68.

The superlattice vertical type N-P-N bipolar transistor consists of a collector N type layer (superlattice collector N type layer) doped with a superlattice, a base P type layer (superlattice base P type layer) doped with a superlattice, an emitter N type layer (superlattice emitter N type layer) doped with a superlattice, a third P+ conductive layer, a third N+ conductive layer and the like. To meet the performance requirements of bipolar transistor integrated circuits, more layers of structures, such as n-i-p-i-n, may be designed. . . . . . The device can not only adopt homogeneous superlattice layers such As silicon, gallium nitride (GaN) and gallium arsenide (GaAs), but also adopt heterogeneous superlattice layers such As gallium arsinide Ga (x) As (1-x) N and gallium arsinide Ga (x) Al (1-x) N, and form special quantum wells by utilizing different forbidden band widths so As to improve the device performance. The n+ and p+ conductive layers are formed by low energy ion implantation techniques, respectively, and the ohmic electrode is formed by plasma sputtering techniques, but the plasma sputtered material will depend on the material of the superlattice semiconductor layer, such as for gallium nitride materials, typically titanium aluminum alloys, and the like. The gate insulating layer may be silicon nitride or the like. The devices need to be isolated by an insulating layer. The channel insulating layer can be formed by a special channel ion etching process and by adding insulating material ion sputtering and then chemical mechanical polishing.

The channel insulating layer can also be formed by ion implantation, and if necessary, the maximum performance optimization can be achieved by adopting a plurality of isolation modes on the same superlattice integrated circuit.

As shown in fig. 8 and 9, the superlattice planar type N-P-N bipolar transistor includes:

the superlattice emitter N-type region 55 is cylindrical and is arranged above the transition layer 2;

the superlattice base P-type region 56 is annular, is arranged above the transition layer 2 and is sleeved outside the superlattice emitter N-type region 55;

the superlattice collector N-type region 57 is annular, is arranged above the transition layer 2 and is sleeved outside the superlattice base P-type region 56;

the sixth channel insulating layer 58 is annular and sleeved outside the superlattice collector N-type region 57, and the sixth channel insulating layer 58 is arranged above the transition layer 2 or above the transition layer 2 and penetrates through the transition layer 2 to be embedded in the substrate;

the fourteenth ohmic contact layer 59 is circular, disposed over the superlattice emitter N-type region 55 and in contact with the superlattice emitter N-type region 55;

the fifteenth ohmic contact layer 61 is annular, is disposed over the superlattice base P-type region 56 and is in contact with the superlattice base P-type region 56;

The sixteenth ohmic contact layer 63 is annular, disposed over the superlattice collector N-type region 57 and in contact with the superlattice collector N-type region 57;

a fourteenth dielectric protective layer 60 having a ring shape and disposed between the fourteenth ohmic contact layer 59 and the fifteenth ohmic contact layer 61;

a fifteenth dielectric protection layer 62 having a ring shape and disposed between the fifteenth ohmic contact layer 61 and the sixteenth ohmic contact layer 63;

the sixteenth dielectric protection layer 64 is annular and is disposed outside the sixteenth ohmic contact layer 63.

The superlattice planar N-P-N bipolar transistor consists of a collector N-type region (superlattice collector N-type region) doped with a superlattice, a base P-type region (superlattice base P-type region) doped with a superlattice, an emitter N-type region (superlattice emitter N-type region) doped with a superlattice, an ohmic contact layer and the like. To meet the performance requirements of bipolar transistor integrated circuits, more layers of structures, such as n-i-p-i-n, may be designed. . . . . . The device can be prepared from homogeneous superlattice layers such As silicon, gallium nitride (GaN), gallium arsenide (GaAs), heterogeneous superlattice layers such As gallium arsinide Ga (x) As (1-x) N, gallium arsinide Ga (x) Al (1-x) N, gallium arsinide Ga (x) Ps (1-x) N, and the like, and special quantum wells can be formed by utilizing different forbidden bandwidths to improve the device performance. And respectively forming a superlattice collector N-type region, a doped superlattice base P-type region, a doped superlattice emitter N-type region and the like by using a low-energy ion implantation technology. The ohmic electrode is formed by plasma sputtering techniques, but the plasma sputtered material will depend on the material of the superlattice semiconductor layer, such as for gallium nitride materials, titanium aluminum alloys, etc. are generally available. The gate insulating layer may be silicon nitride or the like. The devices need to be isolated by an insulating layer. The channel insulating layer can be formed by a special channel ion etching process and by adding insulating material ion sputtering and then chemical mechanical polishing. The channel insulating layer can also be formed by ion implantation, and if necessary, the maximum performance optimization can be achieved by adopting a plurality of isolation modes on the same superlattice integrated circuit.

As shown in fig. 10, the superlattice capacitor and varactor includes:

a fifth superlattice intrinsic layer 77 disposed above the transition layer 2;

a second superlattice P-type layer 78 disposed above the fifth superlattice intrinsic layer 77;

a sixth superlattice intrinsic layer 79 disposed above the second superlattice P-type layer 78;

a first superlattice low-resistance N-type layer 80 disposed above the sixth superlattice intrinsic layer 79;

a fourth p+ conductive layer 81 and a fourth n+ conductive layer 82 penetrate from the upper surface of the first superlattice low-resistance N-type layer 80 downward to the lower surface of the fifth superlattice intrinsic layer 77 in a direction perpendicular to the first superlattice low-resistance N-type layer 80;

a seventh channel insulating layer 83 having a ring shape penetrating from the upper surface of the first superlattice low-resistance N-type layer 80 and downward to the lower surface of the fifth superlattice intrinsic layer 77 in a direction perpendicular to the first superlattice low-resistance N-type layer 80, the fourth p+ conductive layer 81 and the fourth n+ conductive layer 82 being disposed within the seventh channel insulating layer 83;

a seventeenth ohmic contact layer 84 disposed over the first superlattice low-resistance N-type layer 80 and in contact with the first superlattice low-resistance N-type layer 80;

an eighteenth ohmic contact layer 85 disposed over the fourth n+ conductive layer 82 and in contact with the fourth n+ conductive layer 82;

A nineteenth ohmic contact layer 86 disposed over the fourth p+ conductive layer 81 and in contact with the fourth p+ conductive layer 81;

a seventeenth dielectric protective layer 87 disposed between the seventeenth ohmic contact layer 84 and the eighteenth ohmic contact layer 85, and between the seventeenth ohmic contact layer 84 and the nineteenth ohmic contact layer 86;

an eighteenth dielectric protective layer 88 is provided outside the eighteenth ohmic contact layer 85 and the nineteenth ohmic contact layer 86.

The superlattice N-i-P-i diode and the PN junction capacitance varactor (superlattice capacitance and varactor) are composed of a superlattice intrinsic layer (fifth superlattice intrinsic layer), a base P-type layer doped with a superlattice (second superlattice P-type layer), a superlattice intrinsic layer (sixth superlattice intrinsic layer), an N-type layer doped with a superlattice (first superlattice low-resistance N-type layer), a fourth P+ conductive layer, a fourth N+ conductive layer and the like. To meet the performance requirements of bipolar transistor integrated circuits, more layers of structures, such as n-i-p-i-n, may be designed. . . . . . The device can be prepared from homogeneous superlattice layers such As silicon, gallium nitride (GaN), gallium arsenide (GaAs), heterogeneous superlattice layers such As gallium arsinide Ga (x) As (1-x) N, gallium arsinide Ga (x) Al (1-x) N, gallium arsinide Ga (x) Ps (1-x) N, and the like, and special quantum wells can be formed by utilizing different forbidden bandwidths to improve the device performance. The n+ and p+ conductive layers are formed by low energy ion implantation techniques, respectively, and the ohmic electrode is formed by plasma sputtering techniques, but the plasma sputtered material will depend on the material of the superlattice semiconductor layer, such as for gallium nitride materials, typically titanium aluminum alloys, and the like. The gate insulating layer may be silicon nitride or the like. The devices need to be isolated by an insulating layer. The channel insulating layer can be formed by a special channel ion etching process and by adding insulating material ion sputtering and then chemical mechanical polishing. The channel insulating layer can also be formed by ion implantation, and if necessary, the maximum performance optimization can be achieved by adopting a plurality of isolation modes on the same superlattice integrated circuit.

As shown in fig. 11, the superlattice resistor and varistor includes:

a seventh superlattice intrinsic layer 89 disposed above the transition layer 2;

a third superlattice P-type layer 90 disposed above the seventh superlattice intrinsic layer 89;

an eighth superlattice intrinsic layer 91 disposed above the third superlattice P-type layer 90;

a second superlattice low-resistance N-type layer 92 disposed above the eighth superlattice intrinsic layer 91;

the fifth p+ conductive layer 93 and the fifth n+ conductive layer 94 penetrate from the upper surface of the second superlattice low-resistance N-type layer 92 downward to the lower surface of the seventh superlattice intrinsic layer 89 in a direction perpendicular to the second superlattice low-resistance N-type layer 92;

an eighth channel insulating layer 95 having a rectangular or annular shape penetrating from the upper surface of the second superlattice low-resistance N-type layer 92 downward to the lower surface of the seventh superlattice intrinsic layer 89 in a direction perpendicular to the second superlattice low-resistance N-type layer 92, the fifth p+ conductive layer 93 and the fifth n+ conductive layer 94 being disposed within the eighth channel insulating layer 95;

a twenty-first ohmic contact layer 96, a twenty-first ohmic contact layer 97, and a twenty-second ohmic contact layer 98 are provided in a group, two groups being provided;

A twentieth ohmic contact layer 96 disposed over the second superlattice low-resistance N-type layer 92 and in contact with the second superlattice low-resistance N-type layer 92;

a twenty-first ohmic contact layer 97 disposed over the fifth n+ conductive layer 94 and in contact with the fifth n+ conductive layer 94;

a twenty-second ohmic contact layer 98 disposed over the fifth p+ conductive layer 93 and in contact with the fifth p+ conductive layer 93;

a nineteenth dielectric protective layer 99 disposed between the twentieth ohmic contact layer 96 and the twenty-first ohmic contact layer 97, and the twentieth ohmic contact layer 96 and the twenty-second ohmic contact layer 98;

a twentieth dielectric protective layer 100 is disposed outside the twenty-first ohmic contact layer 97 and the twenty-second ohmic contact layer 98.

As shown in fig. 12, in one embodiment, the superlattice resistor and varistor includes two sets of twenty-first ohmic contact layers 96, 97, and 98. Wherein the eighth channel insulating layer 95 is ring-shaped with an I-shaped void; a set of twenty-first, and twenty-second ohmic contact layers 96, 97, 98 are disposed at each end of the i-shaped void.

The superlattice N-i-P-i resistor and varistor (superlattice resistor and varistor) is composed of a superlattice intrinsic layer (seventh superlattice intrinsic layer), a base P-type layer doped with superlattice (third superlattice P-type layer), a superlattice intrinsic layer (eighth superlattice intrinsic layer), an N-type layer doped with superlattice (second superlattice low-resistance N-type layer), a fifth p+ conductive layer and a fifth n+ conductive layer. To meet the performance requirements of bipolar transistor integrated circuits, more layers of structures, such as n-i-p-i-n, may be designed. . . . . . The device can be prepared from homogeneous superlattice layers such As silicon, gallium nitride (GaN), gallium arsenide (GaAs), heterogeneous superlattice layers such As gallium arsinide Ga (x) As (1-x) N, gallium arsinide Ga (x) Al (1-x) N, gallium arsinide Ga (x) Ps (1-x) N, and the like, and special quantum wells can be formed by utilizing different forbidden bandwidths to improve the device performance. The n+ and p+ conductive layers are formed by low energy ion implantation techniques, respectively, and the ohmic electrode is formed by plasma sputtering techniques, but the plasma sputtered material will depend on the material of the superlattice semiconductor layer, such as for gallium nitride materials, typically titanium aluminum alloys, and the like. The gate insulating layer may be silicon nitride or the like. The devices need to be isolated by an insulating layer. The channel insulating layer can be formed by a special channel ion etching process and by adding insulating material ion sputtering and then chemical mechanical polishing. The channel insulating layer can also be formed by ion implantation, and if necessary, the maximum performance optimization can be achieved by adopting a plurality of isolation modes on the same superlattice integrated circuit.

As shown in fig. 13, the superlattice inductor and the inductor include:

a ninth superlattice intrinsic layer 101 disposed above the transition layer 2;

a fourth superlattice P-type layer 102 disposed above the ninth superlattice intrinsic layer 101;

a tenth superlattice intrinsic layer 103 disposed above the fourth superlattice P-type layer 102;

a third superlattice low-resistance N-type layer 104 disposed above the tenth superlattice intrinsic layer 103;

the sixth p+ conductive layer 105 and the sixth n+ conductive layer 106 penetrate from the upper surface of the third superlattice low-resistance N-type layer 104 and downward to the lower surface of the ninth superlattice intrinsic layer 101 in a direction perpendicular to the third superlattice low-resistance N-type layer 104;

a ninth channel insulating layer 107 having a rectangular or annular shape penetrating from the upper surface of the third superlattice low-resistance N-type layer 104 and downward to the lower surface of the ninth superlattice intrinsic layer 101 in a direction perpendicular to the third superlattice low-resistance N-type layer 104, the sixth p+ conductive layer 105 and the sixth n+ conductive layer 106 being disposed within the ninth channel insulating layer 107;

a twenty-third ohmic contact layer 108, a twenty-fourth ohmic contact layer 109, and a twenty-fifth ohmic contact layer 110, in total, in two groups;

A twenty-third ohmic contact layer 108 disposed over the third superlattice low-resistance N-type layer 104 and in contact with the third superlattice low-resistance N-type layer 104;

a twenty-fourth ohmic contact layer 109 disposed over the sixth n+ conductive layer 106 and in contact with the sixth n+ conductive layer 106;

a twenty-fifth ohmic contact layer 110 disposed over the sixth p+ conductive layer 105 and in contact with the sixth p+ conductive layer 105;

a twenty-first dielectric protective layer 111 disposed between the twenty-third ohmic contact layer 108 and the twenty-fourth ohmic contact layer 109, and between the twenty-third ohmic contact layer 108 and the twenty-fourth ohmic contact layer 109;

a twenty-second dielectric protective layer 112, disposed outside the twenty-fourth ohmic contact layer 109 and the twenty-fifth ohmic contact layer 110.

As shown in fig. 14, in one embodiment, the superlattice inductance and the transformer include two sets of a twenty-third ohmic contact layer 108, a twenty-fourth ohmic contact layer 109, and a twenty-fifth ohmic contact layer 110. The ninth channel insulating layer 107 is annular with an S-shaped void left therein; a set of twenty-third ohmic contact layer 108, twenty-fourth ohmic contact layer 109, and twenty-fifth ohmic contact layer 110 are disposed at both ends of the S-type void, respectively.

The superlattice N-i-P-i inductor and the inductor (superlattice inductor and inductor) are composed of a superlattice intrinsic layer (ninth superlattice intrinsic layer), a base P-type layer doped with a superlattice (fourth superlattice P-type layer), a superlattice intrinsic layer (tenth superlattice intrinsic layer), an N-type layer doped with a superlattice (third superlattice low-resistance N-type layer), a sixth p+ conductive layer, a sixth n+ conductive layer, and the like. To meet the performance requirements of integrated circuits, more layers of structures, such as n-i-p-i-n, may be designed. . . . . . The device can be prepared from homogeneous superlattice layers such As silicon, gallium nitride (GaN), gallium arsenide (GaAs), heterogeneous superlattice layers such As gallium arsinide Ga (x) As (1-x) N, gallium arsinide Ga (x) Al (1-x) N, gallium arsinide Ga (x) Ps (1-x) N, and the like, and special quantum wells can be formed by utilizing different forbidden bandwidths to improve the device performance. The n+ and p+ conductive layers are formed by low energy ion implantation techniques, respectively, and the ohmic electrode is formed by plasma sputtering techniques, but the plasma sputtered material will depend on the material of the superlattice semiconductor layer, such as for gallium nitride materials, typically titanium aluminum alloys, and the like. The gate insulating layer may be silicon nitride or the like. The devices need to be isolated by an insulating layer. The channel insulating layer can be formed by a special channel ion etching process and by adding insulating material ion sputtering and then chemical mechanical polishing. The channel insulating layer can also be formed by ion implantation, and if necessary, the maximum performance optimization can be achieved by adopting a plurality of isolation modes on the same superlattice integrated circuit.

An N-i-P-i superlattice flash memory (superlattice flash memory) includes a P-channel doped N-i-P-i superlattice field effect ferroelectric transistor or an N-channel doped N-i-P-i superlattice field effect ferroelectric transistor.

As shown in fig. 15, wherein the P-channel n-i-P-i superlattice field effect ferroelectric transistor comprises:

an eleventh superlattice intrinsic layer 113 disposed above the transition layer 2;

a superlattice low-resistance P-type layer 114 disposed above the eleventh superlattice intrinsic layer 113;

a twelfth superlattice intrinsic layer 115 disposed above the superlattice low-resistance P-type layer 114;

a second superlattice N-type layer 116 disposed above the twelfth superlattice intrinsic layer 115;

a first ferroelectric thin film layer 117 disposed over the second superlattice N-type layer 116;

a seventh p+ conductive layer 118 penetrating from the upper surface of the second superlattice N-type layer 116 and downward to the lower surface of the eleventh superlattice intrinsic layer 113 in a direction perpendicular to the second superlattice N-type layer 116;

a tenth channel insulating layer 119 having a rectangular or annular shape penetrating from the upper surface of the second superlattice N-type layer 116 and downward to the lower surface of the eleventh superlattice intrinsic layer 113 in a direction perpendicular to the second superlattice N-type layer 116, the seventh p+ conductive layer 118 being disposed within the tenth channel insulating layer 119;

A twenty-sixth ohmic contact layer 120 disposed over the first ferroelectric thin film layer 117 and in contact with the first ferroelectric thin film layer 117,

a twenty-seventh ohmic contact layer 121 disposed over the seventh p+ conductive layer 118 and in contact with the seventh p+ conductive layer 118;

a twenty-third dielectric protective layer 123 disposed between the twenty-sixth ohmic contact layer 120 and the twenty-seventh ohmic contact layer 121;

a twenty-fourth dielectric protective layer 124 disposed outside the twenty-seventh ohmic contact layer 121.

The doped P-channel N-i-P-i superlattice field effect ferroelectric transistor (P-channel N-i-P-i superlattice field effect ferroelectric transistor) is composed of a ferroelectric thin film layer, a doped superlattice intrinsic layer (eleventh superlattice intrinsic layer), a doped superlattice P-type layer (superlattice low-resistance P-type layer), a superlattice intrinsic layer (twelfth superlattice intrinsic layer), a doped superlattice N-type layer (second superlattice N-type layer), a seventh p+ conductive layer, and the like. To meet the performance requirements of integrated circuits, superlattice thin film layers of different thicknesses may be designed. The device can be prepared from homogeneous superlattice layers such As silicon, gallium nitride (GaN) and gallium arsenide (GaAs), heterogeneous superlattice layers such As gallium arsinide Ga (x) As (1-x) N, gallium aluminum nitride Ga (x) Al (1-x) N, gallium phosphide Ga (x) Ps (1-x) N and the like, and special quantum wells can be formed by utilizing different forbidden bandwidths to improve the device performance. The p+ conductive layer is formed by low energy ion implantation and the ohmic electrode is formed by plasma sputtering, but the plasma sputtered material will depend on the material of the superlattice semiconductor layer, such as gallium nitride material, titanium aluminum alloy, etc. The gate insulating layer may be silicon nitride or the like. The devices need to be isolated by an insulating layer. The channel insulating layer can be formed by a special channel ion etching process and by adding insulating material ion sputtering and then chemical mechanical polishing. The channel insulating layer can also be formed by ion implantation, and if necessary, the maximum performance optimization can be achieved by adopting a plurality of isolation modes on the same superlattice integrated circuit.

Also, doped N-channel N-i-p-i superlattice field effect ferroelectric transistors may be designed and fabricated. The principle is quite similar, but when a voltage in the same direction is applied to the ferroelectric film, for example, when a negative voltage is applied, the doped P-channel N-i-P-i superlattice field effect ferroelectric transistor is in an on state, and the doped N-channel N-i-P-i superlattice field effect ferroelectric transistor is in an off state;

as shown in fig. 16, wherein the N-channel N-i-p-i superlattice field effect ferroelectric transistor comprises:

a thirteenth superlattice intrinsic layer 125 disposed above the transition layer 2;

a superlattice low-resistance N-type layer 126 disposed above the thirteenth superlattice intrinsic layer 125;

a fourteenth superlattice intrinsic layer 127 disposed above the superlattice low-resistance N-type layer 126;

a fifth superlattice P-type layer 128 disposed above the fourteenth superlattice intrinsic layer 127;

a second ferroelectric thin film layer 129 disposed over the fifth superlattice P-type layer 128;

a seventh n+ conductive layer 130 penetrating from the upper surface of the fifth superlattice P-type layer 128 and downward to the lower surface of the thirteenth superlattice intrinsic layer 125 in a direction perpendicular to the fifth superlattice P-type layer 128;

an eleventh channel insulating layer 131 penetrating from the upper surface of the fifth superlattice P-type layer 128 downward to the lower surface of the thirteenth superlattice intrinsic layer 125 in a direction perpendicular to the fifth superlattice P-type layer 128, the seventh n+ conductive layer 130 being disposed within the eleventh channel insulating layer 131;

A twenty-eighth ohmic contact layer 132 disposed over the second ferroelectric thin film layer 129 and in contact with the second ferroelectric thin film layer 129,

a twenty-ninth ohmic contact layer 133 disposed over the seventh n+ conductive layer 130 and in contact with the seventh n+ conductive layer 130;

a twenty-fifth dielectric protective layer 134 disposed between the twenty-eighth ohmic contact layer 132 and the twenty-ninth ohmic contact layer 133;

a twenty-sixth dielectric protective layer 135 is disposed outside the twenty-ninth ohmic contact layer 133.

The first to eleventh channel insulating layers are self-cooling insulating layers.

As shown in fig. 17, the self-cooling insulating layer 202 includes:

a cooling substance accommodation chamber 201 provided in the autonomous cooling insulation layer 202,

a first capillary 203, disposed in the autonomous cooling insulation layer 202, with one end connected to the cooling substance accommodating cavity 201 and the other end connected to the upper surface of the autonomous cooling insulation layer 202;

in the dielectric protection layer 204 above the self-cooling insulation layer 202, a second capillary tube 205 is also disposed, where the second capillary tube 205 is communicated with the first capillary tube 203 of the self-cooling insulation layer 202, and a portion of the second capillary tube 205 near the upper surface of the dielectric protection layer 204 is curved, so that an outlet of the upper surface of the second capillary tube 205 forms an angle (may be 15 degrees) with the upper surface, and thus when the temperature rises and changes, the cooling material flows out from the outlet of the second capillary tube 205 onto the ohmic contact layer. Thereby cooling down.

By arranging the self-cooling insulating layer, when the component is burnt after being short-circuited, the phase change of the cooling substance in the self-cooling insulating layer is heated, so that the heat is absorbed, the volume of the cooling substance is increased when the phase change further occurs, the cooling substance is sprayed out of the capillary pipeline and onto the burnt component, and the burnt component is further cooled; this prevents damage to nearby components, thereby reducing losses.

The first to eleventh channel insulating layers are isolation insulating layers:

as shown in fig. 18, a cavity 212 is provided inside the insulating layer 211; a cooling substance is disposed within the cavity 212.

By arranging the insulating layer, when the components are burnt after being short-circuited, the outer insulating layer of the insulating layer releases cooling substances after being burnt, and the cooling substances are heated to generate phase change, so that heat is absorbed, and the volume of the cooling substances is increased when the phase change further occurs, so that the burnt components are isolated from external intact components; this prevents damage to nearby components, thereby reducing losses.

As shown in fig. 18, in one embodiment, at least one connecting body 213 is disposed in the cavity 212, one end of the connecting body 213 is connected to the left side wall of the cavity 212, and the other end is connected to the right side wall of the cavity 212; the diameter of the middle part of the connecting body 213 is smaller than that of the two ends.

By arranging the connector, the space in the cavity is supported, so that the cavity structure is firmer; the middle diameter is smaller than the two ends, so that when the cooling substance is heated and expanded, the breaking position of the connecting body is positioned at the middle part, and the components which are perfect beside the connecting body are pulled when being placed and expanded, so that the damage to the components caused by pulling is avoided.

Furthermore, fluorescent substances are doped in the cooling substances, and when the circuit is burnt out, images of the fluorescent substances of the insulating layer can be checked so as to judge the damaged position and degree of the circuit more quickly.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

1. A superlattice ultra-large scale integrated circuit, comprising:

a substrate;

a transition layer disposed over the substrate;

the component layer is arranged above the transition layer and is a superlattice integrated circuit constructed by a device containing two-dimensional electron gas and two-dimensional hole gas;

The device comprises: PNP superlattice bipolar transistor;

the PNP superlattice bipolar transistor is divided into a superlattice planar type P-N-P bipolar transistor and a superlattice vertical type P-N-P bipolar transistor;

wherein the superlattice vertical type P-N-P bipolar transistor comprises:

the superlattice collector P-type layer is arranged above the transition layer;

the third channel insulating layer penetrates downwards from the upper surface of the superlattice emitter P-type layer to the lower surface of the superlattice collector P-type layer in a direction perpendicular to the superlattice emitter P-type layer, and the second P+ conducting layer and the second N+ conducting layer are arranged in the third channel insulating layer;

wherein the superlattice planar P-N-P bipolar transistor comprises:

the superlattice planar P-N-P bipolar transistor includes:

2. The superlattice ultra-large scale integrated circuit as recited in claim 1, wherein said substrate is silicon, germanium or a compound semiconductor.

3. The superlattice ultra-large scale integrated circuit as recited in claim 1, wherein said transition layer is one of a silicon dioxide, silicon nitride, and compound semiconductor layer.

4. The superlattice ultra-large scale integrated circuit as recited in claim 1, wherein the plurality of through holes are uniformly distributed in the bottom of the substrate.

5. The superlattice ultra-large scale integrated circuit as recited in claim 1, wherein the superlattice collector P-type layer, the superlattice base N-type layer, and the superlattice emitter P-type layer are either homogeneous semiconductor superlattice layers or heterogeneous semiconductor superlattice layers.

6. A superlattice ultra-large scale integrated circuit, comprising:

a substrate;

a transition layer disposed over the substrate;

the device comprises: an NPN superlattice bipolar transistor;

the NPN superlattice bipolar transistor is divided into a superlattice vertical type N-P-N bipolar transistor and a superlattice planar type N-P-N bipolar transistor;

wherein the superlattice vertical type N-P-N bipolar transistor comprises:

The superlattice collector N-type layer is arranged above the transition layer;

the third P+ conductive layer and the third N+ conductive layer penetrate downwards from the upper surface of the superlattice emitter N-type layer to the lower surface of the superlattice collector N-type layer in a direction perpendicular to the superlattice emitter N-type layer;

a fifth channel insulating layer penetrating from the upper surface of the superlattice emitter N-type layer and downwards to the lower surface of the superlattice collector N-type layer in a direction perpendicular to the superlattice emitter N-type layer, wherein the third p+ conductive layer and the third n+ conductive layer are arranged in the fifth channel insulating layer;

wherein the superlattice planar type N-P-N bipolar transistor comprises:

7. The superlattice ultra-large scale integrated circuit as recited in claim 6, wherein said substrate is silicon, germanium or a compound semiconductor.

8. The superlattice ultra-large scale integrated circuit as recited in claim 6, wherein said transition layer is one of a silicon dioxide, silicon nitride, and compound semiconductor layer.

9. The superlattice ultra-large scale integrated circuit as recited in claim 6, wherein the plurality of through holes are uniformly distributed in the bottom of the substrate.

10. The superlattice ultra-large scale integrated circuit as recited in claim 6, wherein the superlattice collector N-type layer, the superlattice base P-type layer, and the superlattice emitter N-type layer are either homogeneous semiconductor superlattice layers or heterogeneous semiconductor superlattice layers.