CN109411348B - Method for designing high-power anti-radiation transistor chip and chip - Google Patents
Method for designing high-power anti-radiation transistor chip and chip Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 43
- 230000003471 anti-radiation Effects 0.000 title description 2
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- 238000007254 oxidation reaction Methods 0.000 claims abstract description 34
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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Abstract
The disclosure provides a method for designing a high-power radiation-resistant transistor chip and a chip. The method for designing the high-power radiation-resistant transistor chip comprises the following steps: designing a transverse layout in a gridding manner, and setting relevant parameters of a base region, an emitter region and a bonding region; the base region is divided into a deep base region and a light base region according to the electron diffusion concentration; designing a longitudinal structure according to the performance requirements of preset parameters of the chip to obtain the junction depth of a collector junction and the junction depth of an emitter junction; the following process procedures are sequentially carried out: the method comprises the following steps of primary oxidation, deep base region photoetching, deep base region diffusion, secondary oxidation, light base region photoetching, light base region diffusion, tertiary oxidation, emitter region photoetching, emitter region diffusion, quartic oxidation, lead hole photoetching, aluminum evaporation, aluminum reverse etching and alloy technology, and finally the high-power transistor chip with the preset radiation-resistant performance parameters is obtained.
Description
Technical Field
The disclosure belongs to the technical field of transistor manufacturing, and particularly relates to a method for designing a high-power radiation-resistant transistor chip and the chip.
Background
The statements in this section merely provide background information related to the present disclosure and may not necessarily constitute prior art.
Statistically, the total number of failures caused by various reasons of 39 satellites launched abroad is 1589 times since 1971 to 1986, wherein the number of failures related to space radiation is 1129 times, accounting for 71% of the total number of failures, so that the failures of visible satellites and spacecrafts mainly originate from the space radiation.
For high power bipolar transistors, the spatial radiation is mainly the total dose effect. After the high-power bipolar transistor bears certain space energy, the electrical characteristics of the high-power bipolar transistor can change, such as gain reduction, electric leakage increase, saturation voltage increase and the like, and the reliability and the quality of the spacecraft are seriously influenced by the change of the electrical characteristics of the device.
With the development of aerospace industry in China, the number of the satellites and the spacecraft is continuously increased in recent years, the on-orbit operation time is longer and longer, and the corresponding space irradiation problem is more and more, so that the radiation resistance of a high-power bipolar device is urgently needed to be improved.
Disclosure of Invention
According to one aspect of one or more embodiments of the present disclosure, a method for designing a high-power radiation-resistant transistor chip is provided, which has a general process flow design and is beneficial to different production lines.
The disclosed method for designing a high-power radiation-resistant transistor chip comprises the following steps:
designing a transverse layout in a gridding manner, and setting relevant parameters of a base region, an emission region and a bonding region; the base region is divided into a deep base region and a light base region according to the electron diffusion concentration;
designing a longitudinal structure according to the performance requirements of preset parameters of the chip to obtain the junction depth of a collector junction and the junction depth of an emitter junction;
the following process procedures are sequentially carried out: the method comprises the following steps of primary oxidation, deep base region photoetching, deep base region diffusion, secondary oxidation, light base region photoetching, light base region diffusion, tertiary oxidation, emitter region photoetching, emitter region diffusion, quartic oxidation, lead hole photoetching, aluminum evaporation, aluminum reverse etching and alloy technology, and finally the high-power transistor chip with the preset radiation-resistant performance parameters is obtained.
In one or more embodiments, the light base region is not as large in area during the design of the lateral layoutAt 4.99X 10 - 2 cm 2 The junction capacitance of the radiation-resistant transistor is not more than 120pF.
The beneficial effects produced by the method are as follows: the parameter requirement of the device is guaranteed to be 120pF, and if the area exceeds the value, the capacitance does not meet the requirement certainly.
In one or more embodiments, the emitter region is no greater than 3.58 x 10 during the design of the landscape layout -2 cm 2 The maximum current is 5A, the maximum frequency is 75MHz, and the minimum circumference of the emitting area is 38208 μm.
The beneficial effects of it are: on the premise of ensuring the maximum current 5A, the perimeter of the emitting area is enlarged, so that the area is enlarged, but the maximum frequency is 75MHz, and the maximum frequency cannot be infinitely increased, so that the area and the perimeter of the emitting area are limited.
In one or more embodiments, in the process of designing the transverse layout, the bonding region includes a base bonding point and an emitter bonding point, and both the base bonding point and the emitter bonding point are not less than 3.882 × 10 -3 cm 2 。
The beneficial effects of it are: the two bonding points are not less than the value, the chip mainly considers that the chip requires a circuit of 5A, and the thickness of a bonding wire required by future packaging is not less than the value because the thickness of the bonding wire is required to bear current.
In one or more embodiments, the line width designs a maximum line width of 2 μm in the process of designing the lateral layout.
The beneficial effects of it are: the line width is considered by considering the actual process state of the current manufacturers, and similar products can be basically produced by the line width of 2 um.
In one or more embodiments, in designing the longitudinal structure, the epitaxial wafer material selects a low-resistance silicon single crystal wafer with < 111 > as a crystal orientation and a resistivity of 0.001 Ω · cm to 0.002 Ω · cm as a substrate, and a silicon wafer grown with an epitaxial layer having a thickness of 45 μm to 51 μm and a resistivity ρ =30 Ω · cm to 40 Ω · cm as a material for die fabrication.
The beneficial effects of it are: the epitaxial wafer is selected mainly by considering the requirements of high back pressure 400V and large current 5A of the device, and firstly, the parameters of the substrate need to be required to be smaller in resistivity and smaller in influence parameters. The breakdown voltage of the device is mainly considered in the epitaxial layer, and the value is obtained through theoretical calculation.
In one or more embodiments, the collector junction depth is up to 10 μm during the design of the longitudinal structure.
In one or more embodiments, the emitter junction depth is up to 2 μm in designing the longitudinal structure.
Wherein, the junction depth of the collector junction and the junction depth of the emitter junction can be calculated by the prior empirical formula.
In one or more embodiments, the primary oxidation temperature is 1100-1180 ℃, the oxygen flow is 3-5L/min, the hydrogen is 3-5L/min, and the time is 65-75 min.
The beneficial effects of it are: a masking layer is provided for the deep base region as a base diffusion.
In one or more embodiments, the rotation speed of the deep base region photoetching, the light base region photoetching, the emitter region photoetching, the pin hole photoetching and the aluminum back-etching photoresist is not less than 3500 r/min, and the exposure time is not less than 30s.
Wherein, deep base region photoetching: for making a rich base region window;
light base region photoetching: for making a thin base region window;
and (3) photoetching an emitting region: for making the emitter window;
and (3) photoetching of a lead hole: for making an extraction electrode window;
aluminum reverse etching: for making metal electrode shapes.
In one or more embodiments, the diffusion temperature of the deep basal region is 950 ℃ to 1000 ℃, the nitrogen flow rate is 8L/min to 12L/min, and the time is 25min to 35min.
This step is used to form the deep base region.
In one or more embodiments, the secondary oxidation temperature is 1100-1150 ℃, the oxygen flow is 3-5L/min, the hydrogen is 3-5L/min, and the time is 280-330 min.
This step is used for light base region diffusion and provides a masking film for light base region diffusion.
In one or more embodiments, the diffusion temperature of the dilute base region is 940-950 ℃, the nitrogen flow is 8-12L/min, and the time is 15-25 min.
This step is used to form the light base region and form the collector junction.
In one or more embodiments, the tertiary oxidation temperature is 1100-1150 ℃, the oxygen flow is 3-5L/min, the hydrogen is 3-5L/min, and the time is 250-300 min.
This step is used to provide a masking film for the emitter diffusion.
In one or more embodiments, the diffusion temperature of the emitting area is 920-950 ℃, the nitrogen flow is 6-8L/min, and the time is 15-25 min.
This step is used to form the emitter region and emitter junction.
In one or more embodiments, the quartic oxidation temperature is 950 ℃ to 1050 ℃, the oxygen flow is 9L/min to 10L/min, the hydrogen flow is 5L/min to 6L/min, and the time is 50 min to 70min.
Four oxidations of this step: the extraction electrode is provided with a masking film.
In one or more embodiments, the evaporation voltage and evaporation rate of the evaporated aluminum vacuum degree are 5-6 KV
Evaporation thickness->
This step is used to provide a metal electrode.
In one or more embodiments, the alloy temperature is 610-810 ℃, the oxygen flow is 3-4L/min, the nitrogen flow is 3-3L/min, the hydrogen flow is 3-3L/min, and the time is 35-40 min.
This step is used to achieve ohmic contact of the metal to the silicon.
Another aspect of the disclosure provides a chip.
The chip is designed by adopting the method for designing the high-power radiation-resistant transistor chip.
Compared with the prior art, the beneficial effect of this disclosure is:
(1) The method for designing the high-power radiation-resistant transistor chip has the advantages of universal process flow design and convenience for processing and producing the high-power radiation-resistant transistor chip on different production lines.
(2) The chip obtained by the method for designing the high-power radiation-resistant transistor chip can enable the radiation-resistant index of the high-power transistor to reach 100krad (Si), and the lowest dose rate is as follows: 0.01rad (si)/s.
(3) The chip obtained by the method for designing the high-power radiation-resistant transistor chip has simple and modularized structural design, and provides a solution for the radiation-resistant structural design of a high-power device.
Drawings
The accompanying drawings, which are included to provide a further understanding of the disclosure, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure and are not to be construed as limiting the disclosure.
FIG. 1 is a schematic diagram of a chip;
FIG. 2 is a schematic diagram of a deep base region of a chip;
FIG. 3 is a schematic diagram of a thin base region of a chip;
FIG. 4 is a schematic diagram of an emitter region of a chip;
FIG. 5 is a schematic view of a wire hole of a chip;
FIG. 6 is a schematic diagram of an aluminum layer of a chip;
fig. 7 (a) is a schematic diagram of a first bonding site of a chip;
fig. 7 (b) is a schematic diagram of a second bonding point of the chip.
Detailed Description
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
Term interpretation section:
(1) Bonding zone
A charge density concentration region between the bonding atoms. In this region, the accumulation of electron charges causes the electrons to be attracted to multiple nuclei simultaneously to form chemical bonds.
(2) Base region
The base region is an important area in a Bipolar Junction Transistor (BJT) structure. The BJT is formed by two back-to-back pn junctions, and the common region between the two pn junctions is the base region. The base width must be small (less than the diffusion length of minority carriers in the base) to form a useful transistor, otherwise the amplification performance is too poor (which is also beneficial for increasing frequency and speed); at the same time, the doping concentration of the base region must be less than that of the emitter region, otherwise the same performance is poor (but the doping concentration of the base region cannot be too low, otherwise the performance such as frequency, speed and noise is affected).
(3) The BJT triode comprises an emitter e, a collector c and a base b, and the corresponding impurity regions of the emitter e, the collector c and the base b are respectively called an emitter region, a collector region and a base region. And the PN junction between the emitter region and the base region is called an emitter junction, and the PN junction between the collector region and the base region is called a collector junction.
The triode is formed by manufacturing two PN junctions which are very close to each other on a semiconductor substrate, the positive semiconductor is divided into three parts by the two PN junctions, the middle part is a base region, the two side parts are an emitter region and a collector region, the arrangement modes include a PNP mode and an NPN mode, corresponding electrodes are led out from the three regions, and the electrodes are respectively a base electrode b, an emitter electrode e and a collector electrode c.
The PN junction between the emitter region and the base region is called an emitter junction, and the PN junction between the collector region and the base region is called a collector electrode. The base region is very thin, the emitter region is thicker, the impurity concentration is high, a cavity is emitted from the emitter region of the PNP type triode, the moving direction of the cavity is consistent with the current direction, and therefore the arrow of the emitter faces inwards; the emitting region of the NPN type triode emits free electrons, the moving direction of the free electrons is opposite to the current direction, and therefore an emitter arrow faces outwards. The emitter arrows face outward. The emitter arrow points in the direction of conduction of the PN junction also at forward voltage. The silicon crystal triode and the germanium crystal triode are both of PNP type and NPN type.
A light base region: in general, a light base region is required for diffusion in a transistor.
(4) A high-power transistor: refers to a transistor that operates under high voltage, high current conditions. Generally called power devices, and belongs to the research category in the field of power electronic technology (power electronic technology). The essence of the method is to effectively control the power electronic device to reasonably work and provide high-power output for a load through the power electronic device.
The disclosed method for designing high-power radiation-resistant transistor chip includes:
designing a transverse layout in a gridding manner, and setting relevant parameters of a base region, an emitter region and a bonding region; the base region is divided into a deep base region and a light base region according to the electron diffusion concentration;
designing a longitudinal structure according to the performance requirements of preset parameters of the chip to obtain the junction depth of a collector junction and the junction depth of an emitter junction;
the following process procedures are sequentially carried out: the method comprises the following steps of primary oxidation, deep base region photoetching, deep base region diffusion, secondary oxidation, light base region photoetching, light base region diffusion, tertiary oxidation, emitter region photoetching, emitter region diffusion, quartic oxidation, pin hole photoetching, aluminum evaporation, aluminum reverse etching and alloy process, and finally obtaining a high-power transistor chip with preset radiation-resistant performance parameters, and obtaining the chip structure shown in figure 1.
Wherein, primary oxidation: providing a masking layer for base diffusion;
deep base region photoetching: for making a rich base region window;
light base region photoetching: for making a thin base region window;
and (3) photoetching an emitting region: for making the emitter window;
photoetching a lead hole for manufacturing an extraction electrode window;
aluminum reverse etching: for making metal electrode shapes;
deep base region diffusion: for forming a deep base region;
secondary oxidation: providing a masking film for light base region diffusion;
diffusion of a light base region: forming a light base region and a collector junction;
third oxidation: for providing a masking film for the emitter region diffusion;
diffusion of an emitting region: for forming an emitter region and an emitter junction;
four times of oxidation: for providing a masking film for the extraction electrode;
and (3) aluminum steaming: for providing a metal electrode;
alloy: for achieving ohmic contact of the metal and the silicon.
Wherein, the deep base region is as shown in fig. 2, in order to better form a circuit channel, the high-power device realizes the good contact of the base region in the range of the light base region, and a large amount of deeper deep base region rods are manufactured to realize the good contact.
In one or more embodiments, in designing a landscape layout, as shown in FIG. 3. The area of the light base region is not more than 4.99 multiplied by 10 -2 cm 2 The junction capacitance of the radiation-resistant transistor is not greater than 120pF.
The beneficial effects produced by the method are as follows: the parameter requirement of the device is guaranteed to be 120pF, and if the area exceeds the value, the capacitance does not meet the requirement certainly.
In one or more embodiments, during the design of the landscape layout, as shown in FIG. 4, the emission area is no greater than 3.58 × 10 -2 cm 2 The maximum current is 5A, the maximum frequency is 75MHz, and the minimum circumference of the emitting area is 38208 μm.
The beneficial effects of it are: on the premise of ensuring the maximum current 5A, the perimeter of the emitting area is enlarged, so that the area is enlarged, but the maximum frequency is 75MHz, and the maximum frequency cannot be infinitely increased, so that the area and the perimeter of the emitting area are limited.
In one or more embodiments, during the design of the lateral layout, the bonding regions include a base bonding point and an emitter bonding point, the base bonding point andthe bonding points of the emitter region are not less than 3.882 multiplied by 10 -3 cm 2 As shown in fig. 7 (a) and 7 (b).
The beneficial effects of it are: the two bonding points are not less than the value, the circuit of 5A is mainly considered, and the bonding wire thickness bearing current capacity required by packaging in the future is mainly considered, so the value is not required to be less than the value.
In one or more embodiments, the line width designs a maximum line width of 2 μm in the process of designing the lateral layout.
The beneficial effects of it are: the line width is considered by considering the actual process state of the current manufacturers, and similar products can be basically produced by the line width of 2 um.
In one or more embodiments, in designing the longitudinal structure, the epitaxial wafer material selects a low-resistance silicon single crystal wafer with < 111 > as a crystal orientation and a resistivity of 0.001 Ω · cm to 0.002 Ω · cm as a substrate, and a silicon wafer grown with an epitaxial layer having a thickness of 45 μm to 51 μm and a resistivity ρ =30 Ω · cm to 40 Ω · cm as a material for die fabrication.
The beneficial effects of it are: the epitaxial wafer is selected mainly by considering the requirements of high back pressure 400V and large current 5A of the device, and firstly, the parameters of the substrate need to be required to be smaller in resistivity and smaller in influence parameters. The breakdown voltage of the device is mainly considered in the epitaxial layer, and the value is obtained through theoretical calculation.
In one or more embodiments, the collector junction depth is 10 μm at the maximum during the design of the vertical structure.
In one or more embodiments, the emitter junction depth is up to 2 μm in designing the longitudinal structure.
Wherein, the collector junction depth and the emitter junction depth can be calculated by the prior empirical formula.
In one or more embodiments, the primary oxidation temperature is 1100-1180 ℃, the oxygen flow is 3-5L/min, the hydrogen is 3-5L/min, and the time is 65-75 min.
The beneficial effects of it are: a masking layer is provided for the deep base region as a base diffusion.
In one or more embodiments, the rotation speed of deep base region photoetching, light base region photoetching, emitter region photoetching, lead hole photoetching and aluminum reverse etching spin-coating is not less than 3500 r/min, and the exposure time is not less than 30s.
The lead hole of the chip is schematically shown in fig. 5; a schematic of the aluminum layer of the chip is shown in fig. 6.
Wherein, deep base region photoetching: for making a rich region window;
light base region photoetching: for fabricating a thin base region window;
and (3) photoetching an emitting region: for manufacturing an emitter window;
and (3) photoetching of a lead hole: for making an extraction electrode window;
aluminum reverse etching: for making metal electrode shapes.
In one or more embodiments, the deep basal zone diffusion temperature is 950 ℃ to 1000 ℃, the nitrogen flow is 8L/min to 12L/min, and the time is 25min to 35min.
This step is used to form the deep base region.
In one or more embodiments, the secondary oxidation temperature is 1100-1150 ℃, the oxygen flow is 3-5L/min, the hydrogen is 3-5L/min, and the time is 280-330 min.
This step is used for light base region diffusion and provides a masking film for light base region diffusion.
In one or more embodiments, the diffusion temperature of the thin base region is 940-950 ℃, the nitrogen flow is 8-12L/min, and the time is 15-25 min.
This step is used to form a light base region and form a collector junction.
In one or more embodiments, the tertiary oxidation temperature is 1100-1150 ℃, the oxygen flow is 3-5L/min, the hydrogen is 3-5L/min, and the time is 250-300 min.
This step is used to provide a masking film for the emitter region diffusion.
In one or more embodiments, the diffusion temperature of the emitting area is 920-950 ℃, the nitrogen flow is 6-8L/min, and the time is 15-25 min.
This step is used to form the emitter region and emitter junction.
In one or more embodiments, the fourth oxidation temperature is 950-1050 ℃, the oxygen flow is 9-10L/min, the hydrogen is 5-6L/min, and the time is 50-70 min.
Four oxidations of this step: the extraction electrode is provided with a masking film.
In one or more embodiments, the evaporation voltage and evaporation rate of the evaporated aluminum vacuum degree are 5-6 KV
Evaporation thickness->
This step is used to provide a metal electrode.
In one or more embodiments, the alloy temperature is 610-810 ℃, the oxygen flow is 3-4L/min, the nitrogen flow is 3-3L/min, the hydrogen flow is 3-3L/min, and the time is 35-40 min.
This step is used to achieve ohmic contact of the metal to the silicon.
Test data parameters:
wherein, BVCEO: open base, collector-emitter reverse breakdown voltage.
BVCBO: the emitter is open and the collector-base reverse breakdown voltage.
VCESAT: the saturation value of the voltage across the collector-emitter of the bipolar transistor.
VBESAT: the saturation value of the voltage across the base-emitter of the bipolar transistor.
ICBO: the collector electrode reverse saturates the current.
HFE: (H: hybrid; F: forward; E: common emitter) is actually the current amplification factor of the triode.
VCEmax: maximum value of the voltage across the collector-emitter.
VEBmax: maximum value of the voltage across the emitter-base.
VCB: collector-voltage across the base.
IC: the emitter current.
IB: the base current.
ICE: collector-emitter current.
IEB: the current flows between the emitter and the base.
ICES: the base electrode and the emitter electrode are in short circuit, and reverse leakage current is generated between the emitter electrode and the collector electrode.
The chip obtained by the method for designing the high-power radiation-resistant transistor chip can enable the radiation-resistant index of the high-power transistor to reach 100krad (Si), and the lowest dose rate is as follows: 0.01rad (si)/s.
The method for designing the high-power radiation-resistant transistor chip has the advantages of universal process flow design and convenience for processing and producing the high-power radiation-resistant transistor chip on different production lines.
In another aspect of the disclosure, a chip is provided.
The chip is designed by adopting the method for designing the high-power radiation-resistant transistor chip.
The chip obtained by the method for designing the high-power radiation-resistant transistor chip has simple and modularized structural design, and provides a solution for the radiation-resistant structural design of a high-power device.
Although the present disclosure has been described with reference to specific embodiments, it should be understood that the scope of the present disclosure is not limited thereto, and those skilled in the art will appreciate that various modifications and changes can be made without departing from the spirit and scope of the present disclosure.
Claims (2)
1. A method for designing a high-power radiation-resistant transistor chip is characterized by comprising the following steps:
designing a transverse layout in a gridding manner, and setting relevant parameters of a base region, an emitter region and a bonding region; the base region is divided into a deep base region and a light base region according to the electron diffusion concentration;
designing a longitudinal structure according to the performance requirements of preset parameters of the chip to obtain the junction depth of a collector junction and the junction depth of an emitter junction;
the following process procedures are sequentially carried out: carrying out primary oxidation, deep base region photoetching, deep base region diffusion, secondary oxidation, light base region photoetching, light base region diffusion, tertiary oxidation, emitter region photoetching, emitter region diffusion, quaternary oxidation, lead hole photoetching, aluminum evaporation, aluminum reverse etching and alloy technology to finally obtain a high-power transistor chip with preset radiation-resistant performance parameters;
in the process of designing transverse layout, the area of the light base region is not more than 4.99 multiplied by 10 -2 cm 2 The junction capacitance of the radiation-resistant transistor is not more than 120pF;
the emission area is not more than 3.58 x 10 -2 cm 2 The maximum current is 5A, the maximum frequency is 75MHz, and the minimum circumference of the emitting region is 38208 mu m;
the bonding region comprises a base bonding point and an emitter bonding point, and the base bonding point and the emitter bonding point are not less than 3.882 x 10 -3 cm 2 ；
Designing the maximum line width of 2 mu m for the line width;
in the process of designing a longitudinal structure, selecting a low-resistance silicon single crystal wafer with the crystal orientation less than 111 and the resistivity of 0.001-0.002 omega-cm as an epitaxial wafer material as a substrate, and growing a silicon wafer with an epitaxial layer with the thickness of 45-51 mu m and the resistivity of rho = 30-40 omega-cm as a material for manufacturing a tube core;
in the process of designing the longitudinal structure, the junction depth of the collector is 10 μm at most; the maximum junction depth of the emitter is 2 mu m;
the primary oxidation temperature is 1100-1180 ℃, the oxygen flow is 3-5L/min, the hydrogen is 3-5L/min, and the time is 65-75 min;
the secondary oxidation temperature is 1100-1150 ℃, the oxygen flow is 3-5L/min, the hydrogen is 3-5L/min, and the time is 280-330 min;
the tertiary oxidation temperature is 1100-1150 ℃, the oxygen flow is 3-5L/min, the hydrogen is 3-5L/min, and the time is 250-300 min;
the fourth oxidation temperature is 950-1050 ℃, the oxygen flow is 9-10L/min, the hydrogen is 5-6L/min, and the time is 50-70 min;
the alloy temperature is 610-810 ℃, the oxygen flow is 3-4L/min, the nitrogen flow is 3-3L/min, the hydrogen is 3-3L/min, and the time is 35-40 min;
the rotating speed of deep base region photoetching, light base region photoetching, emitter region photoetching, pin hole photoetching and aluminum reverse-etching spin-coating is not less than 3500 revolutions/min, and the exposure time is not less than 30s;
wherein, deep base region photoetching is used for manufacturing a thick base region window; the light base region photoetching is used for manufacturing a light base region window; emitter region lithography is used to make emitter region windows; lead hole photoetching is used for manufacturing an extraction electrode window; aluminum reverse etching is used for manufacturing metal electrode shapes;
forming a deep base region: the diffusion temperature of the deep base region is 950-1000 ℃, the nitrogen flow is 8-12L/min, and the time is 25-35 min;
and forming a collector junction: the diffusion temperature of the light base region is 940-950 ℃, the nitrogen flow is 8-12L/min, and the time is 15-25 min;
and (3) forming an emitter junction: the diffusion temperature of the emission area is 920-950 ℃, the nitrogen flow is 6-8L/min, and the time is 15-25 min;
and (3) forming a metal electrode: evaporating voltage of 5-6 KV and evaporating speed
Evaporation thickness->
2. A chip, which is designed by the method of claim 1.
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