JP3146024B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a semiconductor element suitable for high-speed operation.

[0002]

2. Description of the Related Art A conventional semiconductor device having a bipolar transistor is a physics of semiconductor.
Devices 2nd Edition, S.M.S.S., by John Willy and Sun, p.146 (Physics of Sem
iconductor Devices, 2ndEdition, S.M. M. Sze, John Wi
ley & Sons, Inc. p. 146). FIG. 2A shows the structure of this bipolar transistor. That is, this bipolar transistor is provided with a high-concentration n-type emitter region 1, a p-type base region 2, an n-type collector region 3, and a high-concentration n-type collector region 4 from the front side, and
Construct a transistor. FIG. 2 shows the impurity distribution.
(B). The impurity concentration 1 'of the high-concentration n-type emitter region, the impurity concentration 2' of the p-type base region, the impurity concentration 3 'of the n-type collector region, and the impurity concentration 4' of the high-concentration n-type collector region are respectively distributions as shown in the figure. have.

[0003]

In the prior art described above, when the width of the p-type base region 2 is reduced in order to increase the speed of the transistor, when the reverse bias is applied to the collector-base junction, the p-type base neutral The region disappears, and a punch-through phenomenon occurs in which a short circuit occurs between the collector and the emitter. This causes a problem that it is difficult to reduce the width of the p-type base region 2 and hinder high-speed operation. Generally, according to the scaling rule, in order to prevent punch-through, when the width of the p-type base region 2 is reduced to 1 / a, the carrier concentration of the p-type base region 2 needs to be increased by a ² times. . However, this scaling rule cannot be applied to the high-concentration n-type emitter region 1. This is because the carrier concentration of the high-concentration n-type emitter region 1 is already at the upper limit, and the high-concentration n-type emitter region 1 is made shallow as in the case of the p-type base region 2 for speeding up. This is because the total number of carriers in the emitter region 1 tends to decrease. For this reason, simply increasing the carrier concentration of the p-type base region 2 in accordance with the scaling law causes a decrease in current gain.
The carrier concentration in the p-type base region 2 cannot be increased, so that the reduction in the width of the p-type base region 2 is restricted, which hinders an increase in speed.

An object of the present invention is to provide a semiconductor device having a semiconductor element suitable for high-speed operation.

[0005]

[MEANS FOR SOLVING THE PROBLEMS] To achieve the above object
In addition, the semiconductor device of the present invention comprises a semiconductor layer of the first conductivity type.
And a first region provided on both sides of the first region.
From a semiconductor layer of a second conductivity type opposite to the first conductivity type.
Second region and third region, and at least the first region
Do not generate carriers that contribute to conductivity provided in part.
Fourth region of the first conductivity type having deep level impurity ions
And the impurity ion concentration at the deep level in the fourth region is
This is higher than the carrier concentration in the first region. this
Preferably, a plurality of fourth regions are provided in the first region.
Good. In this semiconductor device, the first region is defined as a base region.
And one of the second and third regions is a collector region and the other is an air region.
Configure a bipolar transistor as the emitter area.
Can be. Further, in order to achieve the above object, the present invention
Is a semiconductor device of the first conductivity type on a semiconductor substrate.
A base region comprising a layer and a second region having a conductivity type opposite to the first conductivity type.
A bar comprising a collector region and an emitter region of two conductivity type.
Provision of an bipolar transistor and carrier in the base region
To generate impurities and carriers that contribute to conductivity.
And deep level impurity ions that do not form.
Impurity concentration to generate carriers
It is made to be higher than the substance concentration. This deep associate
Impurity ions are present in a part of the base region.
Is preferred. In order to achieve the above objectives,
The semiconductor device of the present invention comprises a first semiconductor layer of a first conductivity type,
A second semiconductor layer of a second conductivity type having a conductivity type opposite to the conductivity type;
A third semiconductor layer of two conductivity type, wherein the first semiconductor layer is
A first semiconductor located between the second semiconductor layer and the third semiconductor layer;
At least a part of the layer is provided with a carrier for generating carriers.
Including pure and unactivated impurity ions
Generates carriers with inactive impurity ion concentration
The impurity concentration is higher than that for

[0006]

The operation of the semiconductor device according to one embodiment of the present invention will be described.
Since the fourth region having the deep-level impurity ions suppresses the width of the depletion layer extending to the first region when a reverse bias is applied to the junction, the loss of the p-type base neutral region can be prevented.
Since the width of the first region can be reduced, the speed of the element can be increased.
Further, since the impurity ions at the deep level in the fourth region do not generate carriers that contribute to conduction, the number of carriers in the first region does not increase, and the current gain can be maintained.

[0007]

Embodiments of the present invention will be described below in detail with reference to the drawings. Embodiment 1 FIG. 1A shows a one-dimensional structure diagram of a semiconductor device according to Embodiment 1 of the present invention. This semiconductor device has a bipolar transistor, and has a high concentration of n-type emitter region 1 and p-type base region 2 from the surface side, and deep-level impurity ions that are not activated, ie, do not generate carriers that contribute to conduction. By providing a p-type base region 22, an n-type collector region 3, and a high-concentration n-type collector region 4, an npn transistor is realized. FIG. 1B shows an impurity distribution diagram of this bipolar transistor. The impurity concentration 22 'of the p-type base region having deep-level impurity ions is higher than the impurity concentration 2' of the p-type base region, and is distributed substantially at the same position.

A method for manufacturing the transistor shown in FIG. 1 will be described below. First, the high concentration n-type collector region 4 of the carrier concentration of about 10 ¹⁹ cm ~ ³ is formed by diffusion from antimony glass, then the carrier concentration of about 5 × 10 ¹⁵ cm
~ ³ n-type collector regions 3 are formed by epitaxial growth. Thereafter, boron is added from the surface side by ion implantation to form a p-type base region 2 having a carrier concentration of about 10 ¹⁸ cm ³ . At this point, the p-type base region 22 having impurity ions of a deep level with an impurity concentration of about 5 × 10 ¹⁸ cm to ³ can be simultaneously formed by adding an impurity to the upper limit of the activation impurity concentration determined by the heat treatment temperature later. .
Next, arsenic is added by ion implantation and annealed,
A high-concentration n-type emitter region 1 having a carrier concentration of about 5 × 10 ²⁰ cm to ³ is formed, and the transistor shown in FIG. 1 is manufactured.

FIG. 3 shows a band structure diagram of the transistor when a bias is applied. The operation principle of the transistor of the present invention will be described with reference to FIG. The bias application conditions in this figure are for normal operation of the transistor. A forward bias V _BE is applied between the base and the emitter, and a reverse bias V _BC is applied between the base and the collector. The width of the depletion layer formed on the base region side by the reverse bias applied between the base and the collector is determined by the sum of the number of shallow level impurity ions 2i and the number of deep level impurity ions 22i.

On the other hand, carriers contributing to electrical operation in the base neutral region are holes 2h induced in the valence band by shallow level impurity ions 2i, and deep level impurity ions 22i are valence electrons. Does not induce holes in the band.
Therefore, the number of carriers in the base region is given by the number of shallow level impurity ions 2i, and the number of shallow level impurity ions 2i is set in accordance with the number of carriers in the emitter region. In order to prevent this, the number of impurity ions 22i having a deep level may be set. This makes it possible to achieve both current gain and breakdown voltage even if the width of the base region is reduced for speeding up.

Second Embodiment FIGS. 4A and 4B show a one-dimensional structure diagram and an impurity distribution diagram of a semiconductor device according to a second embodiment of the present invention. In this embodiment, p
Base region 2 having deep level impurity ions that do not generate carriers contributing to conduction in base region 2
2 is provided at the junction between the p-type base region 2 and the n-type collector region 3. In order to prevent punch-through between the collector and the emitter, the width of the depletion layer formed on the base region side may be suppressed by a reverse bias applied between the base and the collector. The effect was obtained.

Further, the high-concentration n-type emitter region 1 and p-type
Since there is no p-type base region 22 having a deep level impurity ion at the junction of the base region 2, the width of the depletion layer at the emitter-base junction is maintained, and unnecessary base current due to generation of tunnel current is maintained. Can be prevented from increasing, and a stable current gain can be obtained up to a low current region. The p-type base region 22 having deep level impurity ions was formed by adding ions to the junction between the p-type base region 2 and the n-type collector region 3 by ion implantation.

Third Embodiment FIGS. 5A and 5B show a one-dimensional structure diagram and an impurity distribution diagram of a semiconductor device according to a third embodiment of the present invention. In this embodiment, p
Base region 2 having deep level impurity ions that do not generate carriers contributing to conduction in base region 2
2 are provided. Thus, even if the impurity ion concentration at the deep level in each p-type base region 22 is reduced, the width of the depletion layer formed on the base region side by the reverse bias applied between the base and the collector can be suppressed. −
Punch through between emitters can be prevented. That is, if impurity ions of an excessively deep level are added to an extent that the impurity concentration exceeds the limit of solid solubility, there is a risk that a crystal defect occurs and a short circuit occurs between the collector and the emitter.
By dividing the p-type base region 22 having deep-level impurity ions into a plurality as shown in this embodiment, generation of crystal defects can be prevented. Note that the emitter-
Unless a p-type base region 22 having a deep level impurity ion is provided in the vicinity of the base junction, an unnecessary increase in base current due to generation of a tunnel current can be prevented, and a stable current gain can be obtained up to a low current region. it can. As a method for providing a plurality of p-type base regions 22 having deep-level impurity ions, an ion implantation method with different acceleration energies was used. This region can also be formed by using an epitaxial growth method in which the impurity concentration is controlled.

Fourth Embodiment FIG. 6 is a sectional view of a semiconductor device according to a fourth embodiment of the present invention.
In this embodiment, a p-type base region 22 having a deep level impurity ion that does not generate carriers contributing to conduction is provided near the base-collector junction in the low-concentration intrinsic p-type base region 2. Thereby, the intrinsic p-type base region 2 can be made thinner, and the speed of the transistor can be increased. In this embodiment, a region having a deep level of impurity ions is not provided in the high-concentration external base region 25 to prevent a reduction in avalanche breakdown voltage at the external base-collector junction. The structure does not increase the junction capacitance.

A method for manufacturing the semiconductor device will be described. Arsenic ions are added to the substrate 100 by ion implantation to form a high concentration n-type collector region 4. In this case, a mask having a desired pattern is used. The same applies to the use of a mask during ion implantation. An n-type collector region 3 is formed by growing an epitaxial layer containing phosphorus. Silicon nitride (not shown) is deposited, opened using a photoresist pattern, and oxidized to form a silicon oxide film 200 on this portion. Next, 1 phosphorus ion
A high-concentration n-type collector extraction layer 50 containing 0 ²⁰ cm to ³ is formed by ion implantation, a high-concentration p-type base region 25 containing 10 ¹⁹ cm to ³ boron is formed, and ion implantation and heat treatment at 800 ° C. , p type base region 22 having an impurity ion of deep levels of boron containing 5 × 10 ¹⁸ cm ~ ³
And boron to form a 1 × 10 ¹⁸ cm ~ p-type base region 2 containing ^3, further formed by arsenic 10 ²¹ cm ~ a high concentration n-type emitter region 1 ion implantation including ^3. Thereafter, an electrode, an insulating film and the like are formed as usual to obtain a semiconductor layer device.

Fifth Embodiment FIG. 7 is a sectional view of a semiconductor device according to a fifth embodiment of the present invention.
In this embodiment, the base region is extended by the polysilicon layer 250, and the external base region is miniaturized to reduce the external base-collector junction capacitance. The p-type base region 22 having the deep level impurity ions is provided at a depth of about 0.1 μm from the surface, and the high-concentration n-type emitter region 1 is formed.
Was formed by thermal diffusion of arsenic at 800 ° C. from the polycrystalline silicon layer 110. In the figure, reference numeral 201 denotes a silicon oxide film, and reference numerals 1001, 1002, and 1003 denote electrodes.

The speeding up of the transistor is realized by reducing the junction capacitance and improving the cutoff frequency. When the junction capacitance is reduced as in this embodiment, p-type impurity ions having a deep level of impurity ions which do not generate carriers contributing to conduction are obtained. The contribution to speeding up the thinning of the intrinsic p-type base region 2 made possible by the provision of the base region 22 becomes even more remarkable. In this embodiment, the high-concentration n-type emitter region 1
Is formed so that the contribution of the p-type base region 22 having deep-level impurity ions to the high-speed operation becomes more remarkable.

Embodiment 6 FIG. 8 is a sectional view of a semiconductor device according to Embodiment 6 of the present invention.
In the present embodiment, the base region is led out by the polycrystalline silicon layer 250 provided on the side surface of the active region in a self-aligned manner.
The external base region is miniaturized to reduce the external base-collector junction capacitance. In addition, an insulator layer 300 reaching the p-type substrate 100 is provided for isolation between elements to reduce the junction capacitance between the collector and the substrate. Further, a metal (or a metal compound) 210 is provided on the upper surface and the side surface of the polycrystalline silicon layer 250 to reduce the resistance at the lead portion of the base region. By using this structure,
The contribution to speeding up the thinning of the intrinsic p-type base region 2 made possible by the provision of the p-type base region 22 having a deep level impurity ion that does not generate carriers contributing to conduction is more remarkable. Become.

Seventh Embodiment FIG. 9 is a sectional view of a semiconductor device according to a seventh embodiment of the present invention.
In the present embodiment, an n-type emitter region 1, a p-type base region 2, an n-type collector region 3, and a high-concentration n are formed on an insulating substrate 400 made of silicon oxide provided on a support substrate 500.
The provision of the collector region 4 reduces the parasitic capacitance and increases the speed. This semiconductor device was manufactured as follows. A silicon oxide film 401 is formed on the insulating substrate 400 by thermal oxidation using a photoresist pattern, and a high-concentration n-type collector region 4 containing 1 × 10 ¹⁹ cm ^{3 of} arsenic is formed by ion implantation. Two p-type base regions 22 having deep-level impurity ions are provided by ion implantation in which the ion beam is narrowed down, and the whole of the p-type base region 2 including this region is implanted to form this region. The respective impurity concentrations are the same as in the fourth embodiment. Next, the n-type emitter region 1 is implanted by arsenic ion implantation.
Was formed. The base width was 0.2 μm.

This embodiment shows an example in which two p-type base regions 22 having deep-level impurity ions which do not generate carriers contributing to conduction are provided. In this transistor structure, isolation between elements is easy, miniaturization is possible, and a p-type base region 22 having a deep-level impurity ion that does not generate carriers contributing to conduction is provided to make the intrinsic p-type base region 2 thin. Stratification, speeding up became more effective.

In each of the above embodiments, G is used as the semiconductor.
The semiconductor device of the present invention can be realized by using other semiconductors such as aAs. In addition, it goes without saying that the p-type and n-type conductivity types in each embodiment can be used in reverse.

[0022]

According to the present invention, a semiconductor device having a semiconductor element suitable for high-speed operation can be provided.

[Brief description of the drawings]

FIG. 1 shows a one-dimensional structure diagram and an impurity distribution diagram of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 shows a one-dimensional structure diagram and an impurity distribution diagram of a conventional semiconductor device.

FIG. 3 is a band structure diagram when a bias is applied to the semiconductor device according to the first embodiment of the present invention.

FIG. 4 shows a one-dimensional structure diagram and an impurity distribution diagram of a semiconductor device according to a second embodiment of the present invention.

FIG. 5 shows a one-dimensional structure diagram and an impurity distribution diagram of a semiconductor device according to a third embodiment of the present invention.

FIG. 6 is a sectional view of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 7 is a sectional view of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 8 is a sectional view of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 9 is a sectional view of a semiconductor device according to a seventh embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 high-concentration n-type emitter region 1 ', 2', 3 ', 4', 22 'impurity concentration 2 p-type base region 2i shallow-level impurity ions 2h holes induced in valence band 3 n-type collector region 4 High-concentration n-type collector region 22 P-type base region having deep-level impurity ions 22i Deep-level impurity ions 25 High-concentration p-type base region 50 High-concentration n-type collector extraction layer 100 Substrate 110, 250 Polycrystalline silicon Layer 200, 201, 401 Silicon oxide film 210 Metal 300 Insulator layer 400 Insulating substrate 500 Supporting substrate 1001, 1002, 1003 Electrode

Claims (6)

(57) [Claims] A first region comprising a semiconductor layer of a first conductivity type, and a semiconductor layer of a second conductivity type opposite to the first conductivity type provided on both sides of the first region with the first region interposed therebetween. A second region, a third region, and a fourth region of a first conductivity type, which is provided in at least a part of the first region and has deep-level impurity ions that do not generate carriers contributing to conduction. Then, the impurity ion concentration at the deep level in the fourth region is equal to the first level.
A semiconductor device having a higher carrier concentration than a region . 2. The semiconductor device according to claim 1, wherein a plurality of said fourth regions are provided in said first region . 3. The semiconductor device according to claim 1, wherein said first region is a base region, and said second and third regions are base regions.
One as a collector region and the other as an emitter region.
A semiconductor device comprising a polar transistor . 4. A semiconductor layer of a first conductivity type on a semiconductor substrate.
A base region, a collector region of a second conductivity type opposite to the first conductivity type, and
Bipolar transistor consisting of
In the semiconductor device described above, the base region contains impurities for generating carriers.
Deep-level impurities that do not generate carriers that contribute to conduction
And the above-mentioned deep level impurity ion concentration generates the above-mentioned carriers.
Semiconductor having an impurity concentration higher than that of
apparatus. 5. The semiconductor device according to claim 4, wherein said deep-level impurity ions form part of said base region.
A semiconductor device, wherein the semiconductor device exists in a minute . 6. A first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type having a conductivity type opposite to the first conductivity type.
And a third semiconductor layer of a second conductivity type, wherein the first semiconductor layer comprises the second semiconductor layer and the third semiconductor layer.
At least one of the first semiconductor layers,
The part contains impurities and carriers for generating carriers.
Impurity ions that are not activated and the concentration of the non-activated impurity ions
Higher than the impurity concentration for generating
Semiconductor device.