CN110718545A - Low residual voltage ESD surge protection device with low-capacitance structure - Google Patents
Low residual voltage ESD surge protection device with low-capacitance structure Download PDFInfo
- Publication number
- CN110718545A CN110718545A CN201810761857.3A CN201810761857A CN110718545A CN 110718545 A CN110718545 A CN 110718545A CN 201810761857 A CN201810761857 A CN 201810761857A CN 110718545 A CN110718545 A CN 110718545A
- Authority
- CN
- China
- Prior art keywords
- region
- low
- tube
- protection device
- residual voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
- H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
- H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
Abstract
The invention discloses a low residual voltage ESD surge protection device with a low-capacitance structure, which comprises a capacitance reducing tube D1, a TVS tube D4, a Schottky tube D2, an NPN tube T1 and a forward capacitance reducing tube D3 which are connected in an electrical connection manner; wherein the capacitance reducing tube D3 provides a forward current path; d1 and T1 form a PNPN structure which is a main discharge channel; the TVS tube D4 provides a turn-on voltage. The invention has reasonable design, realizes the protection device with the unidirectional large snapback SCR structure, realizes the SCR structure protection device with the extremely low capacitance through a double-groove process, can meet the current low residual voltage protection requirement, and has the characteristics of low capacitance, low clamping, large surge current capacity and the like.
Description
Technical Field
The invention belongs to a semiconductor component device, and particularly relates to a low-residual-voltage ESD surge protection device with a low-capacitance structure.
Background
Longitudinal low residual voltage devices are limited by the structure of Zener + R2R due to process limitations, and residual voltage is difficult to reduce. As the signal port protection is weakened by the follow current problem, the SCR structure becomes the most effective way to reduce the residual voltage of the device, however, in order to realize the device of the unidirectional SCR structure, various processes are used to manufacture the protection device of the SCR structure, each of which has advantages that the process becomes very complicated in the forward direction of the device due to the use of the multilayer structure. The planar structure is relatively simple, but in order to obtain the breakdown voltage required to operate, the breakdown voltage has to be reduced by using a relatively low doping concentration, which makes it difficult to make the capacitance low.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a low-residual-voltage ESD surge protection device with a low-capacitance structure, which is reasonable in design, realizes a protection device with a unidirectional large snapback SCR structure, realizes an SCR structure protection device with an extremely low capacitance through a double-groove process, can meet the current low-residual-voltage protection requirement, and has the characteristics of low capacitance, low clamping, large surge current capacity and the like.
In order to achieve the purpose, the invention provides the following technical scheme:
the utility model provides a low residual voltage ESD surge protector of low-capacitance structure which characterized in that: the device comprises a capacity reducing tube D1, a TVS tube D4, a Schottky tube D2, an NPN tube T1 and a forward capacity reducing tube D3 which are connected in an electrical connection relationship; wherein the capacitance reducing tube D3 provides a forward current path; d1 and T1 form a PNPN structure which is a main discharge channel; the TVS tube D4 provides a turn-on voltage.
As an optimized technical scheme, the TVS tube consists of an N-type substrate, an N + expansion region and a P + expansion region from bottom to top in sequence, wherein the cathode of the TVS tube is the N + expansion region, and the N + expansion region is positioned in the center; the P + expansion region is used for manufacturing an anode of the TVS tube.
As an optimized technical scheme, the main discharge channel is composed of two substrate N + Deep regions, an N-Epi region, a P + base region and an N + emitter region from bottom to top in sequence; the two substrate N + Deep regions are arranged on two sides of the N-Epi region; the P + base region is positioned above the N + emitter region, and cathode short-circuit holes which can enable the gate electrode to have the same potential when the gate electrode is triggered are reserved at equal intervals around the center of the anode of the TVS tube.
The invention also provides a manufacturing process of the low residual voltage ESD surge protection device, which comprises the following steps:
the method comprises the following steps:
forming an N + buried layer region on the high-doped P + substrate material in an injection annealing mode; growing an epitaxial layer N-Epi, forming an N + Deep region through implantation annealing, and respectively forming an N + expansion region and a P + expansion region through an implantation annealing mode; and etching the Deep groove to form a groove, filling silicon dioxide in the groove, forming a mesa groove by a wet etching process, depositing a metal layer to form metal interconnection, and connecting the metal with the N + Deep region, the P + region and the N-Epi region of the substrate.
Due to the adoption of the technical scheme, compared with the prior art, the protection device of the one-way large snapback SCR structure is reasonable in design, the SCR structure protection device with the extremely low capacitance is realized through a double-groove process, the current low residual voltage protection requirement can be met, and the device has the characteristics of low capacitance, low clamping, large surge current capacity and the like.
The invention is further illustrated with reference to the figures and examples.
Drawings
FIG. 1 is a circuit schematic of one embodiment of the present invention;
fig. 2 is a schematic view of the overall structure of the finished product of one embodiment of the present invention.
Detailed Description
Examples
As shown in fig. 1, a low residual voltage ESD surge protection device with a low capacitance structure includes a capacitance reducing tube D1, a TVS tube D4, a schottky tube D2, an NPN tube T1, and a forward capacitance reducing tube D3 connected in an electrical connection relationship; wherein the capacitance reducing tube D3 provides a forward current path; d1 and T1 form a PNPN structure which is a main discharge channel; the TVS tube D4 provides a turn-on voltage.
The TVS tube consists of an N-type substrate, an N + expansion region and a P + expansion region from bottom to top in sequence, wherein the cathode of the TVS tube is the N + expansion region, and the N + expansion region is positioned in the center; the P + expansion region is used for manufacturing an anode of the TVS tube.
The main discharge channel is composed of two substrate N + Deep regions, an N-Epi region, a P + base region and an N + emitter region from bottom to top in sequence; the two substrate N + Deep regions are arranged on two sides of the N-Epi region; the P + base region is positioned above the N + emitter region, and cathode short-circuit holes which can enable the gate electrode to have the same potential when the gate electrode is triggered are reserved at equal intervals around the center of the anode of the TVS tube.
The device is a double-groove process device, the groove provides device isolation, and the groove is used for connecting the substrate, the N + IOS and the surface P + region. The device is an epitaxial low-capacitance device, and the N-Epi provides low-capacitance support for the device. The device is a one-way device, and can form a two-way and multi-way protection device through an array original package structure.
As shown in fig. 2, the manufacturing process of the low residual voltage ESD surge protection device is as follows: forming an N + buried layer region on the high-doped P + substrate material in an injection annealing mode; growing an epitaxial layer N-Epi, forming an N + Deep region through implantation annealing, and respectively forming an N + expansion region and a P + expansion region through an implantation annealing mode; and etching the Deep groove to form a groove, filling silicon dioxide in the groove, forming a mesa groove by a wet etching process, depositing a metal layer to form metal interconnection, and connecting the metal with the N + Deep region, the P + region and the N-Epi region of the substrate.
The invention has reasonable design, realizes the protection device with the unidirectional large snapback SCR structure, realizes the SCR structure protection device with the extremely low capacitance through a double-groove process, can meet the current low residual voltage protection requirement, and has the characteristics of low capacitance, low clamping, large surge current capacity and the like.
The protection scope of the present invention is not limited to the above embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may occur to those skilled in the art without departing from the principle of the invention, and are considered to be within the scope of the invention.
Claims (4)
1. The utility model provides a low residual voltage ESD surge protector of low-capacitance structure which characterized in that: the device comprises a capacity reducing tube D1, a TVS tube D4, a Schottky tube D2, an NPN tube T1 and a forward capacity reducing tube D3 which are connected in an electrical connection relationship;
wherein the capacitance reducing tube D3 provides a forward current path; d1 and T1 form a PNPN structure which is a main discharge channel; the TVS tube D4 provides a turn-on voltage.
2. The low residual voltage ESD surge protection device with low capacitance structure as claimed in claim 1, wherein: the TVS tube consists of an N-type substrate, an N + expansion region and a P + expansion region from bottom to top in sequence, wherein the cathode of the TVS tube is the N + expansion region, and the N + expansion region is positioned in the center; the P + expansion region is used for manufacturing an anode of the TVS tube.
3. The low residual voltage ESD surge protection device with low capacitance structure as claimed in claim 2, wherein: the main discharge channel is composed of two substrate N + Deep regions, an N-Epi region, a P + base region and an N + emitter region from bottom to top in sequence; the two substrate N + Deep regions are arranged on two sides of the N-Epi region; the P + base region is positioned above the N + emitter region, and cathode short-circuit holes which can enable the gate electrode to have the same potential when the gate electrode is triggered are reserved at equal intervals around the center of the anode of the TVS tube.
4. A low residual voltage ESD surge protection device with low capacitance structure as claimed in claim 3, wherein:
the manufacturing process of the low residual voltage ESD surge protection device comprises the following steps: forming an N + buried layer region on the high-doped P + substrate material in an injection annealing mode; growing an epitaxial layer N-Epi, forming an N + Deep region through implantation annealing, and respectively forming an N + expansion region and a P + expansion region through an implantation annealing mode; and etching the Deep groove to form a groove, filling silicon dioxide in the groove, forming a mesa groove by a wet etching process, depositing a metal layer to form metal interconnection, and connecting the metal with the N + Deep region, the P + region and the N-Epi region of the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810761857.3A CN110718545A (en) | 2018-07-12 | 2018-07-12 | Low residual voltage ESD surge protection device with low-capacitance structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810761857.3A CN110718545A (en) | 2018-07-12 | 2018-07-12 | Low residual voltage ESD surge protection device with low-capacitance structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110718545A true CN110718545A (en) | 2020-01-21 |
Family
ID=69209091
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810761857.3A Pending CN110718545A (en) | 2018-07-12 | 2018-07-12 | Low residual voltage ESD surge protection device with low-capacitance structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110718545A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20220360072A1 (en) * | 2021-05-07 | 2022-11-10 | Stmicroelectronics (Tours) Sas | Unidirectional transient voltage suppression device |
-
2018
- 2018-07-12 CN CN201810761857.3A patent/CN110718545A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20220360072A1 (en) * | 2021-05-07 | 2022-11-10 | Stmicroelectronics (Tours) Sas | Unidirectional transient voltage suppression device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101414005B1 (en) | Transient voltage suppressor and its manufacturing method | |
| CN205542793U (en) | Cascade switch structure | |
| US10566462B2 (en) | Bipolar semiconductor device and manufacturing method | |
| CN105470309A (en) | Low-voltage MOSFET device with antistatic protection structure and manufacturing method therefor | |
| US10062746B2 (en) | Semiconductor rectifier and manufacturing method thereof | |
| CN105655402A (en) | Low-voltage super-junction MOSFET (metal-oxide-semiconductor field effect transistor) terminal structure and method for manufacturing same | |
| CN112802899A (en) | High-voltage plane VDMOS device integrated with ESD structure and manufacturing method | |
| US9722035B2 (en) | Method for manufacturing termination structure of semiconductor device | |
| CN210429829U (en) | High-voltage shielded gate MOSFET with floating island structure | |
| CN110718545A (en) | Low residual voltage ESD surge protection device with low-capacitance structure | |
| CN107910325B (en) | ESD protective device of external PMOS triggering SCR-L DMOS structure | |
| CN208385408U (en) | A kind of low low residual voltage ESD surge protective device for holding structure | |
| CN107946374A (en) | A kind of Schottky rectifier and manufacture method with surface impurity concentration regulatory region | |
| CN106816463B (en) | Terminal structure, semiconductor device and preparation method thereof | |
| US11652098B2 (en) | Transistor structure for electrostatic protection and method for manufacturing same | |
| CN106409827A (en) | Rectifying device and preparation method thereof | |
| CN111199970B (en) | Transistor structure for electrostatic protection and manufacturing method thereof | |
| CN111430468B (en) | Dual-core isolation structure of dual-cell packaged Schottky diode chip and manufacturing method | |
| JPS60263461A (en) | Manufacture of high withstand voltage longitudinal transistor | |
| CN209626228U (en) | A kind of semiconductor power device for cutting down the light shield number of plies | |
| CN209626219U (en) | A kind of semiconductor power device | |
| KR101463078B1 (en) | Schottky barrier diode and fabricating method thereof | |
| CN111192871A (en) | Transistor structure for electrostatic protection and manufacturing method thereof | |
| US20130256680A1 (en) | Vertical Semiconductor Device and Manufacturing Method Thereof | |
| CN205488142U (en) | Low pressure surpasses knot MOSFET terminal structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |