CN103489860B - A kind of compound semiconductor wafer structure - Google Patents
A kind of compound semiconductor wafer structure Download PDFInfo
- Publication number
- CN103489860B CN103489860B CN201210195095.8A CN201210195095A CN103489860B CN 103489860 B CN103489860 B CN 103489860B CN 201210195095 A CN201210195095 A CN 201210195095A CN 103489860 B CN103489860 B CN 103489860B
- Authority
- CN
- China
- Prior art keywords
- layer
- doped layer
- type doped
- equal
- shaped
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Bipolar Transistors (AREA)
Abstract
The present invention is about a kind of compound semiconductor wafer structure, comprise a substrate, a N-shaped field-effect transistor epitaxial structure, one N-shaped doping etch stop layer, a p-type insert layer and a npn heterojunction bipolar transistor epitaxial structure, can in order to fabricating yard effect transistor, heterojunction bipolar transistor or Men Liuguan transistor.
Description
Technical field
The present invention relates to a kind of compound semiconductor wafer structure, particularly relate to a kind of integration heterojunction bipolar transistor (heterojunctionbipolartransistor; HBT), field-effect transistor (fieldeffecttransistor; FET) with Men Liuguan transistor (Thyristor) epitaxial structure in single wafer, can be applicable to the compound semiconductor wafer structure of electrostatic defending (ElectrostaticDischarge, ESD) system.
Background technology
When human body touches integrated circuit; the electrostatic that human body is accumulated can enter in circuit via the pin of integrated circuit; discharge via IC ground again; discharge process can how (ns) time second produces the immediate current of several amperes at short hundreds of; cause integrated circuit package dysfunction or damage, therefore usually need design one systems for providing electrostatic discharge protection with the assembly in protective circuit in integrated circuits.
In compound semiconductor single wafer processing procedure, be limited to the design of epitaxial layer, at the design aspect of electrostatic defending, mostly is traditionally use pn junction rectifier or Schottky diode (Schottkydiode), in practical application, normally in wafer, first makes multiple diode, again these diodes serial connection is used, therefore need to occupy larger wafer area, and the conducting voltage of diode is less, therefore antistatic capacity is restricted.
Thyristor (silicon-controlledrectifier; SCR) be the one of thyratron transistor (Thyristor), its structure is pnpn structure, is widely used in Silicon Wafer processing procedure.Thyristor has high break-over voltage; then have one when assembly enters conducting state and lowly hold voltage (holdingvoltage); can by system voltage strangulation at very low voltage quasi position when being applied to electrostatic discharge protection circuit; make internal circuit can effectively protected live, there is good electrostatic defending usefulness.
At present in compound semiconductor wafer structure, in order to improve assembly integration, gradually adopt a kind of structure being called BiFET/BiHEMT, that is the vertical stack structure of a kind of heterojunction bipolar transistor (HBT) and field-effect transistor/High Electron Mobility Transistor (FET/HEMT), can HBT and FET/HEMT assembly be integrated on same chip; Because HBT has npn or pnp contact structure, and FET/HEMT can be N-shaped or p-type, therefore, if form the pnpn structure needed for thyristor in BiFET/BiHEMT structure, thyristor and BiFET/BiHEMT structure can be integrated, more can improve the range of application of single wafer, significantly can improve antistatic capacity simultaneously.
Summary of the invention
Main purpose of the present invention is to provide a kind of compound semiconductor wafer structure, it is in a BiFET structure, insert an a N-shaped doping etch stop layer and p-type insert layer, uses and integrates field-effect transistor (FET), heterojunction bipolar transistor (HBT) with the epitaxial structure with Men Liuguan transistor (Thyristor) in a compound semiconductor wafer structure; Wherein this thyratron transistor in electrostatic protection system (ESD), can significantly can reduce the electrostatic discharge protective circuit wafer usable floor area that tradition utilizes diode, and promotes electrostatic protection ability further, significantly promotes product competitiveness.
For reaching above-mentioned purpose, the invention provides a kind of compound semiconductor wafer structure, comprise a substrate, a field-effect transistor epitaxial structure, N-shaped doping etch stop layer, a p-type insert layer and a heterojunction bipolar transistor arrangement, wherein this field-effect transistor epitaxial structure is positioned on this substrate, comprise a channel layer and a N-shaped doped layer, wherein this N-shaped doped layer is positioned on this channel layer, can in order to make N-shaped field-effect transistor; This heterojunction bipolar transistor epitaxial structure from bottom to top sequentially comprises collector layer, a collector layer, a base layer and an emitter layer, wherein this collector layer, this collector layer and this emitter layer are a N-shaped doped layer and this base layer is a p-type doped layer, thus form a npn type heterojunction bipolar transistor epitaxial structure; Wherein this field-effect transistor epitaxial structure, this N-shaped doping secondary collector layer of etch stop layer, this p-type insert layer and this heterojunction bipolar transistor epitaxial structure, collector layer and base layer can form thyratron transistor (Thyristor) epitaxial structure that has pnpn type contact structure.
In time implementing, the N-shaped doping etch stop layer in aforementioned structure is made up of InGaP (InGaP), and its doping content is for being more than or equal to 1 × 10
15and be less than or equal to 1 × 10
22cm
-3, and its thickness be between
extremely
between.
In time implementing, the p-type insert layer in aforementioned structure can comprise one to several layers p-type doped layer, and its doping content of wherein adjacent between two p-type doped layer is different, and the every one deck doping content of this p-type insert layer is for being more than or equal to 1 × 10
15cm
-3and be less than or equal to 1 × 10
22cm
-3, and its every a layer thickness be between
extremely
between.
In time implementing, p-type insert layer in aforementioned structure can comprise a p+ type doped layer and a p-type doped layer, wherein this p+ type doped layer is a high concentration of p-type doped layer, and this p-type doped layer is a low concentration p-type doped layer, and this p-type doped layer is positioned on this p+ type doped layer.
In time implementing, aforementioned p+ type doped layer and p-type doped layer are made up of GaAs (GaAs).
In time implementing, the doping content of aforementioned p+ type doped layer is for being more than or equal to 1 × 10
18cm
-3and be less than or equal to 1 × 10
22cm
-3, and its thickness is for being more than or equal to
and be less than or equal to
In time implementing, the doping content of aforementioned p-type doped layer is for being more than or equal to 1 × 10
16cm
-3and be less than or equal to 1 × 10
17cm
-3, and its thickness is for being more than or equal to
and be less than or equal to
In time implementing, aforementioned field effect transistor epitaxial structure can be a N-shaped metal semiconductor field-effect transistor (metalsemiconductortransistor; MESFET) epitaxial structure.
In time implementing, aforementioned field effect transistor epitaxial structure can be a N-shaped High Electron Mobility Transistor (highelectronmobilitytransistor; HEMT) epitaxial structure.
In time implementing, aforementioned field effect transistor epitaxial structure can be the pseudo-crystal formation High Electron Mobility Transistor of a N-shaped (pseudomorphichighelectronmobilitytransistor; PHEMT) epitaxial structure.
In time implementing, the material forming aforesaid base plate can be GaAs (GaAs) or indium phosphide (InP).
The present invention adopts technique scheme, has the following advantages:
The invention provides one and comprise field-effect transistor (FET), heterojunction bipolar transistor (HBT) with the single compound semiconductor crystal circle structure with Men Liuguan transistor (Thyristor) epitaxial structure; The thyratron transistor utilizing this crystal circle structure to make can be used for electrostatic discharge protective circuit (ESD), can significantly reduce electrostatic discharge protective circuit usable floor area, and thyratron transistor has higher trigger voltage, lowlyer hold voltage, lower energy dissipation, and to high electric current, there is preferably disposal ability, therefore can promote antistatic capacity further, significantly promote product competitiveness; In addition, the present invention can with existing BiFET/BiHEMT process integration, therefore significantly can reduce the cost of the manufacturing.The value that its true tool industry utilizes.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of a kind of compound semiconductor wafer structure of the present invention;
Fig. 2 is the cross-sectional view that a kind of compound semiconductor wafer structure of the present invention is applied in semiconductor subassembly;
Fig. 3 is the current vs voltage variation diagram that the transmission line pulse system (TLP) of thyratron transistor (Thyristor) in the present invention is tested.
Description of reference numerals: substrate 101; Field-effect transistor epitaxial structure 110; Thyratron transistor epitaxial structure 120; Heterojunction bipolar transistor epitaxial structure 130; Channel layer 111; N-shaped doped layer 112; N-shaped doping etch stop layer 121; P-type insert layer 122; Secondary collector layer 131; Collector layer 132; Base layer 133; Emitter layer 134; Field-effect transistor 210; Thyratron transistor 220; Heterojunction bipolar transistor 230; Source electrode 201; Drain electrodes 202; Gate electrode 203; Base electrode 204; Collector electrode 205; Emitter-base bandgap grading electrode 206; Anode electrode 207; Cathode electrode 208.
Embodiment
Integration one field-effect transistor (FET) provided by the present invention, the compound semiconductor wafer structure of the epitaxial structure of one heterojunction bipolar transistor (HBT) and a thyratron transistor (Thyristor), as shown in Figure 1, comprise a substrate 101, one field-effect transistor epitaxial structure 110, one N-shaped doping etch stop layer 121, one p-type insert layer 122 and a heterojunction bipolar transistor arrangement 130, wherein the constituent material of this substrate 101 can be the half insulation semi-conducting material such as GaAs (GaAs) or indium phosphide (InP), be wherein better with GaAs (GaAs), this field-effect transistor epitaxial structure 110, is positioned on this substrate 101, and comprise channel layer 111 and a N-shaped doped layer 112, wherein this N-shaped doped layer is positioned on this channel layer, and this structure can in order to make N-shaped field-effect transistor, this N-shaped doping etch stop layer 121 is positioned on this field-effect transistor epitaxial structure 110, this p-type insert layer 122 is positioned on N-shaped doping etch stop layer 121, this heterojunction bipolar transistor epitaxial structure 130 from bottom to top sequentially comprises collector layer 131, collector layer 132, base layer 133 and an emitter layer 134, wherein this collector layer 131, this collector layer 132 and this emitter layer 134 are a N-shaped doped layer, and this base layer 133 is a p-type doped layer, thus form a npn type heterojunction bipolar transistor epitaxial structure 130, thus, this compound semiconductor wafer structure from top to bottom has n-p-n-p-n structure, and the p-n-p-n structure contained needed for formation one thyratron transistor (Thyristor), that is the p-type doped base layer of the doping of this N-shaped field-effect transistor epitaxial structure, this N-shaped etch stop layer, this p-type insert layer and this heterojunction bipolar transistor epitaxial structure, N-shaped doping collector layer, the secondary collector layer that adulterate with N-shaped can form thyratron transistor (Thyristor) epitaxial structure 120 that has pnpn type contact structure.
In time implementing, field-effect transistor epitaxial structure 110 can be the epitaxial structure of a N-shaped metal semiconductor field-effect transistor (MESFET), a N-shaped High Electron Mobility Transistor (HEMT), N-shaped puppet crystal formation High Electron Mobility Transistor (pHEMT) or other N-shaped field-effect transistor; The constituent material of N-shaped doping etch stop layer 121 is better with InGaP (InGaP), and its doping content is between 1 × 10
15to 1 × 10
22cm
-3between, wherein with between 1 × 10
17to 1 × 10
18cm
-3between be better, its thickness can be between
extremely
between, wherein with between
extremely
between be better; P-type insert layer 122 can comprise one to several layers p-type doped layer, and its doping content of wherein adjacent between two p-type doped layer is different, and its every one deck doping content is for being more than or equal to 1 × 10
15and be less than or equal to 1 × 10
22cm
-3, and its every a layer thickness be between
extremely
between; The main composition material of heterojunction bipolar transistor epitaxial structure 130 can be GaAs (GaAs), and secondly collector layer 131 doping content is between 1 × 10
15to 1 × 10
22cm
-3between, wherein to be more than or equal to 1 × 10
18cm
-3and be less than or equal to 1 × 10
22cm
-3high-dopant concentration be better.Be applied in semiconductor subassembly, as shown in Figure 2, can one source pole electrode 201 and a drain electrodes 202 be set on the N-shaped doped layer 112 of aforementioned wafer integrated structure, arrange the gate electrode 203 of a link channel layer 111 in N-shaped doped layer groove between source electrode and drain, then this channel layer 111, this N-shaped doped layer 112, this source electrode 201, this drain electrodes 202 and this gate electrode 203 can form a N-shaped field-effect transistor (FET) 210; One base electrode 204 is set in the base layer 133 of aforementioned wafer integrated structure, one collector electrode 205 is set on secondary collector layer 131, and an emitter-base bandgap grading electrode 206 is set on emitter layer 134, then this collector layer 131, this collector layer 132, this base layer 133, this emitter layer 134, this base electrode 204, this collector electrode 205 and this emitter-base bandgap grading electrode 206 can form a heterojunction bipolar transistor (HBT) 230; One anode electrode 207 is set in base layer 133, and a cathode electrode 208 is set on N-shaped doped layer 112, then this N-shaped doped layer 112, this N-shaped doping etch stop layer 121, this p-type insert layer 122, this collector layer 131, this collector layer 132, this base layer 133, this anode electrode 207 and this cathode electrode 208 can form a thyratron transistor (Thyristor) 220.
Table 1 is an embodiment of compound semiconductor wafer structure of the present invention; This embodiment comprises a substrate and is positioned at 14 layers of epitaxial layer on this substrate, wherein from top to down the 1st layer and the 2nd layer is emitter contact layer and a cover layer of a high-dopant concentration, 3 to 6 layer is emitter layer, comprises the N-shaped doped layer of plural layer different-thickness and different levels of doping; 7th layer is base layer, is the p-type doped layer of a high-dopant concentration; The secondary collector layer that 8 to the 10 layer of collector layer for N-shaped doping and n+ type adulterate; 11st, 12 layers is p-type doped layer, be respectively a p+ type doped layer and a p-type doped layer, be made up of GaAs (GaAs), this p+ type doped layer is a high concentration of p-type doped layer, and this p-type doped layer is a low concentration p-type doped layer, wherein this p-type doped layer is positioned on this p+ type doped layer, and the doping content of this p+ type doped layer may be selected to be and is more than or equal to 1 × 10
18cm
-3and be less than or equal to 1 × 10
22cm
-3, and its thickness can be and is more than or equal to
and be less than or equal to
the doping content of this p+ type doped layer is chosen as 1 × 10 in this embodiment
18cm
-3, and thickness is chosen as
and the doping content of this p-type doped layer is for being more than or equal to 1 × 10
16cm
-3and be less than or equal to 1 × 10
17cm
-3, and its thickness can be and is more than or equal to
and be less than or equal to
the doping content of this p-type doped layer is chosen as 1 × 10 in this embodiment
16cm
-3, and thickness is chosen as
13rd layer is N-shaped doping etch stop layer, and it is made up of InGaP (InGaP), and its doping content is chosen as 3 × 10
17cm
-3, and its thickness is chosen as
14th layer is a n+ type doped layer, and its doping content is chosen as 4 × 10
18cm
-3, and its thickness is chosen as
the 7 to 14 layer in this embodiment is p-n-p-n structure, can in order to make a thyratron transistor (Thyristor).
The electrostatic defending performance of semiconductor integrated circuit is normally with transmission line pulse system (TransmissionLinePulse, TLP) test, be by a high-current pulse signal input test circuit in this test, measured incidence and reflected impulse signal are through can be calculated the voltage-to-current change curve of test circuit; The energy range of this high-current pulse input signal and pulse time length are close to human-body model (HumanBodyModel, HBM); Fig. 3 is the TLP voltage-current characteristic curve (solid line) of thyratron transistor provided by the present invention, and does one with the TLP voltage-current characteristic curve (dotted line) of series diode and compare; The trigger voltage (triggervoltage) of the thyratron transistor in figure made by display application crystal circle structure of the present invention is about 8 volts, hold voltage (holdingvoltage) and be about 2 volts, assembly collapse electric current (devicefailurecurrent) is about 0.57 ampere; Compared with the TLP voltage-current characteristic curve using series diode as electrostatic discharge protection circuit in prior art, thyratron transistor provided by the present invention has higher trigger voltage, and assembly also can remain lower after triggering holds voltage; The trigger voltage of this assembly affects with the thickness and doping content holding the p-type doped layer that voltage is inserted; Better assembly antistatic protection function can be reached by adjustment p-type doped layer thickness and doping content.
Table 1
These embodiments are only exemplary above, do not form any restriction to scope of the present invention.It will be understood by those skilled in the art that and can modify to the details of technical solution of the present invention and form or replace down without departing from the spirit and scope of the present invention, but these amendments and replacement all fall within the scope of protection of the present invention.
Claims (11)
1. a compound semiconductor wafer structure, integrate the epitaxial structure of a field-effect transistor, a heterojunction bipolar transistor and a thyratron transistor, sequentially comprise:
One substrate;
One field-effect transistor epitaxial structure, is positioned on this substrate, has a channel layer, and
One N-shaped doped layer is positioned on this channel layer;
One N-shaped doping etch stop layer;
One p-type insert layer, is positioned on this N-shaped doping etch stop layer; And
One heterojunction bipolar transistor arrangement, is positioned on this p-type insert layer, comprises:
A collector layer is a N-shaped doped layer,
One collector layer, is positioned on this collector layer, is a N-shaped doped layer,
One base layer, is positioned on this collector layer, is a p-type doped layer, and
One emitter layer, is positioned on this base layer, is a N-shaped doped layer;
Wherein this field-effect transistor epitaxial structure, this N-shaped doping secondary collector layer of etch stop layer, this p-type insert layer and this heterojunction bipolar transistor epitaxial structure, collector layer and base layer form a thyratron transistor epitaxial structure.
2. compound semiconductor wafer structure as claimed in claim 1, is characterized in that, this N-shaped doping etch stop layer is made up of InGaP, and its doping content is for being more than or equal to 1 × 10
15cm
-3and be less than or equal to 1 × 10
22cm
-3, and its thickness be between
extremely
between.
3. compound semiconductor wafer structure as claimed in claim 1, it is characterized in that, this p-type insert layer comprises one deck or plural layer p-type doped layer, and its doping content of wherein adjacent between two p-type doped layer is different, and the every one deck doping content of this p-type insert layer is for being more than or equal to 1 × 10
15cm
-3and be less than or equal to 1 × 10
22cm
-3, and its every a layer thickness be between
extremely
between.
4. compound semiconductor wafer structure as claimed in claim 3, it is characterized in that, this p-type insert layer comprises a p+ type doped layer and a p-type doped layer, wherein this p+ type doped layer is a high concentration of p-type doped layer, and this p-type doped layer is a low concentration p-type doped layer, this p-type doped layer is positioned on this p+ type doped layer.
5. compound semiconductor wafer structure as claimed in claim 4, it is characterized in that, this p+ type doped layer and this p-type doped layer are made up of GaAs.
6. compound semiconductor wafer structure as claimed in claim 4, it is characterized in that, the doping content of this p+ type doped layer is for being more than or equal to 1 × 10
18cm
-3and be less than or equal to 1 × 10
22cm
-3, and its thickness is for being more than or equal to
and be less than or equal to
7. compound semiconductor wafer structure as claimed in claim 4, it is characterized in that, the doping content of this p-type doped layer is for being more than or equal to 1 × 10
16cm
-3and be less than or equal to 1 × 10
17cm
-3, and its thickness is for being more than or equal to
and be less than or equal to
8. compound semiconductor wafer structure as claimed in claim 1, it is characterized in that, this field-effect transistor epitaxial structure is a N-shaped metal semiconductor field-effect transistor epitaxial structure.
9. compound semiconductor wafer structure as claimed in claim 1, it is characterized in that, this field-effect transistor epitaxial structure is a N-shaped High Electron Mobility Transistor epitaxial structure.
10. compound semiconductor wafer structure as claimed in claim 1, is characterized in that, this field-effect transistor epitaxial structure is a N-shaped pseudo-crystal formation High Electron Mobility Transistor epitaxial structure.
11. compound semiconductor wafer structures as claimed in claim 1, is characterized in that, the material forming this substrate is GaAs or indium phosphide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210195095.8A CN103489860B (en) | 2012-06-13 | 2012-06-13 | A kind of compound semiconductor wafer structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210195095.8A CN103489860B (en) | 2012-06-13 | 2012-06-13 | A kind of compound semiconductor wafer structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103489860A CN103489860A (en) | 2014-01-01 |
| CN103489860B true CN103489860B (en) | 2016-02-10 |
Family
ID=49829978
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210195095.8A Active CN103489860B (en) | 2012-06-13 | 2012-06-13 | A kind of compound semiconductor wafer structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103489860B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1507660A (en) * | 2001-03-02 | 2004-06-23 | �����Ҹ��ݴ�ѧ | A modulation doped thyristor and complementary transistor combination for a monolithic optoelectronic integrated circuit |
| CN102412265A (en) * | 2010-09-17 | 2012-04-11 | 寇平公司 | Method for preventing semiconductor layer mix and laminated structure |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6841795B2 (en) * | 2002-10-25 | 2005-01-11 | The University Of Connecticut | Semiconductor devices employing at least one modulation doped quantum well structure and one or more etch stop layers for accurate contact formation |
| JP2010206020A (en) * | 2009-03-04 | 2010-09-16 | Panasonic Corp | Semiconductor device |
-
2012
- 2012-06-13 CN CN201210195095.8A patent/CN103489860B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1507660A (en) * | 2001-03-02 | 2004-06-23 | �����Ҹ��ݴ�ѧ | A modulation doped thyristor and complementary transistor combination for a monolithic optoelectronic integrated circuit |
| CN102412265A (en) * | 2010-09-17 | 2012-04-11 | 寇平公司 | Method for preventing semiconductor layer mix and laminated structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103489860A (en) | 2014-01-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9209265B2 (en) | ESD devices comprising semiconductor fins | |
| CN102593168B (en) | Semiconductor device and a reverse conducting IGBT | |
| US9570436B2 (en) | Semiconductor device | |
| US8304838B1 (en) | Electrostatic discharge protection device structure | |
| US11699899B2 (en) | Electronic device and electrostatic discharge protection circuit | |
| EP3072154B1 (en) | Electrostatic discharge protection circuits and structures and methods of manufacture | |
| US9087923B2 (en) | Monolithic compound semiconductor structure | |
| CN110600467A (en) | TVS device with surface silicon controlled rectifier structure triggered by vertical triode | |
| CN212571005U (en) | TVS device | |
| CN112259597A (en) | TVS device | |
| CN211125650U (en) | TVS device with surface silicon controlled rectifier structure triggered by vertical triode | |
| CN108766964B (en) | LDMOS electrostatic protection device | |
| CN108565260B (en) | Semiconductor device with a plurality of transistors | |
| KR101524408B1 (en) | Electrostatic Discharge protection circuit | |
| CN107910325B (en) | ESD protective device of external PMOS triggering SCR-L DMOS structure | |
| CN103489860B (en) | A kind of compound semiconductor wafer structure | |
| CN105679836A (en) | Ultra-low-capacitance TVS diode structure and preparation method therefor | |
| CN113053874B (en) | Radiation-resistant high-voltage ESD semiconductor device | |
| JP2024520102A (en) | GGNMOS TRANSISTOR STRUCTURE, ESD PROTECTION DEVICE AND CIRCUIT | |
| US20200321432A1 (en) | Semiconductor device, semiconductor apparatus and method of manufacturing the same | |
| US20200321330A1 (en) | Device of protection against electrostatic discharges | |
| CN111180439A (en) | Electrostatic protection device of integrated circuit chip applied to FinFET process and preparation method thereof | |
| US9478531B2 (en) | Semiconductor device comprising an ESD protection device, an ESD protection circuitry, an integrated circuit and a method of manufacturing a semiconductor device | |
| CN111816650B (en) | SCR electrostatic protection structure and forming method thereof | |
| CN205140988U (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |