JPH04180240A - Field effect transistor - Google Patents

Abstract

PURPOSE:To improve the electric features (especially, mobility) of InGaAs on an InP substrate by adjusting the In composition ratio and layer thickness of the InGaAs layer. CONSTITUTION:On a semi-insulating InP substrate 1, an InAlAs buffer layer 1a, an InGaAs channel layer 2, an InAlAs spacer (non-doped) layer 3, an InAlAs doped layer 4 with a high concentration of Si dopant, and an InGaAs cap layer 5 are consecutively formed. Next, the In composition ratio of the InGaAs channel layer 2 is set at 0.53 or higher to create and imperfect matrix and the thickness of the InGaAs crystal layer 2 with this In composition ratio is set below the critical film thickness at which growth can be achieved without producing misfit transition. As a result, the electric features (especially, mobility) of the InGaAs channel layer 2 which the carrier gas actually transits are improved.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to field effect transistors using InGaAs, and particularly to improvements in high carrier mobility.

[Conventional technology]

Although Si is generally used as a material for field effect transistors, compound semiconductors are materials that have higher carrier mobility than Si and improve transistor performance. MESFETs with high-purity GaAs on semi-insulating GaAs substrates as active layers, and HEs with active layers of two-dimensional electron gas generated at AlGaAs/GaAs heterojunctions have already been developed.
MT etc. have been put into practical use. In addition, in recent years, InGaAs has attracted attention as a material that has even greater mobility than GaAs and enables higher-speed operation.
InGaAs/In grown on semi-insulating InP substrate
AlAs heterojunction is an A I Ga on a GaAS substrate.
It has better mobility, saturated electron velocity, and sheet carrier concentration than the As/GaAs heterojunction, and is attracting attention as a high-frequency, 0ErC material.

Here, InGaAs is a material obtained by growing a mixed crystal of InAs and GaAs. Comparing the lattice constants of InAs and GaAs, InAs has a lattice constant of 0.606 nm,
Since GaAs has a different lattice constant of 0.565 nm, InP with a lattice constant of 0.587 nm between these is different from InGa.
It is used as a substrate for epitaxial growth of As.

FIG. 1 shows the basic structure (cross-sectional view) of a field effect transistor basically composed of InAlAs/InGaAs/InP (substrate).

In the figure, an InGaAs crystal growth layer 2 of the highest possible purity is formed as an active layer on a semi-insulating InP substrate 1, and furthermore, an InGaAs crystal growth layer 2 with a wider energy band width than the InGaAs crystal growth layer 2 is formed on the semi-insulating InP substrate 1. In addition, it is preferable that a non-doped crystal growth layer of InA with as high purity as possible be formed.
A lAs crystal growth layer 3 is formed. A heterojunction interface A is therefore formed between these layers 2.3.

On this InAlAs crystal growth layer 3, a heavily doped InAlAs crystal growth layer 4 is formed, for example, made of the same material as this crystal growth layer 3 but doped with a high concentration. A surface crystal layer 5 is formed, and electrodes 6.8 (generally, one is called a source electrode and the other is called a drain electrode) are brought into ohmic contact with the InGaAs crystal growth layer 2 by impurity diffusion. and an electrode 7 (also generally referred to as a gate electrode) that controls the electric field applied to the heterojunction interface A. Note that this gate electrode 7 is formed to form a Schottky or pn junction with the heavily doped crystal growth layer 4.

In a field effect transistor using such a heterojunction, an electrode By applying an electric field in parallel through the electrodes 6 and 8 to make the carrier gas layer 2a an active layer, carriers induced in the active layer are controlled by the electric field applied from the electrode 7. The current flowing between .8 and 8 is controlled to operate as a transistor. Therefore, the electrical characteristics (particularly the mobility) of the InGaAs crystal growth layer 2 through which the carrier gas actually travels have a large influence on the high-speed operation of the transistor, and the higher the mobility, the better the high-speed operation.

In contrast to the basic structure shown in FIG. 1, there is a reverse heterostructure in which the InGaAs crystal growth layer 2 and the heavily doped crystal growth layer 4 are replaced, or the InGaAs crystal growth layer 2 is replaced with the non-doped crystal growth layer 3 and the heavily doped crystal growth layer. There are also modified examples such as a double hetero structure sandwiched between the growth layers 4 and a structure in which a crystal layer of another material is formed as a buffer layer between the semi-insulating InP substrate 1 and the InGaAs crystal growth layer 2.

In addition, there are cases where the InGaAs layer is doped instead of the heterostructure and used as an active layer.

[Problem to be solved by the invention]

Here, in the configuration shown in FIG. 1, InGaAs,
Due to its composition, InAlAs has a -
Since it has a lattice mismatch rate of 3.7 to +3.2%,
In order to grow InAlAs and InAlAs on an InP substrate with good crystallinity, the composition ratio X is set to In x Ga, -*
It is necessary to precisely control the lattice constant to 0.53 for As and 0.52 for InXA11-XAS to match that of InP. This is because when growth occurs with lattice mismatch, distortion occurs due to the difference in lattice constant between the substrate and the growth layer, and crystallinity deteriorates due to the effect of the strain or dislocations generated by the strain, and electrical properties (especially mobility) increase. This is because it decreases.

Furthermore, InAs is a difficult material to grow crystals, especially in a state of lattice mismatch, and it is difficult to grow high-quality crystals.
When s is grown on an InP substrate, the crystallinity deteriorates as the In composition increases.

However, on the other hand, high purity bulk single crystal InAS and C
Comparing the electron mobilities of aAs at room temperature, each InA
s33000cdl/Vs, GaAs8000cd/V
s, InAs is about four times larger. Therefore, in InGaAs, the higher the composition of InAS, the higher the mobility, which is considered to be advantageous for high-speed operation.

In view of these circumstances, the present invention has developed an InGa film on an InP substrate.
In a structure grown with As, we found an optimal condition that balances the mobility-increasing effect caused by increasing the In composition and the mobility-decreasing effect due to the generation of dislocations and deterioration of crystallinity. The objective is to realize a field effect transistor with improved characteristics (particularly mobility).

[Summary of the invention]

In order to achieve the above object, a field effect transistor according to the present invention has a structure in which InGaAS is formed as an active layer on an InP substrate, or a structure in which InGaAs and this InGaAs are formed as an active layer on an InP substrate.
In a structure in which a two-dimensional carrier gas generated at the heterojunction interface between aAs and a semiconductor having a different energy band width is formed as an active layer, the In composition ratio of the InGaAs crystal layer in which the carrier or two-dimensional carrier gas is formed is determined by the lattice. The rnGaAs crystal layer is grown to a thickness of 0.7 to 0.9 with mismatch, and the thickness of the r nGaAs crystal layer is set to be below the critical thickness that can be grown without generating misfit dislocations, depending on the In composition ratio. It is characterized by being

For example, when the In composition ratio is 0.7, the thickness of the InGaAs crystal layer is 50 nm or less, and when the In composition ratio is 0.8, the thickness of the In GaAs crystal layer is 25 nm.
Below, when the In composition ratio is 0.9, the thickness is 13 nm or less.

According to the experimental considerations of the present inventors, even in the case of lattice-mismatched growth, the crystal lattice absorbs the energy of the lattice strain, and the maximum film thickness (critical film thickness) that can be grown without generating misfit dislocations. It was confirmed that if the film is not grown beyond this thickness, a pseudomorphic state is achieved and the crystallinity does not deteriorate (good electrical properties are obtained).

In other words, if the InGaAs crystal layer is grown by shifting the In composition from 0,53, which is lattice-matched to InP, and the thickness of the InGaAs crystal layer is set below the critical film thickness depending on the In composition, the active layer Mobility increases. FIG. 2 shows the characteristics of two-dimensional electron gas mobility change in a structure with a critical thickness or less when the In composition of the InGaAs layer serving as the active layer in an InAlAs/fnGaAs heterojunction is changed. In this way, the inventors have discovered that I
It has been found that increasing the n composition increases the mobility and reaches a maximum at a composition ratio of around 0.80. Also, the composition ratio is 0.80
Comparing the mobility at room temperature for a composition ratio of 0.53 in a lattice matched state (conventional), each is 14,000 d! /Vs
, 10000c+11/V s, the former being 40% higher than the latter.

As described above, according to the present invention, mobility can be significantly improved,
This is advantageous for high-speed operation, and it is possible to obtain a basic structure that is optimal for amplifiers in the ultra-high frequency range above microwaves.

[First Example] Hereinafter, a first example in which the present invention is applied to an InAlAs/TnGaAs heterojunction field effect transistor will be described.

FIG. 3 shows a cross-sectional structural diagram of the first embodiment of the present invention. In FIG. 3, InAlAs is deposited on a semi-insulating InP substrate 1.
nAlAs huff 00nm, 1nGaAs channel layer 2 10nm, InAIAS spacer (non-doped) layer 3 5nm, InAlAs heavily doped with Si.
The doped layer 4 has a thickness of 40 nm, and the InC; aAs skip layer 5 has a thickness of 10 nm, which are successively formed by MBE or MOCVD. Note that the InGaAs channel layer 2
The composition ratio is controlled to 0.8, and a heterojunction interface A is formed between the InGaAs channel layer 2 and the InAlAs spacer layer 3). Then, the source/drain electrode 6.8 and the heterojunction interface A are brought into ohmic contact with the InGaAs channel layer 2B by impurity diffusion.
A Schottky gate electrode 7 is formed to control the electric field applied to the capacitor.

Here, the InAlAs buffer layer 1a is formed as a buffer layer and eliminates the influence of defects in the InP substrate 1. Moreover, the InAlAs spacer layer 3 is for spatially separating the donor ions of the InAlAs doped layer 4 and the two-dimensional electron gas layer formed in the InGa'As channel layer at the hetero interface A. .

Note that the InAlAs spacer layer 3, InAlAs doped layer 4, and cap layer 5, which supply carriers from the source/drain electrodes 6 and 8 to the InGaAs channel layer 2, may have a superlattice structure. In addition, the InAlAs doped layer 4 was doped with Si to make it n-type, but
It may also be doped with a P-type impurity at a high concentration.

In the heterojunction field effect transistor of this embodiment, carriers doped in the InAlAs doped layer 4 are accumulated at the heterojunction interface A, and the carriers doped in the InAlAs doped layer 4 are accumulated at the heterojunction interface A,
A two-dimensional carrier gas is generated on the s-channel layer 2 side. In a field effect transistor using a heterojunction, an electric field is applied in parallel to the two-dimensional carrier gas formed on the channel layer 2 side of the heterojunction interface A through the source/drain electrodes 6 and 8, and the gas layer is is used as an active layer, and by controlling the carriers induced in this active layer by the electric field applied from the gate electrode 7, the current flowing between the source and drain electrodes 6 and 8 is controlled to perform transistor operation. . Therefore, the InGa where the carrier gas actually travels
The electrical characteristics (particularly the mobility) of the As channel layer 2 are greatly related to the high-speed operation of the transistor.

Conventionally, the In composition ratio of the InGaAs channel layer 2 through which the two-dimensional carrier gas runs was adjusted to prevent dislocations from occurring.
It was set to 0 and 53 to be lattice matched to the nP substrate 1. With such a composition, the high mobility feature of InAs cannot be fully exhibited.

On the other hand, in the structure of this example, the In&u ratio of the InGaAs channel layer 2 is controlled to 0.8 to increase the InAs composition, which increases the mobility. In order to suppress dislocations caused by strain caused by mismatching, the thickness of the InGaAs channel layer 2 is set to 10 nm (critical thickness 25 nm or less), which prevents the occurrence of dislocations. The mobility can be increased by about 40% from 10,000 d/V s to 14,000 cj/V s at room temperature, and a field effect transistor useful for high-speed operation can be obtained.

Next, precise control of the In composition of InGaAs when the MBE growth method is adopted will be explained.

In this example, the RHEED vibration method is used for composition control. The RHEED vibration method is a method in which the growth rate of each material is measured to determine the flux, and the composition is determined from the ratio.

Normally, in composition control using the RHEED vibration method, the measurement substrate is the same as the growth substrate, but InGaA
Taking s as an example, the growth substrate is InP as in this example.
If so, RH of GaAs and InGaAs on InP substrate
Measure EED vibration.

Here, the reason why the RHEED vibration of InGaAs is measured is that it is difficult to measure the RHEED vibration of InAs using an InP substrate. With this method, GaA
s, InGaAs is measured in a lattice-mismatched state with respect to the InP substrate, and there is a problem in that the vibration period is not stable and the number of vibrations is small compared to the lattice-matched condition, making it impossible to perform precise measurements.

Therefore, in this embodiment, GaAs and AlAs are
The substrate, InAs, was set to lattice matching conditions using an InAs substrate. In this case, since the growth substrate and the measurement substrate are different, the growth rate may change and an accurate composition ratio may not be obtained.
When it was investigated whether the sum of the GaAs fluxes determined for the As substrate was equal to the InGaAs fluxes determined for the InP substrate, it was found that they were equal within a measurement error range of 2% or less regardless of the composition. Note that the same was true for InAlAs. Therefore, even if the growth substrate and the measurement substrate are different, composition control (measurement) can be performed without any problem.

Furthermore, in the MBE device, flux overshoot occurs immediately after the source shutter opens.

FIG. 4(a) shows the change in flux (pressure read with a B-A gauge) over time, taking In as an example. Almost 10% overshoot occurs immediately after the shutter opens, and more than 2 m1n elapses before it stabilizes. Ga and AI also show a similar tendency. If such an overshoot occurs, the composition ratio at the initial stage of growth will deviate from the target. Particularly in the case of forming a thin film of around 10 nm as in this embodiment, the process ends before the flux stabilizes. Furthermore, since the RHEED vibration is attenuated after approximately 1 m1n, problems arise such as the inability to measure the flux in a stable region. Possible causes of such overshoot include the influence of flux accumulated in the space between the shutter and the source surface, and a decrease in the source surface temperature due to the opening of the shutter.

Therefore, in this embodiment, a 5QRT source temperature control method is adopted to eliminate this overshoot. As shown in Figure 4(b), the source temperature is set lower than the original temperature before the shutter is opened (before the growth starts), and after the shutter is opened the parabolic (SQUARE)
This method returns the temperature to its original temperature in a ROOT manner. This method attempts to eliminate overshoot by lowering the source temperature. FIG. 4(C) shows an example in which the 5QRT method is adopted. It can be seen that overshoot (fluctuation in flux), which was conventionally close to 10%, can be reduced to 1%. Note that the overshoot for AI and Ga can also be reduced to 1 to 2% or less.

By measuring the flux using the RHEED vibration of lattice matching and stabilizing the flux using the 5QRT source temperature control method, precise composition control is possible in this example, and crystal growth with a stable composition is realized.

Next, the setting of the critical thickness of the InGaAs channel layer 2 of this example will be explained.

In this example, we proposed to obtain the critical film thickness from the relationship between the electron mobility and the composition ratio, and the two-dimensional electron gas layer 2a formed by the thickness of the InGaAs channel layer 2 and the hetero interface A.
The critical film thickness was determined by examining the relationship between electron mobility. Note that the composition ratio of InAlAs is 0, which is lattice matched to the InP substrate.
, 52.

FIG. 5(a) shows changes in mobility and sheet carrier concentration when the In composition ratio is fixed at 0.80 and the thickness of the InGaAs channel layer 2 is varied. Thickness 10-20
The mobility shows 13,000 to 14,000 cd/Vs at nm, but it rapidly decreases when it exceeds 25 nm. This is considered to be because dislocations occur and crystallinity deteriorates when the critical film thickness is exceeded. From this, it can be seen that the critical film thickness of InGaAs with an In&1 ratio of 0.80 is 20 to 25 nm. Note that no significant change was observed in the sheet carrier concentration.

Similarly, when the In&fl composition ratio is 0.90, the fifth
It is shown in (Return). Similarly, the critical film thickness at this time is 10 to 13
It can be seen that it is between nm. Also in this case, no change in sheet carrier concentration is observed before and after the critical film thickness. This is presumed to be because the dislocations generated in the InGaAs channel layer 2 stop at the Peter junction interface A and do not propagate to the InAlAs doped layer 4. Note that the In composition ratio is 0
．． The critical film thickness at No. 7 was 50 nm.

Note that FIG. 5(C) shows the cryogenic mobility of the sample having a composition ratio of 0.80 shown in FIG. 5(a). The value of room temperature is 2
It shows an almost flat tendency of 13,000 to 14,000 d/Vs up to 0 nm, but at 10K.

At an extremely low temperature of 77°C, a decrease in mobility is seen from around 1Q nm onwards, and no rapid change is observed at room temperature. The difference in trends between room temperature and extremely low temperatures can be presumed to be due to the fact that mobility increases at extremely low temperatures, making it more sensitive to minute changes in dislocation density. The tendency of mobility at extremely low temperatures shows that dislocations are already occurring even at about half the critical film thickness at room temperature. The decrease in mobility at a layer thickness of 7 nm is considered to be due to the generation of surplus carriers due to the thinning of the channel layer.

In addition, InGaA with a thickness below the critical thickness investigated as described above
The characteristic diagram in FIG. 2 shows the relationship between the composition ratio of InxGa and -XAs in the layer thickness of the s-channel layer 2 and the mobility of the two-dimensional electron gas layer 2a. Note that the mobility is a value at room temperature. When the In composition ratio is increased from 0.47, the mobility increases to 10,000 CI at 0.49! /Exceeds VS. The mobility is determined at a lattice-matched composition ratio of 0.0, which causes no distortion.
It continues to increase even when it exceeds 53, and shows a maximum value of 14300 cA/V s at a composition ratio of 0.80. The mobility gradually decreases after exceeding 0.80, and sharply decreases after exceeding 0.90. Composition ratio 1.0, that is, the channel layer is In
When the As layer was used, the mobility did not recover even if the layer thickness was reduced to 5 to 3 nm. Estimating the reason for the maximum mobility at a composition ratio of 0.80, we find that InAS and Cy
When comparing the mobility at room temperature for aAs, InAs3300
0. CaAs8000 and InAs are larger. Therefore, it is considered that the higher the In composition, the higher the mobility. However, TnAs is said to be a material in which it is difficult to grow high-quality crystals, and especially in the case of lattice-mismatched growth such as the present case, it is thought that as the In composition increases, deterioration of crystallinity is more likely to occur. Therefore, the composition ratio of 0°8 balances both effects.
It is considered that the maximum value was 0.

Furthermore, the relationship between composition ratio and mobility at extremely low temperatures is shown in FIG.

Even at extremely low temperatures, it shows the same tendency as at room temperature, with a composition ratio of 0.80 and a maximum value of 10 at 121,500all/Vs, and 77 at 9
It is 1300CIII/Vs.

However, once the composition ratio exceeds 0.80, the mobility decreases.
It occurs gradually at room temperature, but rapidly at extremely low temperatures.

This indicates that as the In composition increased, dislocations that affected fast mobility at extremely low temperatures were generated, resulting in deterioration of crystallinity.

In this way, it is clear that the critical film thickness is set according to each In composition ratio, and that the mobility takes the maximum value at an In composition ratio of 0.80.
Since the thickness of the aAs channel layer 2 is 10 nm, which is less than the critical film thickness, high-speed operation is guaranteed over a wide temperature range, and the sheet carrier concentration is stable, resulting in excellent transistor performance and the highest performance low-noise microwave, millimeter wave FET
It will be possible to achieve this.

[Second Embodiment] FIG. 7 shows a cross-sectional structural diagram of a second embodiment of the present invention. Third
Components that are the same as those of the first embodiment shown in the figures are given the same reference numerals. In this example, InGaAs channel layer 2 and InAl
It is characterized in that an InAs layer is inserted and formed between the As spacer layer 3 and the As spacer layer 3.

In normal growth, I n A I A s / I n
The Ga As hetero interface has irregularities, and the InAl
It is thought that it is a GaAs layer. In order to increase the mobility, it is necessary to flatten the interface and separate InGaAs and InAlAs. A ] G a As / G a
The growth interruption that was effective in the A s heterojunction is I n
Since this is not effective in the case of AIAs/InGaAs, in this example a thin InAs layer 9 is inserted between the InAlAs spacer layer 3 and the InGaAs channel layer 2 in order to separate AI and Ga. We are growing it in a different way. Note that the composition ratio of the InGaAs channel layer 2 is set to 0.80 as in the first embodiment, and the thickness of each layer is also set to be the same.

FIG. 8 shows the relationship between the number of InAs layers 9 and the mobility. Note that 0.5 (monolayers) is 0.5 (monolayers).
This means that In was supplied to the 5th layer.

The mobility at room temperature is 14 in the 0 layer of InAs (first example).
300cj/Vs, 15000all/V with 0.5 layer
s, 14700cffl/V at 1.0 layer s, 1.5
It is amplified with 14400cj/Vs in the layer, and l nA
sAsO2 results can be expected. Also, 10K as well.

At the extremely low temperature of 77, it is possible to improve the mobility by about 30%, and I
The effect of the nAs layer 9 is very large. It is understood that when the number of layers is further increased, the strain increases due to the increase in lattice mismatch, and the mobility decreases due to deterioration of the crystal, indicating that there is an optimal number of inserted layers.

I n A I A S / I n G a A S
In the heterostructure, the composition ratio of the InGaAs channel layer is 0.
FIG. 9 shows the temperature characteristics of the mobility and sheet carrier concentration of the sample. The mobility is
15100C111/VS at room temperature, 11160 at 77
0CIII/VS, 157300CIII/V at IOK
It shows a high value of S. Sheet carrier concentration is 1.60 x 10” (/ci11) at room temperature, 1.50 at 77
X1 (102 (/c-d), 10 to 1.50 X 1
0" (/d) and is well stable regardless of temperature changes.

[Other Embodiments] The present invention is not limited to the various embodiments described above, and may be modified. For example, it may be one that does not form the haphazard layer 1a, one that has an inverted hetero structure, or one that has a double hetero structure.
/I Not limited to nGaAs heterojunctions, but also InGaAs
It may also be a heterojunction with a semiconductor layer having a wider energy hand width than InGaAS.

In addition, it is not limited to those having a heterostructure, for example, the 10th
As shown in the third embodiment of the present invention in the figure, InGaAs
It is also applicable to a layer doped with an n-type (or p-type) impurity to form an active layer. In FIG. 10, electrodes 6.8 are source/drain electrodes in ohmic contact with the InGaAs layer 2, and electrode 7 is a gate electrode forming a Schottky junction.

In FIG. 10, for example, InAlAs may be grown as a buffer layer before the n-InGaAs channel layer 2 is grown. Furthermore, a non-doped Ir+Ga'As cap layer may be formed on the InGaAs layer 2 as a surface protection layer.

[Brief explanation of the drawing]

Figure 1 shows I n A I A s / I n Ga
A cross-sectional view showing the basic structure of a field effect transistor constructed with an A s / I n P substrate.
Characteristic diagram showing the relationship between the n composition ratio and the mobility of the two-dimensional electron gas layer at room temperature; FIG. 3 is a cross-sectional view showing the first embodiment of the present invention; FIG. 4(a)
4(b) is a diagram used to explain the 5QRT source temperature control method applied in the first embodiment, and FIG. 4(C) is a diagram used to explain the flux overshoot that occurs in the MBE device. Figure 5(a) shows the time change in flux when using the 5QRT source temperature control method.
．． Figure 5(b) is a characteristic diagram showing the relationship between the mobility and sheet carrier concentration at room temperature of the two-dimensional electron gas layer of 80) and the layer thickness of the channel layer. Figure 5 (C) is a characteristic diagram showing the relationship between the mobility and sheet carrier concentration at room temperature of the two-dimensional electron gas layer of 90) and the layer thickness of the channel layer.
．． 80) is a characteristic diagram showing the relationship between the mobility at room temperature and cryogenic temperature of the two-dimensional electron gas layer and the layer thickness of the channel layer. Figure 6 shows the two-dimensional electron gas layer considering the composition ratio and critical thickness. FIG. 7 is a cross-sectional view showing the second embodiment of the present invention, and FIG. 8 is a characteristic diagram showing the relationship between the number of InAs layers and the mobility of the two-dimensional electron gas layer. FIG. 9 is a temperature characteristic diagram of the mobility and sheet carrier concentration of a prototype InAlAs/InGaAs heterostructure field effect transistor, and FIG. 1O is a sectional view showing a third embodiment of the present invention. 1...Semi-insulating InP substrate, 13.1nAIAs buffer layer, 2...InGaAs channel N, 2a.
... two-dimensional electron gas layer, 3... InAlAs spacer layer, 4... nAlAs doped layer, 5. InC; aA
S cap layer, 6. Death...source/drain electrodes. 7... Gate electrode, 9... InAs layer.

Claims (10)

[Claims] (1) Indium phosphide (InP) substrate and indium gallium arsenide (InP) crystal grown on this InP substrate.
A field-effect transistor comprising a source and drain electrodes that supply carriers to the active layer, and a gate electrode that controls the amount of carriers moving in the active layer, using the InGaAs layer as an active layer. In this case, the In composition ratio of the InGaAs layer is defined to be a large value exceeding 0.53, which is lattice matched with the InP substrate, and the layer thickness of the InGaAs layer is set to a large value that exceeds the In composition ratio as the In composition ratio becomes large. 1. A field effect transistor characterized in that the film thickness is defined below a critical film thickness at which the crystal lattice can absorb the energy of the lattice distortion even if there is a lattice mismatch. (2) The field effect transistor according to claim 1, wherein the In composition ratio is defined to a value between 0.7 and 0.9. (3) The In composition ratio is 0.7, and the InGaA
3. The field effect transistor according to claim 2, wherein the thickness of the s layer is defined to be 50 nm or less. (4) The In composition ratio is 0.8, and the InGaA
3. The field effect transistor according to claim 2, wherein the layer thickness of the s-layer is defined to a value of 25 nm or less. (5) The In composition ratio is 0.9, and the InGaA
3. The field effect transistor according to claim 2, wherein the thickness of the s-layer is defined to be 13 nm or less. (6) The field effect transistor is made of the InGaAs
The semiconductor layer has a semiconductor layer having a wider energy band width than the InGaAs layer forming a heterojunction interface with the InGaAs layer, and the active layer is a two-dimensional carrier gas layer formed at the heterojunction interface of the InGaAs layer. The field effect transistor according to any one of claims 1 to 5, characterized in that: (7) The field effect transistor according to claim 6, wherein the semiconductor layer is an InAlAs layer. (8) An InAs layer is inserted at the heterojunction interface to absorb irregularities at the heterojunction interface between the semiconductor layer and the InGaAs layer.
Or the field effect transistor described in 7. (9) The field effect transistor according to claim 8, wherein the InAs layer supplies In in an amount equivalent to 0.5 layers to the heterojunction interface. (10) The field effect transistor according to any one of claims 1 to 5, wherein the InGaAs layer is doped with an impurity to serve as the active layer.