JPS6211279A - Field effect transistor - Google Patents
Field effect transistorInfo
- Publication number
- JPS6211279A JPS6211279A JP15107285A JP15107285A JPS6211279A JP S6211279 A JPS6211279 A JP S6211279A JP 15107285 A JP15107285 A JP 15107285A JP 15107285 A JP15107285 A JP 15107285A JP S6211279 A JPS6211279 A JP S6211279A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- doped
- superlattice
- fet
- field effect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title description 15
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000012535 impurity Substances 0.000 claims description 4
- 239000013078 crystal Substances 0.000 abstract description 6
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 abstract 3
- 230000003252 repetitive effect Effects 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 2
- 241000237502 Ostreidae Species 0.000 description 1
- 241000270666 Testudines Species 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 235000020636 oyster Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、動作速度の速いデジタルICやGH2帯の低
雑音増幅器などに用いることのできる電界効果トランジ
スタに関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a field effect transistor that can be used in high-speed digital ICs, low-noise amplifiers in the GH2 band, and the like.
従来の技術
近年、電界効果トランジスタは、ヘテロ構造作成技術の
進歩によって、新しい段階を迎えている。BACKGROUND OF THE INVENTION In recent years, field effect transistors have entered a new phase due to advances in heterostructure fabrication technology.
特にG a A sとA立GaAsとは、熱膨張係数お
よび格子定数の差が小さいため、良好なヘテロ接合を実
現できる。このへテロ接合を利用した電界効果トランジ
スタは、高速動作を実現できるため注目されている。In particular, GaAs and A-vertical GaAs have a small difference in thermal expansion coefficient and lattice constant, so a good heterojunction can be realized. Field-effect transistors that utilize this heterojunction are attracting attention because they can achieve high-speed operation.
このような従来のへテロ構造の電界効果トランジスタに
ついて、第3図を用いて説明する。第3図は従来のへテ
ロ接合型の電界効果トランジスタの断面図で、1は半絶
縁性G a A s基板、2はその上に成長された高純
度アンドープG a A s層、3はN型AJL x
G ax −X A s層(X″;0.3)、 4 a
はソース電極、4bはゲート電極、4cはドレイン電極
である。Such a conventional heterostructure field effect transistor will be explained with reference to FIG. FIG. 3 is a cross-sectional view of a conventional heterojunction field effect transistor, in which 1 is a semi-insulating GaAs substrate, 2 is a high purity undoped GaAs layer grown thereon, and 3 is an N Type AJL x
G ax −X A s layer (X″; 0.3), 4 a
is a source electrode, 4b is a gate electrode, and 4c is a drain electrode.
N型A蛎亀a、−2AsJ13から放出された電子は、
高純度アンドープG a A s層2とN型AuxGa
1−2As層3との界面の高純度アンドープG a A
8層2側にたまる。高純度アンドープG a A s
層2は高純度で不純物が少ないため、この電子は、不純
物と衝突する度合が小さく、移動度は大きい。The electrons emitted from N-type A oyster turtle a, -2AsJ13 are
High-purity undoped GaAs layer 2 and N-type AuxGa
1-2 High purity undoped Ga A at the interface with As layer 3
It accumulates on the 2nd side of the 8th layer. High purity undoped Ga As
Since the layer 2 has high purity and contains few impurities, the electrons collide with impurities to a small degree and have a high mobility.
発明が解決しようとする問題点
しかしながら、上記従来の構成では、N型AlxGax
AsABO39Jの混晶比Xが0.2〜0.6のときド
ナー準位が深くなり、ドナーの電子は伝導帯に上がらず
、電子密度は高くならないという現象がある(DXセン
ター)ため、電子密度を高くしようと、ドナーを多量に
ドープしても、電子密度は高くできず、予想されたほど
高速動作ができないという欠点を有していた。Problems to be Solved by the Invention However, in the above conventional configuration, N-type AlxGax
When AsABO39J's mixed crystal ratio Even if a large amount of donor is doped to increase the electron density, the electron density cannot be increased and the device cannot operate as fast as expected.
本発明は上記従来の問題点を解消するもので、電子濃度
を高くして、低雑音で高速動作を実現できる電界効果ト
ランジスタを提供することを目的とする。The present invention solves the above-mentioned conventional problems, and aims to provide a field effect transistor that can increase electron concentration and realize high-speed operation with low noise.
問題点を解決するための手段
上記問題点を解決するため、本発明の電界効果トランジ
スタは、半絶縁性G a A s基板と、この半絶縁性
G a A s基板上に形成され゛たGaAs層と、こ
のG a A s層上に形成された不純物をドープして
いないAAGaAs層と不純物をドープしたAuxGa
z −X A s層(X≦0.2)との超格子層とを備
えた構成としたものである。Means for Solving the Problems In order to solve the above problems, the field effect transistor of the present invention includes a semi-insulating GaAs substrate and a GaAs layer formed on the semi-insulating GaAs substrate. layer, an undoped AAGaAs layer formed on this GaAs layer, and an impurity-doped AuxGaAs layer.
The structure includes a z −X As layer (X≦0.2) and a superlattice layer.
作用
上記構成によれば、ドナーはAMの混晶比Xが0.2以
下のA M)(Ga1−xAs層にのみ存在することに
なる。そのため、ドナー準位が深くなって電子が伝導帯
に励起されなくなるという現象は起こらず、電子濃度を
増すことができる。Effect According to the above configuration, the donor exists only in the AM (Ga1-xAs) layer where the mixed crystal ratio The phenomenon of no longer being excited occurs, and the electron concentration can be increased.
実施例
以下、本発明の一実施例を第1図〜第2図に基づいて説
明する。EXAMPLE Hereinafter, an example of the present invention will be described based on FIGS. 1 and 2.
第1図は本発明の一実施例における電界効果トランジス
タの断面図で、11は半絶縁性G a A s基板、1
2は高純度アンドープG a A s層、13はアンド
ープAM。4Ga0.、As層とN型Au、、、Ga、
、、As層との超格子層、14aはソース電極、14b
はゲート電極。FIG. 1 is a cross-sectional view of a field effect transistor according to an embodiment of the present invention, in which 11 is a semi-insulating GaAs substrate;
2 is a high purity undoped Ga As layer, and 13 is an undoped AM layer. 4Ga0. , As layer and N-type Au, ,Ga,
,, superlattice layer with As layer, 14a is a source electrode, 14b
is the gate electrode.
14cはドレイン電極であり、超格子層13以外は第3
図に示した従来の電界効果トランジスタと同様の構成で
ある。前記超格子層13は、第2図に詳細に示すように
、各層約5原子厚の、アンドープAno、4Gaa、s
As層15とアンドープAn。2Gao、。14c is a drain electrode, and the parts other than the superlattice layer 13 are the third
The structure is similar to that of the conventional field effect transistor shown in the figure. The superlattice layer 13 is made of undoped Ano, 4 Gaa, s, each layer having a thickness of about 5 atoms, as shown in detail in FIG.
As layer 15 and undoped An. 2Gao,.
Ass層6とN型Auo、zGao、++As層17と
の繰り返しによる超格子構造となっている。A superlattice structure is formed by repeating the Ass layer 6 and the N-type Auo, zGao, and ++As layers 17.
ヘテロ接合型電界効果トランジスタにおいて、N型AA
GaAs層は電子供給源の役割をしているので、高濃度
に電子を供給できるほど、素子の特性は良くなる。本実
施例では、電子供給源であるドナーをドープした層17
のAMの混晶比Xは0.2以下、層15は超格子の実効
的な混晶比を上げるためにX≠0.4とし、この層15
には不純物をドーピングしない構造とした。x =0.
2のアンドープ層16は、バッファ層で、ドナーが層1
5の影響を受けないようにするための層である。In a heterojunction field effect transistor, N-type AA
Since the GaAs layer plays the role of an electron supply source, the higher the concentration of electrons that can be supplied, the better the characteristics of the device will be. In this example, a layer 17 doped with a donor serving as an electron supply source is used.
The mixed crystal ratio X of AM is 0.2 or less, and in order to increase the effective mixed crystal ratio of the layer 15,
The structure is such that no impurities are doped. x=0.
The undoped layer 16 of 2 is a buffer layer, and the donor is in layer 1.
This is a layer to avoid being affected by 5.
このような構成では、N型Au。2GaI、、11As
層17にドープしたドナーの電子のほぼすべてが放出さ
れ、伝導帯に励起されるため、超格子層13全体として
見ると、10”cm’程度の電子濃度が得られることに
なる。In such a configuration, N-type Au. 2GaI, 11As
Almost all of the donor electrons doped in the layer 17 are emitted and excited to the conduction band, so that when looking at the superlattice layer 13 as a whole, an electron concentration of about 10"cm" is obtained.
発明の効果
以上述べたごとく本発明によれば、ヘテロ接合型電界効
果トランジスタの電子供給源であるAMG a A s
層を超格子構造にしたので、従来よりも約1桁高い電子
濃度を実現できるため、高速デジタルICやGH2帯の
低雑音増幅器用などとして良好な特性を得ることができ
る。Effects of the Invention As described above, according to the present invention, AMG a A s which is an electron supply source of a heterojunction field effect transistor
Since the layer has a superlattice structure, it is possible to achieve an electron concentration that is approximately one order of magnitude higher than that of the conventional method, and therefore, it is possible to obtain good characteristics for use in high-speed digital ICs and low-noise amplifiers in the GH2 band.
第1図は本発明の一実施例における電界効果トランジス
タの断面図、第2図は同電界効果トランジスタにおける
超格子層の拡大断面図、第3図は従来のへテロ接合型電
界効果トランジスタの断面図である。
11・・・半絶縁性G a A s基板、12・・・高
純度アンドープGaAs層、13・・・超格子層、15
・・・アンドープAio4Gao、6As層、17−N
型Ano20ao、sAs層代理人 森 本
義 弘
第1図
第2図
第3図
rl−横り性6raAsTa&。
/2−114−ヘアンr−舟シAs層
13・−超朱与屓FIG. 1 is a sectional view of a field effect transistor according to an embodiment of the present invention, FIG. 2 is an enlarged sectional view of a superlattice layer in the same field effect transistor, and FIG. 3 is a sectional view of a conventional heterojunction field effect transistor. It is a diagram. DESCRIPTION OF SYMBOLS 11... Semi-insulating GaAs substrate, 12... High purity undoped GaAs layer, 13... Superlattice layer, 15
...Undoped Aio4Gao, 6As layer, 17-N
Type Ano20ao, sAs layer agent Morimoto
YoshihiroFigure 1Figure 2Figure 3rl- Laterality 6raAsTa&. /2-114-Hean r-Funashi As layer 13--Super vermilion
Claims (1)
板上に形成されたGaAs層と、このGaAs層上に形
成された不純物をドープしていないAl_xGa_1_
−_xAs層と不純物をドープしたAl_xGa_1_
−_xAs層(但し、不純物をドープしたAl_xGa
_1_−_xAs層のxは0.2以下とする)との超格
子層とを備えた電界効果トランジスタ。1. A semi-insulating GaAs substrate, a GaAs layer formed on this semi-insulating GaAs substrate, and an undoped Al_xGa_1_ formed on this GaAs layer.
−_xAs layer and impurity-doped Al_xGa_1_
−_xAs layer (However, Al_xGa doped with impurities)
_1_-_x x of the As layer is 0.2 or less) and a superlattice layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15107285A JPS6211279A (en) | 1985-07-08 | 1985-07-08 | Field effect transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15107285A JPS6211279A (en) | 1985-07-08 | 1985-07-08 | Field effect transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6211279A true JPS6211279A (en) | 1987-01-20 |
Family
ID=15510691
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15107285A Pending JPS6211279A (en) | 1985-07-08 | 1985-07-08 | Field effect transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6211279A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6100542A (en) * | 1996-11-19 | 2000-08-08 | Denso Corporation | InP-based HEMT with superlattice carrier supply layer |
CN105390541A (en) * | 2015-10-30 | 2016-03-09 | 江苏能华微电子科技发展有限公司 | HEMT epitaxial structure and preparation method thereof |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5963769A (en) * | 1982-10-05 | 1984-04-11 | Agency Of Ind Science & Technol | High-speed semiconductor element |
JPS6028273A (en) * | 1983-07-26 | 1985-02-13 | Nec Corp | Semiconductor device |
-
1985
- 1985-07-08 JP JP15107285A patent/JPS6211279A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5963769A (en) * | 1982-10-05 | 1984-04-11 | Agency Of Ind Science & Technol | High-speed semiconductor element |
JPS6028273A (en) * | 1983-07-26 | 1985-02-13 | Nec Corp | Semiconductor device |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6100542A (en) * | 1996-11-19 | 2000-08-08 | Denso Corporation | InP-based HEMT with superlattice carrier supply layer |
CN105390541A (en) * | 2015-10-30 | 2016-03-09 | 江苏能华微电子科技发展有限公司 | HEMT epitaxial structure and preparation method thereof |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2804041B2 (en) | Field-effect transistor | |
JPH0810751B2 (en) | Semiconductor device | |
JPS6211279A (en) | Field effect transistor | |
JPH0312769B2 (en) | ||
Chen et al. | Depletion mode modulation doped Al 0.48 In 0.52 As-Ga 0.47 In 0.53 As heterojunction field effect transistors | |
JPS63288061A (en) | Semiconductor negative resistance element | |
JP3447438B2 (en) | Field effect transistor | |
JPS61147577A (en) | Complementary semiconductor device | |
JPS63278277A (en) | Compound semiconductor device | |
JPH01128473A (en) | Field effect transistor | |
JP2921835B2 (en) | Heterojunction field effect transistor | |
JP3000489B2 (en) | Stress compensated pseudomorphic high electron mobility transistor | |
JPH084140B2 (en) | Field effect transistor | |
JPS609174A (en) | Semiconductor device | |
JP2621854B2 (en) | High mobility transistor | |
JP2000323499A (en) | Compound semiconductor epitaxial wafer | |
JP3054216B2 (en) | Semiconductor device | |
JPS6027172A (en) | Fet device | |
JP2730511B2 (en) | Heterojunction field effect transistor | |
JP2687664B2 (en) | Field effect transistor | |
JPH0684958A (en) | Inp field effect semiconductor device | |
JPS6197966A (en) | Semiconductor device | |
JPS6196769A (en) | Field effect transistor | |
JPH0666334B2 (en) | Field effect transistor | |
JPS63155772A (en) | Field effect transistor |