JPS61240170A - Method of testing semiconductor integrated circuit - Google Patents
Method of testing semiconductor integrated circuitInfo
- Publication number
- JPS61240170A JPS61240170A JP8040885A JP8040885A JPS61240170A JP S61240170 A JPS61240170 A JP S61240170A JP 8040885 A JP8040885 A JP 8040885A JP 8040885 A JP8040885 A JP 8040885A JP S61240170 A JPS61240170 A JP S61240170A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- input terminal
- semiconductor integrated
- test
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Testing Relating To Insulation (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体集積回路の静電破壊を試験する方法に
関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for testing electrostatic discharge damage in semiconductor integrated circuits.
従来の技術
従来の静電破壊試験装置を第２図に示す。従来では、第
２図のように入力端子４とアース端子２に電圧を印加す
るのみである。2. Prior Art A conventional electrostatic breakdown test apparatus is shown in FIG. Conventionally, voltage is only applied to the input terminal 4 and the ground terminal 2 as shown in FIG.
発明が解決しようとする問題点
このような従来の方法では、入力端子とアース端子との
間の静電破壊は試験できるが、入力端子と電源供給端子
との間の静電破壊の試験はできなかりた。本発明は、こ
の点を解決し、入力端子と電源供給端子との間の静電破
壊も試験できるようにするものである。Problems to be Solved by the Invention With such conventional methods, it is possible to test for electrostatic discharge damage between the input terminal and the ground terminal, but it is not possible to test for electrostatic discharge breakdown between the input terminal and the power supply terminal. There wasn't. The present invention solves this problem and makes it possible to test for electrostatic discharge damage between the input terminal and the power supply terminal.
問題点を解決するための手段
本発明は、前記問題点を解決する為に、電源供給端子と
アース端子とを接続し、その接続点と入力端子との間に
測定電圧又は試験電圧を印加し、もって入力端子とＭＷ
供給端子との閣の静電破壊をも試験する。Means for Solving the Problems In order to solve the above problems, the present invention connects a power supply terminal and a ground terminal, and applies a measurement voltage or a test voltage between the connection point and the input terminal. , with the input terminal and MW
Also test for electrostatic damage in connection with supply terminals.
作 用
本発明は、前記した構成により入力端子と電源供給端子
との間の静電破壊試験としても有効にしたものである。Function The present invention is made effective as an electrostatic breakdown test between an input terminal and a power supply terminal by the above-described configuration.
実施例 次に、本発明の実施例を第１図の回路により説明する。Example Next, an embodiment of the present invention will be explained using the circuit shown in FIG.
第１図において、電源供給端子１とアース端子２を接続
し、その接続点３と入力端子４との間に測定電圧を印加
する。５は電荷充電用コンデンサー、６は充電用電源で
ある。In FIG. 1, a power supply terminal 1 and a ground terminal 2 are connected, and a measurement voltage is applied between the connection point 3 and an input terminal 4. In FIG. 5 is a capacitor for charging, and 6 is a power source for charging.
発明の効果
以上述べたように、本発明によれば、入力端子とアース
端子との間の静電破壊を試験するだけではなく、入力端
子と電源供給端子との間の静電破壊を考えた試験が実施
でき、より市場の静電破壊に近い試験が出来る。Effects of the Invention As described above, according to the present invention, it is possible to not only test for electrostatic damage between an input terminal and a ground terminal, but also to consider electrostatic damage between an input terminal and a power supply terminal. Tests can be performed, and tests that are closer to those on the market for electrostatic damage can be performed.
第１図は本発明の実施例における静電破壊試験回路を示
すものである。第２図は従来からの静電破壊試験回路で
ある。
１・・・電源供給端子 ２・・・アース端子 ３・・・
接続点 ４・・・入力端子 ５・・・電荷充電用コンデ
ンサー〇・・・充電用電源 ７・・・半導体集積回路
８・・・充電、放電切換用スイッチ
特許出願人 松下電子工業株式会社
第１図
第２図FIG. 1 shows an electrostatic breakdown test circuit according to an embodiment of the present invention. FIG. 2 shows a conventional electrostatic breakdown test circuit. 1...Power supply terminal 2...Earth terminal 3...
Connection point 4...Input terminal 5...Charging capacitor〇...Charging power source 7...Semiconductor integrated circuit
8...Charging/discharging switch Patent applicant: Matsushita Electronics Co., Ltd. Figure 1 Figure 2
Claims (1)
を共通接続し、その接続点と制御入力端子または出力端
子との間に静電破壊試験用高電圧を印加することを特徴
とする集積回路の試験方法。A first terminal and a second terminal for power supply of a semiconductor integrated circuit are commonly connected, and a high voltage for electrostatic breakdown test is applied between the connection point and a control input terminal or an output terminal. Test methods for integrated circuits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8040885A JPS61240170A (en) | 1985-04-17 | 1985-04-17 | Method of testing semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8040885A JPS61240170A (en) | 1985-04-17 | 1985-04-17 | Method of testing semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61240170A true JPS61240170A (en) | 1986-10-25 |
Family
ID=13717463
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8040885A Pending JPS61240170A (en) | 1985-04-17 | 1985-04-17 | Method of testing semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61240170A (en) |
-
1985
- 1985-04-17 JP JP8040885A patent/JPS61240170A/en active Pending
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