JPH0480349B2 - - Google Patents
Info
- Publication number
- JPH0480349B2 JPH0480349B2 JP58105715A JP10571583A JPH0480349B2 JP H0480349 B2 JPH0480349 B2 JP H0480349B2 JP 58105715 A JP58105715 A JP 58105715A JP 10571583 A JP10571583 A JP 10571583A JP H0480349 B2 JPH0480349 B2 JP H0480349B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- external connection
- test
- connection terminal
- electrostatic breakdown
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000012360 testing method Methods 0.000 claims description 33
- 239000004065 semiconductor Substances 0.000 claims description 29
- 230000015556 catabolic process Effects 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 10
- 238000010998 test method Methods 0.000 claims description 9
- 230000006378 damage Effects 0.000 claims description 7
- 238000007599 discharging Methods 0.000 claims description 7
- 238000005259 measurement Methods 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
- 239000000057 synthetic resin Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/001—Measuring interference from external sources to, or emission from, the device under test, e.g. EMC, EMI, EMP or ESD testing
- G01R31/002—Measuring interference from external sources to, or emission from, the device under test, e.g. EMC, EMI, EMP or ESD testing where the device under test is an electronic circuit
Description
【発明の詳細な説明】
〔技術分野〕
本発明は、半導体装置、特に半導体集積回路の
静電破壊試験を行う際に好適な試験方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a test method suitable for conducting electrostatic breakdown tests on semiconductor devices, particularly semiconductor integrated circuits.
〔背景技術〕
半導体集積回路の特性試験は多項目にわたる
が、そのうちの一つに静電破壊試験がある。この
試験には、いわゆるコンデンサ方式とも呼ばれる
方法がある。この方法は、人体の静電容量に対応
する200PF程度のコンデンサに充電された電荷を
半導体集積回路に印加し、半導体集積回路の破壊
の有無を測定するものである。[Background Art] Characteristic tests for semiconductor integrated circuits include many items, one of which is an electrostatic discharge test. This test has a method called the so-called capacitor method. In this method, a charge stored in a capacitor of about 200 PF, which corresponds to the capacitance of the human body, is applied to a semiconductor integrated circuit, and the presence or absence of damage to the semiconductor integrated circuit is measured.
この方法が採用される技術的思想は、半導体装
置を運搬する際に、ケースと半導体装置との間に
静電容量、或いは人体と半導体装置との間の静電
容量に蓄積された電荷により破壊が発生する、と
の考えに立脚している。 The technical idea behind this method is that when a semiconductor device is transported, it is destroyed due to the electric charge accumulated in the capacitance between the case and the semiconductor device, or between the human body and the semiconductor device. It is based on the idea that this will occur.
ところで、半導体装置は上述のような蓄積電荷
による破壊のみならず、半導体装置のストレイキ
ヤパシテイに充電されていた電荷が放電し、これ
により静電破壊が発生することがある。したがつ
て、このような状況下における静電破壊試験を行
なう必要がある。かかる静電破壊試験の具体的方
法は、特開昭57−80557号公報に開示されている。
かかる公報に開示の方法は、絶縁外周部いわゆる
封止体に直流高電圧を接触電極から印加し、その
後、半導体装置の外部電極いわゆる外部接続端子
を基準電位電極に接触させるものである。しかし
ながら、かかる方法によれば、接触電極と封止体
との接触状態により半導体装置に誘導される電荷
量が不安定となり一定した静電破壊試験が困難と
なる。 Incidentally, a semiconductor device may not only be destroyed by the accumulated charge as described above, but also the charge stored in the stray capacitance of the semiconductor device may be discharged, resulting in electrostatic damage. Therefore, it is necessary to conduct an electrostatic breakdown test under such conditions. A specific method for such an electrostatic breakdown test is disclosed in JP-A-57-80557.
The method disclosed in this publication is to apply a DC high voltage to an insulating outer peripheral portion, so-called a sealed body, from a contact electrode, and then bring an external electrode, so-called external connection terminal, of the semiconductor device into contact with a reference potential electrode. However, according to this method, the amount of charge induced in the semiconductor device becomes unstable depending on the contact state between the contact electrode and the sealing body, making it difficult to conduct a constant electrostatic discharge test.
本発明の目的は、半導体装置に蓄積された電荷
による静電破壊の有無を測定する試験方法、特に
簡単かつ安定した試験方法を提供することにあ
る。
An object of the present invention is to provide a test method, particularly a simple and stable test method, for measuring the presence or absence of electrostatic damage caused by charges accumulated in a semiconductor device.
本願において開示される発明の概要いを簡単に
説明すれば、下記のとおりである。
A brief overview of the invention disclosed in this application is as follows.
すなわち、所定の電圧を半導体装置の外部接続
端子に供給し、ストレイキヤパシテイに充電す
る。その後、ストレイキヤパシテイに充電された
電荷を放電し、この放電時における破壊の有無を
測定する試験方法である。 That is, a predetermined voltage is supplied to the external connection terminal of the semiconductor device to charge the stray capacity. This is a test method in which the charge stored in the stray capacitance is then discharged and the presence or absence of destruction during this discharge is measured.
実施例 １
以下、第１図を参照して、本発明を適用した静
電破壊試験方法の一実施例を述べる。なお、以下
に述べる実施例において、半導体装置としては、
半導体集積回路（以下においてICという）が用
いられている。このICは、第１図から明らかな
ようにパツケージ本体（封止体）とその本体から
導出する複数の外部接続端子から成るものであ
り、周知構造のものである。Example 1 An example of the electrostatic breakdown test method to which the present invention is applied will be described below with reference to FIG. In addition, in the examples described below, the semiconductor device is as follows:
Semiconductor integrated circuits (hereinafter referred to as ICs) are used. As is clear from FIG. 1, this IC consists of a package body (sealed body) and a plurality of external connection terminals led out from the body, and has a well-known structure.
試験電圧V1は、例えばDC1000V程度の電圧で
ある。抵抗R1は、例えば100MΩ程度の抵抗値で
あり、これは可変抵抗であつてもよい。100MΩ
もの高抵抗を使用する理由は、急速充電により
IC1内部の電位分布が不明確な状態で破壊しない
ようにするためである。スイツチSW1は、ICの
ストレイキヤパシテイ（図示せず）に対する充電
と、充電された電荷の放電を行うためのスイツチ
である。 The test voltage V 1 is, for example, about 1000V DC. The resistor R 1 has a resistance value of, for example, about 100 MΩ, and may be a variable resistor. 100MΩ
The reason for using high resistance is because of fast charging.
This is to prevent IC 1 from being destroyed when the potential distribution inside it is unclear. The switch SW 1 is a switch for charging the stray capacitance (not shown) of the IC and discharging the charged electric charge.
静電破壊試験を行う際は、スイツチSW1を固定
接点ａに切換える。IC1の外部接続端子に、抵抗
R1を介して試験電圧V1が供給される。この結果、
IC1内の浮遊容量（ストレイキヤパシテイ）に電
荷が充電される。なお、上記ストレイキヤパシテ
イをC1とすると、等価的には第１図の如く図示
することができる。 When performing an electrostatic discharge test, switch SW 1 to fixed contact a. Connect a resistor to the external connection terminal of IC 1 .
A test voltage V 1 is supplied via R 1 . As a result,
Stray capacitance inside IC 1 is charged with electric charge. Note that if the above stray capacity is C1 , it can be equivalently illustrated as shown in FIG.
次に、スイツチSW1を固定接点ｂに切換える。
ストレイキヤパシテイC1に充電されていた電荷
が、スイツチSW1を介してアースラインへ放電さ
れる。その後、IC1が破壊されているか否かを検
査する。 Next, switch SW 1 is switched to fixed contact b.
The charge stored in the stray capacitance C1 is discharged to the ground line via the switch SW1 . After that, it is checked whether IC 1 is destroyed or not.
上記静電破壊試験は、IC1の各外部接続端子に
つき個別に行つてよく、或いは同時に行つてもよ
い。特に各外部接続端子につき個別に行なう場合
は、各外部接続端子に対して、どこくらいの試験
電圧（帯電電圧）で破壊するかを高精度に試験す
ることができる。そして、放電破壊試験を行つた
後、測定装置により特性測定を行ない、IC1の静
電破壊に対する耐性を評価する。 The electrostatic breakdown test described above may be performed individually for each external connection terminal of IC 1 , or may be performed simultaneously. In particular, when testing is performed for each external connection terminal individually, it is possible to highly accurately test each external connection terminal at what test voltage (electrostatic voltage) is required to cause breakdown. After performing the discharge breakdown test, characteristics are measured using a measuring device to evaluate the resistance of IC 1 to electrostatic breakdown.
実施例 ２
次に、第２図を参照して本発明の第２の実施例
を述べる。なお、上記第１の実施例と同一部分に
は同一の符号を付し、その説明を省略する。Embodiment 2 Next, a second embodiment of the present invention will be described with reference to FIG. Note that the same parts as in the first embodiment are given the same reference numerals, and the explanation thereof will be omitted.
IC1は測定台１上に載置され、IC1と測定台１と
の間には１〜2PFD程度のストレイキヤパシテイ
C2が介在している。上記測定台１は、導体で構
成されたものである。この結果、IC1内のストレ
イキヤパシテイ、更にアースラインとの間のスト
レイキヤパシテイC2がともに安定する。また、
電圧供給側からみた容量値を増大し、実際より強
制した静電破壊試験を行い得る。 IC 1 is placed on measurement stand 1, and there is a stray capacitance of about 1 to 2 PFD between IC 1 and measurement stand 1.
C2 is intervening. The measuring table 1 is made of a conductor. As a result, both the stray capacity within IC 1 and the stray capacity C 2 between it and the ground line are stabilized. Also,
By increasing the capacitance value seen from the voltage supply side, it is possible to conduct a more forced electrostatic breakdown test than in reality.
この結果、試験精度（再現性）の向上を計るこ
とができる。なお、上記測定台１は、導体に限定
されるものではなく、合成樹脂等の誘電体であつ
てもよい。 As a result, it is possible to improve test accuracy (reproducibility). Note that the measurement table 1 is not limited to a conductor, and may be made of a dielectric material such as synthetic resin.
実施例 ３
次に、第３図を参照して本発明の第３の実施例
を述べる。なお、上述した第１及び第２の実施例
と同一部分には同一の符号を付し、その説明を省
略する。Embodiment 3 Next, a third embodiment of the present invention will be described with reference to FIG. Note that the same parts as in the first and second embodiments described above are denoted by the same reference numerals, and the explanation thereof will be omitted.
IC1内のストレイキヤパシテイC1に充電する際
は、スイツチSW1を固定接点ａに切換える。放電
させる際は、スイツチSW1を固定接点ｂに切換え
るのであるが、充電から放電までの間にIC1に常
に試験電圧V1がかけられている。従つて、スイ
ツチSW1の切換え時間中に、ストレイキヤパシテ
イC1に充電された電荷が、IC1内で放電すること
がない。 When charging the stray capacity C 1 in IC 1 , switch SW 1 to fixed contact a. When discharging, switch SW 1 is switched to fixed contact b, but test voltage V 1 is always applied to IC 1 between charging and discharging. Therefore, during the switching time of the switch SW1 , the charge stored in the stray capacitance C1 is not discharged within the IC1 .
すなわち、本実施例における静電破壊試験方法
によれば試験精度（再現性）が更に向上する。 That is, according to the electrostatic breakdown test method in this example, test accuracy (reproducibility) is further improved.
〔効果〕
(1) 半導体装置内に充電された電荷を放電させ、
放電時の静電破壊試験を行うことができるの
で、実際に則した静電破壊試験となり、半導体
装置の試験精度が向上する。[Effects] (1) Discharges the electric charge stored in the semiconductor device,
Since it is possible to perform an electrostatic breakdown test during discharge, the electrostatic breakdown test is more realistic and the testing accuracy of semiconductor devices is improved.
(2) 上記(1)により、静電破壊に対する有効な対策
をとることができ、半導体装置の品質向上を計
ることができる。(2) According to (1) above, effective measures against electrostatic damage can be taken and the quality of semiconductor devices can be improved.
(3) 試験方法が簡単であるため、高速試験が可能
になる。すなわち、本発明によれば各実施例の
図から明らかなように、半導体装置の一つの外
部接続端子を通して充放電を行なうものである
ため、測定用接触子はその外部接続端子へ接触
させるだけでよく、極めて簡単に行ない得るこ
とができる。(3) The simple testing method enables high-speed testing. That is, according to the present invention, as is clear from the drawings of each embodiment, since charging and discharging is performed through one external connection terminal of a semiconductor device, the measurement contact only needs to be brought into contact with that external connection terminal. Well, it can be done very easily.
(4) (1)〜(3)により、静電破壊試験の一方法とし
て、確立した試験方法にすることができる。(4) According to (1) to (3), this test method can be established as a method for electrostatic breakdown testing.
以下に、本発明者等によつてなされた発明を実
施例にもとづき具体的に説明したが、本発明は上
記実施例に限定されるものではなく、その要旨を
逸脱しない範囲で種々変形可能であることはいう
までもない。 The invention made by the present inventors has been specifically explained below based on Examples, but the present invention is not limited to the above Examples, and can be modified in various ways without departing from the gist thereof. It goes without saying that there is.
例えば、スイツチSW1は充電用スイツチと放電
用スイツチとに分離してもよい。また、スイツチ
SW1の固定接点ｂとアースラインとの間に、抵抗
やコンデンサを介在させ、放電時に時定数をもた
せるようにしてもよい。 For example, the switch SW 1 may be separated into a charging switch and a discharging switch. Also, switch
A resistor or a capacitor may be interposed between the fixed contact b of SW 1 and the earth line to provide a time constant during discharge.
更に、第２の実施例で述べた測定台１は、半導
体装置を収納するケース、或いは運搬用のケース
であつてよい。 Furthermore, the measurement table 1 described in the second embodiment may be a case for storing a semiconductor device or a case for transportation.
以上の説明では、主として本発明者等によつて
なされた発明を、その背景となつた利用分野であ
る半導体装置の静電破壊試験に適用した場合につ
いて説明したが、それに限定されるものではな
い。例えば、配線基板の静電破壊試験に適用する
こともできる。
In the above explanation, the invention made by the present inventors was mainly applied to the electrostatic breakdown test of semiconductor devices, which is the background field of application, but the invention is not limited to this. . For example, it can also be applied to electrostatic damage testing of wiring boards.
本発明は少なくとも、静電容量に充電された電
荷が放電されたときの、各種影響を測定する際に
用いることができる。 The present invention can be used at least when measuring various effects when the charge stored in the capacitance is discharged.
第１図は本発明の第１の実施例を示す静電破壊
試験を行うための回路図、第２図は本発明の第２
の実施例を示す静電破壊試験を行うための回路
図、第３図は本発明の第３の実施例を示す静電破
壊試験を行うための回路図である。
IC1……被測定半導体装置、V1……試験電圧、
R1……抵抗、SW1……スイツチ、１……測定台、
C1……ストレイキヤパシテイ。
FIG. 1 is a circuit diagram for conducting an electrostatic breakdown test showing a first embodiment of the present invention, and FIG.
FIG. 3 is a circuit diagram for conducting an electrostatic breakdown test showing a third embodiment of the present invention. IC 1 ... Semiconductor device under test, V 1 ... Test voltage,
R 1 ...Resistance, SW 1 ...Switch, 1...Measurement stand,
C 1 ... Stray capacity.
Claims (1)
導出する複数の外部接続端子とを具備した半導体
装置に対する静電破壊試験方法であつて、その半
導体装置の外部接続端子の一つに電源と所望抵抗
とが直接接続された電圧供給回路手段を電気的接
続させ、その外部接続端子にその抵抗を介して所
定の試験電圧を供給することによりその外部接続
端子を通して半導体装置に存在する浮遊容量に電
荷を蓄積する段階と、蓄積された電荷をその外部
接続端子を通して放電する段階とを有することを
特徴とする半導体装置の静電破壊試験方法。 ２ 前記複数の所望外部接続端子のそれぞれに対
して個別に前記蓄積する段階と前記放電する段階
とを行なうことを特徴とする特許請求の範囲第１
項記載の半導体装置の静電破壊試験方法。[Scope of Claims] 1. An electrostatic breakdown test method for a semiconductor device comprising a package body and a plurality of external connection terminals led out from the package body, the method comprising: connecting a power source to one of the external connection terminals of the semiconductor device; By electrically connecting the voltage supply circuit means in which the and the desired resistance are directly connected, and supplying a predetermined test voltage to the external connection terminal through the resistance, the stray capacitance existing in the semiconductor device is removed through the external connection terminal. 1. A method for testing electrostatic discharge damage of a semiconductor device, comprising the steps of accumulating electric charge in a semiconductor device, and discharging the accumulated electric charge through an external connection terminal thereof. 2. Claim 1, characterized in that the accumulating step and the discharging step are individually performed for each of the plurality of desired external connection terminals.
Electrostatic breakdown test method for semiconductor devices as described in Section 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58105715A JPS59231458A (en) | 1983-06-15 | 1983-06-15 | Electrostatic destruction testing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58105715A JPS59231458A (en) | 1983-06-15 | 1983-06-15 | Electrostatic destruction testing method |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2155227A Division JPH0315773A (en) | 1990-06-15 | 1990-06-15 | Electrostatic breakdown test equipment for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59231458A JPS59231458A (en) | 1984-12-26 |
| JPH0480349B2 true JPH0480349B2 (en) | 1992-12-18 |
Family
ID=14415028
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58105715A Granted JPS59231458A (en) | 1983-06-15 | 1983-06-15 | Electrostatic destruction testing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59231458A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6073375A (en) * | 1983-09-30 | 1985-04-25 | Oki Electric Ind Co Ltd | Method of testing semiconductor apparatus |
| JPS62145170U (en) * | 1986-03-07 | 1987-09-12 | ||
| US4806857A (en) * | 1986-04-11 | 1989-02-21 | Oki Electric Industry Co., Ltd. | Apparatus for testing semiconductor devices |
| JPH0711556B2 (en) * | 1986-04-11 | 1995-02-08 | 沖電気工業株式会社 | Electrostatic breakdown voltage test method and device |
| JP2572816B2 (en) * | 1988-06-10 | 1997-01-16 | 株式会社日立製作所 | Electrostatic breakdown test equipment |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5780577A (en) * | 1980-11-06 | 1982-05-20 | Mitsubishi Electric Corp | Testing method of semiconductor |
-
1983
- 1983-06-15 JP JP58105715A patent/JPS59231458A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5780577A (en) * | 1980-11-06 | 1982-05-20 | Mitsubishi Electric Corp | Testing method of semiconductor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59231458A (en) | 1984-12-26 |
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