JPS62145170U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1: A circuit diagram showing the principle of electrostatic damage testing for integrated circuits, which is the premise of the present invention. DESCRIPTION OF SYMBOLS 1... integrated circuit, 21, 22... switch, 3... voltmeter, 41... voltage power supply, 42... programmer controller, 43... current source, 51, 52... pin switching device. Fig. 2a: A broken side view showing the entire structure of the device according to the present invention, Fig. 2b: A top view showing the entire structure of the device according to the present invention, Fig. 2c: A schematic diagram of the circuit showing the configuration of the measuring section of the present invention, Fig. Figure 2d: A schematic diagram of a circuit showing the configuration of the electrostatic application section of the present invention. 2... Electrostatic applying section, 3... Measuring section, 4... Moving device,
21... Contact pin for application, 31... Contact pin for measurement,
6... Socket board, 61... Contact terminal, 7... Socket board rack (no need to store to load socket board). Figures 3a and 3b: A plan view of an embodiment in which contact terminals are arranged in two rows; Figures 4a and 4b: a side view showing an embodiment of a mechanism for moving contact pins for application and connecting contact terminals in succession; Figures 5a and 5b: A plan view of an embodiment in which contact terminals are arranged in one row and two rows of ground pins are arranged in parallel, 62: Ground pin. Figures 6a and 6b: Top and side views of an embodiment in which one row of contact terminals is arranged on both sides and two rows of ground pins are arranged in parallel; Figure 7:
FIG. 7 is a side view of an embodiment using either of two application contact pins for use in the embodiment of FIG. 6;

Claims (1)

[Claims for Utility Model Registration] (1) A socket base having a plurality of sockets for inserting the terminals of an integrated circuit, contact terminals connected to the sockets, and contact pins for applying voltage by selecting the contact terminals. An electrostatic charge applying device applies an electrostatic charge to a specific terminal of an integrated circuit by bringing the terminals into contact with each other, and a measuring contact pin is brought into contact with all the contact terminals to determine the operating characteristics between each terminal and the possibility of electrostatic damage. An electrostatic damage tester for integrated circuits that consists of a measuring device that measures the presence or absence of a socket, and a moving mechanism that moves the socket board. (2) The electrostatic breakdown tester for integrated circuits according to claim (1), characterized in that the contact terminals are arranged in a straight line. (3) The electrostatic breakdown tester for integrated circuits according to claim (1), characterized in that the contact terminals are arranged circumferentially. (4) For each socket from each terminal of the integrated circuit,
The electrostatic charge of an integrated circuit according to claim (1) for registration of a utility model, characterized in that contact terminals for input and output are arranged in two rows, and contact pins for application to select the contact terminals are provided for each row. destructive tester. (5) Arrange the contact terminals connected to each socket in one row, and one of the contact terminals selected
The electrostatic charge of the integrated circuit according to claim (1) of claim (1) for registration of a utility model, characterized in that one terminal is connected to ground, and an electrostatic charge is applied between the terminal and the other terminal by a contact pin for application. destructive tester.