JPS6159657B2 - - Google Patents
Info
- Publication number
- JPS6159657B2 JPS6159657B2 JP55064982A JP6498280A JPS6159657B2 JP S6159657 B2 JPS6159657 B2 JP S6159657B2 JP 55064982 A JP55064982 A JP 55064982A JP 6498280 A JP6498280 A JP 6498280A JP S6159657 B2 JPS6159657 B2 JP S6159657B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- terminal
- voltage
- switching element
- voltage application
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 9
- 230000015556 catabolic process Effects 0.000 claims description 7
- 238000011156 evaluation Methods 0.000 claims description 7
- 238000000034 method Methods 0.000 description 5
- 238000009413 insulation Methods 0.000 description 4
- 239000000523 sample Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
この発明は半導体集積回路に用いられる絶縁膜
の破壊故障を、ウエハ状態で評価する評価用半導
体素子に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an evaluation semiconductor element for evaluating breakdown failure of an insulating film used in a semiconductor integrated circuit in a wafer state.
絶縁膜の評価に、長時間の電圧印加が重要であ
るという事が最近わかつてきた。 It has recently become clear that long-term voltage application is important for evaluating insulating films.
すなわち、いわゆる絶縁膜破壊電圧以下の電圧
であつても長時間の印加により絶縁膜破壊が起
り、これが直接的に絶縁膜の信頼性に対応する。 That is, even if the voltage is lower than the so-called insulation film breakdown voltage, the insulation film will break down if it is applied for a long time, and this directly affects the reliability of the insulation film.
従来、絶縁膜の評価は、後述の２つの方法でな
されていた。 Conventionally, insulating films have been evaluated using two methods described below.
一つはウエハを小さなダイに細分し、それぞれ
のダイに含まれている絶縁膜素子の２端子がパツ
ケージの外部ピンと接続されるように組立てる。 One is to subdivide the wafer into small dies and assemble them so that the two terminals of the insulating film element included in each die are connected to the external pins of the package.
しかる後に、パツケージの外部ピンを介して絶
縁膜素子の２端子に電圧を印加する事で絶縁膜破
壊故障を評価する。この方法では、簡単な治具で
大量の素子に電気的ストレスを同時印加する事が
可能であるという利点があるが、パツケージに組
立てる時間が長くかかり、その費用が高くつくと
いう欠点がある。 Thereafter, a voltage is applied to two terminals of the insulating film element via an external pin of the package to evaluate the insulating film breakdown failure. This method has the advantage that it is possible to simultaneously apply electrical stress to a large number of elements using a simple jig, but has the disadvantage that it takes a long time to assemble the devices into a package, and the cost is high.
もう一つの方法は、ウエハ状態で、プローブ接
触により各絶縁膜素子に電圧印加していくもので
ある。 Another method is to apply a voltage to each insulating film element by contacting a probe in the wafer state.
この方法はウエハ状態で行なうので、パツケー
ジの組立て時間及びコストが省ける、という利点
がある。しかし、プローブ接触できるピン数は、
たかだか10〜100ポイント程度であるため、ウエ
ハ上の全絶縁膜素子（数干個）に電圧印加するに
は、非常に長期間かかつてしまうという欠点があ
つた。 Since this method is carried out in the wafer state, it has the advantage of saving time and cost for assembling the package. However, the number of pins that can be contacted by the probe is
Since the number of points is about 10 to 100 at most, it has the disadvantage that it takes a very long time to apply voltage to all the insulating film elements (several pieces) on the wafer.
この発明は、上記のような従来の方法の欠点を
除去するためになされたもので、各絶縁膜素子の
一端子をそのまま外部端子とすると同時に、それ
ぞれ一つの共通信号でオン・オフするスウイツチ
ング素子を介して共通の外部端子に接続する事に
よつて、絶縁膜素子への電圧印加を同時に行なえ
るようにし、パツケージ組立を不要にすると共に
評価時間の大巾な短縮を達成しようとするもので
ある。 This invention was made in order to eliminate the drawbacks of the conventional method as described above, and it is possible to use one terminal of each insulating film element as an external terminal as it is, and at the same time to create a switching element that is turned on and off by one common signal. By connecting to a common external terminal through a 3-pin connector, voltage can be applied to the insulating film elements at the same time, eliminating the need for package assembly and significantly shortening evaluation time. be.
以下、この発明の一実施例を図について説明す
る。図は、本発明による評価用半導体素子を示し
ており、１は半導体ウエハ、２はこの半導体ウエ
ハ上に形成された絶縁膜素子、３はこの絶縁膜素
子が破壊されたかどうかをチエツクするためのチ
エツク用外部端子、４はスウイツチング素子で、
絶縁膜素子をチエツクする時は、スウイツチング
用信号端子６からの信号でオフされ、全絶縁膜素
子に電圧を印加する時はオンにされて電圧印加用
外部端子５から全端子３に電圧が印加する。７は
絶縁膜素子全部の共通接地端子である。 An embodiment of the present invention will be described below with reference to the drawings. The figure shows a semiconductor device for evaluation according to the present invention, where 1 is a semiconductor wafer, 2 is an insulating film element formed on this semiconductor wafer, and 3 is a device for checking whether or not this insulating film element has been destroyed. External terminal for checking, 4 is a switching element,
When checking the insulating film elements, it is turned off by a signal from the switching signal terminal 6, and when applying voltage to all the insulating film elements, it is turned on and voltage is applied from the external terminal 5 for voltage application to all terminals 3. do. 7 is a common ground terminal for all insulating film elements.
絶縁膜の評価において、数μsecから数10時間
までの範囲で電圧を印加する必要があり、電圧印
加前後のリーク電流チエツクで絶縁膜の破壊を調
べるのが一般的である。絶縁膜破壊率と電圧印加
時間の関係から絶縁膜の信頼性を推定する事が可
能となる。次に評価手順について説明する。 When evaluating an insulating film, it is necessary to apply a voltage for a period of several microseconds to several tens of hours, and it is common to check for leakage current before and after applying the voltage to check for breakdown of the insulating film. It becomes possible to estimate the reliability of the insulating film from the relationship between the breakdown rate of the insulating film and the voltage application time. Next, the evaluation procedure will be explained.
まず、端子６からの信号で、スウイツチング素
子４をオフにした状態でウエハ１上の全絶縁膜素
子２に対し、チエツク用外部端子３から順次リー
クチエツクを行なう。次に端子６からの信号でス
ウイツチング素子４をオンさせ、端子５から全絶
縁膜素子２に所定の時間電圧を印加する。しかる
後に、スウイツチング素子４をオフさせ、再び全
絶縁膜素子２のリークチエツクを行なう。上記作
業を繰り返す事によつて絶縁膜破壊故障率対電圧
印加時間の関係が求められる。 First, with the switching element 4 turned off using a signal from the terminal 6, a leak check is sequentially performed on all the insulating film elements 2 on the wafer 1 starting from the external check terminal 3. Next, the switching element 4 is turned on by a signal from the terminal 6, and a voltage is applied from the terminal 5 to all the insulating film elements 2 for a predetermined time. Thereafter, the switching element 4 is turned off and a leak check of all the insulating film elements 2 is performed again. By repeating the above operations, the relationship between the insulation film breakdown failure rate and the voltage application time can be determined.
本発明は、上記電圧印加が全絶縁膜素子共通に
行なえる事にあり、例えば、1000個の絶縁膜素子
に対し、100時間の電圧印加が必要である場合を
考えると、従来の方法であれば、100時間×（１０００
／１０
回〜１０００／１００回）＝10000時間〜1000時間かか
つてしま
うのに対し、本発明の場合には、100時間です
む。 The present invention is that the voltage application described above can be applied to all insulating film elements in common.For example, if we consider a case where voltage application is required for 100 hours to 1000 insulating film elements, it is possible to apply the voltage to all insulating film elements. For example, 100 hours x (1000
/10 times to 1000/100 times) = 10000 hours to 1000 hours, whereas in the case of the present invention, it only takes 100 hours.
なお、第１図においては、スウイツチング素子
としてMOSトランジスタを用いているが、スウ
イツチング素子であれば、どんなものを用いても
同様の効果がある。 In FIG. 1, a MOS transistor is used as the switching element, but any switching element can be used to achieve the same effect.
以上のように、この発明によれば、各絶縁膜素
子の一端子をそれぞれ一つのスウイツチング素子
を介して共通の電圧印加端子に接続したので、電
圧印加がウエハ上の全絶縁膜素子に同時に行なえ
るようになり、大巾な評価時間の短縮が可能とな
る。また各絶縁膜素子の２端子がパツケージの外
部ピンと接続されるように組立てるような手間が
不要となる利点がある。 As described above, according to the present invention, one terminal of each insulating film element is connected to a common voltage application terminal through one switching element, so that voltage can be applied to all insulating film elements on the wafer at the same time. This makes it possible to significantly reduce evaluation time. Another advantage is that there is no need to assemble the two terminals of each insulating film element to connect them to the external pins of the package.
図は、本発明による評価用半導体素子の一実施
例を示す構成図である。
１……半導体ウエハ、２……絶縁膜素子、３…
…絶縁膜素子のチエツク用端子、４……スウイツ
チング素子、５……電圧印加用端子、６……スウ
イツチング用信号端子、７……絶縁膜素子の共通
接地端子。
FIG. 1 is a configuration diagram showing an embodiment of a semiconductor device for evaluation according to the present invention. 1... Semiconductor wafer, 2... Insulating film element, 3...
...terminal for checking the insulating film element, 4... switching element, 5... terminal for voltage application, 6... signal terminal for switching, 7... common grounding terminal for the insulating film element.
Claims (1)
障をウエハ状態で評価するものにおいて、各絶縁
膜素子の一端子をそのままチエツク用端子とする
と同時に、それぞれ一つの共通信号でオン・オフ
するスウイツチング素子を介して共通の電圧印加
用端子に接続した事を特徴とする評価用半導体素
子。1. In evaluating breakdown failures of insulating films used in semiconductor integrated circuits in the wafer state, one terminal of each insulating film element is used as a check terminal, and at the same time, a switching element that turns on and off with one common signal is used. A semiconductor device for evaluation, characterized in that it is connected to a common voltage application terminal through a terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6498280A JPS56161650A (en) | 1980-05-15 | 1980-05-15 | Semiconductor element for appraisement |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6498280A JPS56161650A (en) | 1980-05-15 | 1980-05-15 | Semiconductor element for appraisement |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56161650A JPS56161650A (en) | 1981-12-12 |
| JPS6159657B2 true JPS6159657B2 (en) | 1986-12-17 |
Family
ID=13273764
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6498280A Granted JPS56161650A (en) | 1980-05-15 | 1980-05-15 | Semiconductor element for appraisement |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56161650A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63312648A (en) * | 1987-06-15 | 1988-12-21 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of semiconductor integrated circuit chip |
| JP2591800B2 (en) * | 1988-08-12 | 1997-03-19 | 沖電気工業株式会社 | Semiconductor integrated circuit defect detection method and defect detection circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5051267A (en) * | 1973-09-07 | 1975-05-08 | ||
| JPS5332679A (en) * | 1976-09-08 | 1978-03-28 | Hitachi Ltd | Easy to inspect lsi mounting package |
-
1980
- 1980-05-15 JP JP6498280A patent/JPS56161650A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5051267A (en) * | 1973-09-07 | 1975-05-08 | ||
| JPS5332679A (en) * | 1976-09-08 | 1978-03-28 | Hitachi Ltd | Easy to inspect lsi mounting package |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56161650A (en) | 1981-12-12 |
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