JPS60235455A - Dynamic memory - Google Patents

Abstract

PURPOSE:To execute a withstanding voltage test for a dynamic memory completely by forming an electrode for external connection connected to a capacitor electrode. CONSTITUTION:With the memory chip, an electrode 12 for external connection connected by lead sections 11 is shaped to capacitor electrodes 7, and the electrode 12 for external connection has structure in which a needle for a wafer prober can be brought into contact. A withstanding voltage test for an insulating layer in such a dynamic memory is executed by applying voltage between the electrode 12 for external connection and a semiconductor substrate 1 at a step such as the last (before bonding) of a wafer step, and voltage can be applied to the insulating layer without applying supply voltage for a circuit, thus allowing the test by applying voltage up to approximately four times as mush as operating voltage. Accordingly, chips having defective withstanding voltage can be thrown out positively by utilizing the electrode for external connection.

Description

[Detailed description of the invention] [Technical field of invention] The present invention is a MOIII type dyna type dynomic memory.

[Technical Background of the Invention and Background Art Problems 1 The MO8 type dynamic memory is composed of a plurality of memory cells arranged, and each memory cell is made of a semiconductor, for example, p
MO8111nT formed on the surface of a type silicon substrate
and a capacitor, the capacitor having capacitor electrodes facing each other through an insulating layer, that is, a dielectric layer, on a semiconductor substrate. FIGS. 1 to 3 show an example of such a memory cell. It is. In the example shown, the mesa portions 1O of the p-type silicon substrate 1 are formed close to each other on the surface of the mesa portions 1O. The type regions 2 and 3 constitute a drain and a source, respectively, and a region between the drain 2 and the source 30 is disposed facing each other with an insulating layer, for example, a 5 in 2 silicon oxide film 4a having a thickness of about 200 μm interposed therebetween. A conductive layer such as a polysilicon layer 5 constitutes a capacitor electrode.

These form a front circuit as shown in FIG. That is, a capacitor electrode 7 and an insulating layer 4 are formed thereon.
A capacitor C is formed by the regions of the substrate facing each other via b, and a transfer transistor T is formed by the drain 2, source 3, and gate electrode 5.

In addition, an aluminum wire 8 is connected to a contact 9 at the drain 2.
connected with. In FIG. 1, the aluminum a8 extends horizontally in the drawing and constitutes a bit line. On the other hand, the gate electrode 5 extends vertically in FIG. 1 and constitutes a word line.

Further, the polysilicon layer constituting the capacitor electrode 7 extends over the entire memory cell array block except for the window hole 7a shown in FIGS. 1 and 3.

In addition, in the figure, a polysilicon layer 5.7 and an aluminum a
8. The space between the substrates 10, other than the insulating layer portions 4a and 4b, is also filled with silicon oxide 5in2 (the whole is indicated by 4).

Dynamic memory can also be used as an electrode for external connection.
It has address input electrodes, control signal input electrodes, data readout electrodes, etc. (not shown) arranged around the chip, and lead electrodes of the package are bonded to these.

The operation of each memory cell is as follows. The capacitor electrode 7 is held at a constant potential, and the bit line signal is written as a voltage to the capacitor 0 via the transfer transistor T.
This voltage is maintained even when the switch is turned off. At the time of reading, the charge stored in the capacitor C flows out through the transfer transistor T into the bit 2 trap.In this way, a predetermined voltage is applied to the capacitor C, so that the oxidized $4b It is extremely important to increase the reliability of dielectric strength. However, it is difficult to manufacture chips with good dielectric strength over the entire wafer. Moreover, it is also possible to completely remove, ie, screen out, chips with poor dielectric strength. As can be seen from the fact that the breakdown frequency for an electric field applied for a predetermined time (for example, 1 second) is as shown in Fig. There are some chips that break down in (region B), and these cannot be completely screened in a short test. In other words, dielectric strength tests are performed by increasing the power supply voltage of the circuit, but if it is too high, there is a risk of destroying the circuit elements, so conventionally, the voltage can only be raised to about twice the operating voltage of the circuit. I can't do it,
With such voltages, there is never enough time to apply the voltage, and if the voltage is applied for a normally practicable time, some chips that would break down if the voltage was applied for a longer period of time do not break down, resulting in poor withstand voltage. This is because it is not possible to sift out all the chips.

[Purpose of the invention]

An object of the present invention is to enable complete voltage resistance testing of dynamic memories.

That is, this makes it possible to reliably distinguish between good and bad memory, thereby increasing the reliability, especially long-term reliability, of dynamic memories placed in the field.

[Overview of the invention]

The dynamic memory of the present invention has an external connection electrode connected to a capacitor electrode. This external connection electrode has a structure with which, for example, a needle of a wave blower set can come into contact. In the dynamic memory of the present invention, a voltage can be applied between the external connection electrode and the semiconductor substrate to perform a withstand voltage test of the insulating layer. The applied voltage can be, for example, about four times the operating voltage of the circuit. Such a test is performed, for example, at the end of the wafer stage by bringing the needle of a wafer prober into contact with the external connection electrode.

[Embodiments of the invention]

Figures 6 and 7 show an embodiment of the dynamic memory of the present invention. Figure 6 shows the overall layout, and Figure 7 shows the details of the part surrounded by the broken line ■ in Figure 6. show. The memory chip of this embodiment has four memory cell array blocks Bl.

It has B2, B3, and B4. These memory cell array blocks are provided with bonding pads for various signal systems and input systems, but these are not shown. Also, regarding the peripheral circuits that drive memory cells,
Illustrations are omitted. The structure and operation of each memory cell are
This is the same as described with reference to FIGS. 1 to 4. The memory chip of the present invention has a lead portion 1 on the capacitor electrode 7.
It is characterized in that an external connection electrode 12 connected by 1 is provided. In the illustrated example, the lead portion 11 and the external connection electrode 12 are formed integrally with the υ capacitor electrode 7 from polysilicon, and the external connection electrode 12 is in contact with the needle of the wave propper. It has a possible structure. Oka, the external connection electrode 12 does not need to be bonded, so its position can be arbitrary.
The material is not limited to polysilicon, and may be any conductive material such as metal or metal oxide.

The above memory chip can be manufactured using known manufacturing techniques.

Voltage testing of the insulation layer of such dynamic memories can be carried out, for example, at the end of the wafer stage (before bonding).
The insulation layer is formed by applying a voltage between the external connection electrode 12 and the semiconductor substrate 10.
In addition to the layer 4b located under the gate electrode 5, there is a layer 4a located under the gate electrode 5, but the thinner layer is the layer 4a located under the gate electrode 5.
a, 4b, of which layer 4b occupies the majority. Therefore, if a voltage is applied to the layer 4b and a withstand voltage test is performed, the chip has been subjected to a sufficiently reliable withstand voltage test. For the twisted layer 4a, etc., a conventional pressure resistance test may be conducted separately.

Incidentally, even when there are a plurality of memory cell array blocks as in the illustrated example, the voltage is applied by the common electrode 12 to all the blocks, so that the test is easy.

The voltage is applied to the external connection electrode 12 by, for example, bringing the needle of a wafer prober into contact with the external connection electrode 12. The applied voltage can be, for example, about four times the operating voltage of the circuit. The reason why such a high voltage can be applied will be described below. That is, in the past, the withstand voltage test was performed by increasing the power supply voltage of the circuit, which was limited to a range that would not destroy the circuit elements, that is, about twice the operating voltage. In contrast, in the present invention, voltage can be applied to the insulating layer without applying the power supply voltage of the circuit.

When no power supply voltage is applied, the capacitor electrode 7 is separated from the substrate 1 by the capacitor insulating layer 4b and the junction (of the element of the power supply circuit, not shown). Therefore, a voltage can be applied up to the breakdown voltage in the opposite direction of the pn junction. The breakdown voltage of a pn junction is usually designed to be about four times the operating voltage. Therefore, as described above, it is possible to conduct experiments by applying a voltage up to about four times the operating voltage. For example, in a circuit system with an operating voltage of 5V, up to 20V can be applied, which is 200A.
In the case of the insulating film, an electric field of 10MV7cm is applied. As a result of this application of high voltage and therefore high electric field,
Even if the application time is relatively short, sufficient screening can be performed. The reason for this will be explained below with reference to FIG.

FIG. 8 shows the cumulative failure rate with respect to the voltage application time. As shown in the figure, the cumulative failure rate increases until t x tB, but after that it hardly changes. Therefore,
By applying a voltage up to tB, all chips with poor breakdown voltage can be screened out.

However, this 1. varies depending on the applied voltage.

That is, when the applied voltage is low (about twice the operating voltage), 1B is so long as to be impractical. On the other hand, if the applied voltage is increased, tB can be shortened, and 4
If it is doubled, it will be short enough to be actually implemented. Thus, as mentioned above, the present invention allows for complete screening.

That is, chips with long-term reliability problems can be reliably screened out in a short test.

〔Effect of the invention〕

As described above, according to the misfired 8AK, an external connection electrode connected to a capacitor electrode is provided, and this external connection electrode can be used to easily and quickly perform a withstand voltage test on an insulating layer to detect voltage failures. Chips can be sieved out reliably.

[Brief explanation of drawings]

Figure 1 is a plan view of a known dynamic memory, Figure 2 is a plan view of a known dynamic memory;
The figure is an enlarged cross-sectional view of the line ■-■ in Figure 1, and Figure 3 is an enlarged cross-sectional view of
4 is a circuit diagram showing a part of the Q dynamic memory shown in FIG. 1; FIG. 5 is a diagram showing an example of dielectric breakdown frequency with respect to the applied electric field of the dynamic memory;
FIG. 6 is a plan view showing the layout of a dynamic memory chip according to an embodiment of the present invention, and FIG. 7 is a diagram showing the broken line in FIG.
FIG. 8 is a plan view showing in detail the portion surrounded by . FIG. 8 is a diagram showing the cumulative failure rate with respect to the voltage application time. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Drain, 3... Source, 4, 4&, 4b... Insulating layer, 5... Gate, 7... Capacitor electrode, 8... Aluminum wire, DESCRIPTION OF SYMBOLS 11... Lead part, 12... External connection electrode, Bl, B2, B3, B4... Memory cell array block. Decay 1 Figure 83 Mouth

Claims (1)

[Scope of Claims] fll has a plurality of memory cells, each memory cell has an M08FFtT and a capacitor, and the capacitor has a capacitor electrode facing the semiconductor substrate with an insulating layer interposed therebetween; A dynamic memory having an external connection electrode connected to the capacitor electrode. (2. In the memory described in claim 1,
A memory characterized in that the capacitor electrodes of all memory cells are interconnected. (3) In the memory described in claim 1,
The dynamic memory has a plurality of memory cell array blocks, each memory cell array block has a plurality of memory cells, and the capacitor electrodes of the cells are connected to each other, A memory characterized in that the above-mentioned external connection electrode is provided in common to these.