JPH02105568A - Mos type dynamic semiconductor memory - Google Patents

Abstract

PURPOSE:To ensure the quality and reliability of a device by installing a capacitance counter electrode extraction wire which extracts counter electrodes and removing memory cells having defective capacitance insulating films at the step of applying voltage after the foregoing memory cells are destroyed by applying voltage. CONSTITUTION:Electrodes facing to charge storage regions of memory cell capacitors 16, that is to say, counter electrodes 11 are connected to a 1/2 power voltage wire 17 through a cutoff transistor. Further, the level of the counter electrodes 11 makes up a switching means by connecting it to the gate terminal 15 of the cutoff transistor 12 through an inverter 14 so that the transistor 12 comes to a state of OFF when voltage is applied to an input pad 1. Consequently, linear voltage is applied to the capacitance insulating film of memory cells from the outside and any device deteriorated by defects which are caused by the failure of the capacitance insulating film is removed effectively as initial failure. The quality and reliability of the device are thus improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a MOS type dynamic semiconductor memory device having a memory cell consisting of one transistor and one capacitor.

[Conventional technology]

Conventionally, this type of MOS type dynamic semiconductor memory device has been subjected to an accelerated test (hereinafter referred to as BT) in which it is operated at high power supply voltage and high temperature for a long time to eliminate initial failures caused by defects in the capacitor insulating film and to ensure long-term reliability. I was trying to guarantee that.

[Problem to be solved by the invention]

The recent miniaturization of MOS type dynamic semiconductor memory devices,
With the increasing density of integration, various problems have arisen in the conventional structure described above.

First, in order to compensate for the electric field applied on the capacitor insulating film, a method in which the potential applied to the capacitor counter electrode is approximately 1/2 of the power supply voltage is becoming mainstream. At that time, the power supply voltage and a potential lower than the power supply voltage that is uniquely determined by the circuit type are applied to the capacitive insulating film. Selection through accelerated testing takes a long time. Furthermore, there is a drawback that long-term reliability can no longer be guaranteed because defective products are shipped without sufficient acceleration, causing reliability problems. Furthermore, the MOS transistors that constitute the peripheral circuits of MO3 dynamic semiconductor memory devices have also been miniaturized. A high load is placed on the MOS transistors that make up the device, creating the risk of deterioration of characteristics.
The drawback is that it does not effectively remove defective devices.

An object of the present invention is to provide an MO3 type dynamic semiconductor memory device that can ensure quality and reliability by removing memory cells having defective capacitive insulating films.

[Means to solve the problem]

The MO3 type dynamic semiconductor memory device of the present invention has a capacitance counter electrode facing a charge storage region that is approximately half the power supply voltage.
A 1/2 power supply voltage line to which a voltage is applied, a capacitor counter electrode lead-out line for drawing out the capacitive counter electrode, and a voltage between the 1/2 power supply voltage line and the capacitor counter electrode depending on the level of voltage on the capacitor counter electrode lead-out line. and switching means for making the conductive state conductive or conductive.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

The input pad 1 is connected to the drain 4 and gate 5 of a first MOS transistor (parasitic channel MOS transistor 2) whose source 3 is connected to the V55 line 18, and is connected to the drain 4 and gate 5 of the second MOS transistor 7 via a resistive element 6. 8
After being connected to the electrode opposite to the charge storage region of the capacitor 16 of the memory cell, that is, connected to the capacitor pair 8i11, forming a capacitor counter electrode lead line. Here, the gate 9 and source 10 of the second MOS transistor 7 are connected to the Vs5 line 18. parasitic channel MOS
Transistor 2. Resistance element 6. and the second MOS transistor 7 constitute a normal input protection circuit.

Further, the capacitor counter electrode 11 is connected to the cutoff transistor 12.
It is connected to the 1/2 power supply voltage line 17 via. Furthermore, when a voltage is applied to the input pad 1, this transistor 12 is turned off, so that the level of the capacitance vs.
is connected to the gate terminal 15 of the switch to constitute a switching means. When no voltage is applied to the test input pad 1, the cutoff transistor 12 is turned on and normal operation is possible.

After performing a low-level write operation on all bits with the power supply voltage Vcc = 5V for a wafer-stage MO3 type dynamic semiconductor memory device that has completed diffusion and has input bins having the above-described structure, a constant voltage is applied to the input pad 1. Apply 8■ at the source. Memory cells with defects in the capacitor insulating film are destroyed at this stage. After that, defective chips can be removed by testing according to the normal test flow, improving the sorting yield at the time of shipment.During long-term high power supply voltage and high temperature life tests, defects in the breakdown mode of the capacitor insulating film are eliminated. This can be significantly reduced.

Note that the input pad 1 does not necessarily need to be connected to an external terminal of the package.

〔Effect of the invention〕

As explained above, since the present invention has a lead wire at the opposite electrode of the capacitor of the memory cell, it is possible to apply a voltage directly to the capacitor insulating film of the memory cell from the outside, and effectively This has the effect that devices that deteriorate due to defects can be excluded as initial failures, and that the quality and reliability of the MO3 type dynamic semiconductor memory device can be improved. Furthermore, there is also the effect that the test time required for sorting at the time of shipment is significantly reduced and the yield is improved.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Input bad, 2... Parasitic channel MOS transistor, 3, 4.5... Source, drain, gate of parasitic channel MOS transistor, 6... Resistance element, 7... Second MOS Transistor, 8,9°10・
...Train of the second MOS transistor 7. Gate, source, 11...memory cell capacitance counter electrode, 1
2... Transistor for cutoff, 13... Capacitor counter electrode lead line, 14... Inverter, 15... Gate of cutoff transistor 12, 16... Capacitor of memory cell, 17... 1 /2 power supply voltage line, 18
...Vss line.

Claims (1)

[Claims] Approximate power supply voltage 2 on the capacitor counter electrode facing the charge storage region
a 1/2 power supply voltage line to which a voltage of 1/2 is applied; a capacitor counter electrode lead line for drawing out the capacitor counter electrode; 1. A MOS type dynamic semiconductor memory device, comprising: switching means for making a non-conducting state or a conducting state between the MOS transistors and the semiconductor memory device.