KR100548541B1 - Apparatus and method for testing refresh rate of semiconductor device - Google Patents

Abstract

The present invention relates to a test apparatus and a circuit for measuring refresh characteristics.

In the test apparatus for measuring the refresh characteristic, the present invention provides a plurality of MOS transistors on a semiconductor substrate on which a field oxide film is formed. A plurality of bit line node contact plugs are formed in the contacts formed in the source impurity regions of the plurality of MOS transistors, respectively. Bit lines are connected to the plurality of bit line node contact plugs, and storage node contact plugs are respectively formed in the drain impurity regions. A lower electrode is formed on the bit line by connecting to the plurality of storage node contact plugs. A cell capacitor is formed using a dielectric film formed on the lower electrode and a first upper electrode formed on the dielectric film. A second upper electrode is formed on one substrate of the plurality of MOS transistors. A gate capacitor is formed using the impurity region formed in the second upper electrode as the lower electrode.

In the test method for measuring the refresh characteristic, the capacitance of the cell capacitor between the lower electrode and the first upper electrode and the gate capacitor formed between the lower electrode and the second upper electrode has a value equal to the total capacitance of the memory cell. The refresh characteristics of the semiconductor device are measured by measuring the rate at which the voltage applied to the lower electrode is decreased over time.

Description

Apparatus and method for testing refresh rate of semiconductor device for measuring refresh characteristics of semiconductor devices

1 is a cross-sectional view of a test apparatus for measuring refresh characteristics of a semiconductor device according to an exemplary embodiment of the present invention;

2 is a circuit diagram of a test apparatus for measuring refresh characteristics of a semiconductor device according to an embodiment of the present invention;

3 is a voltage waveform diagram of an input voltage and a storage node lower electrode in a method of testing refresh characteristics of a semiconductor device according to an exemplary embodiment of the present invention.

(Name of the code for the main part of the drawing)

1: P-well 2: field oxide film

3: gate 4: bit line node contact plug

5: bit line 6: storage node contact plug

7: Storage node lower electrode 8: Dielectric film

9: storage node first upper electrode 10: storage node second upper electrode

11: Storage Node Bottom Electrode Monitor Terminal

12: gate oxide film

The present invention relates to a test apparatus and a test method for measuring the refresh characteristics of a DRAM (Dynamic Random Access Memory) cell, and more particularly, to a storage node formed by a semiconductor device. The lower electrode is commonly tied, and a cell capacitor and a gate capacitor are formed to have a value equal to the total capacitance of the memory cell.

The present invention also relates to a test method for measuring a refresh characteristic by measuring a rate at which a voltage applied to a lower electrode of a storage node decreases over time through a gate line using the test apparatus. .

Measuring the refresh time from a DRAM to read or write a data signal from a capacitor for storing the data signal through a transistor and then to a read or write operation to the capacitor is a memory device. It is a criterion for determining the completeness of the manufacturing process and the superiority of the memory device.

In order to measure the refresh characteristics as described above, a method of directly measuring the refresh characteristics and measuring the leakage current of the semiconductor elements are generally performed by reading and writing a data signal to a semiconductor device which is actually manufactured. Indirectly to measure the refresh characteristics.

However, since the method of measuring the refresh characteristics by performing the operation of reading and writing a data signal to a semiconductor device which has been actually manufactured can be performed when the fabrication process of the semiconductor device is completed, the semiconductor is not good when the refresh characteristics are not good. There is a problem that all the manufacturing line of the device must be replaced.

In addition, the method of determining the refresh characteristic by measuring the leakage current of the semiconductor device is only an indirect method of estimating the refresh characteristic by the leakage current over time, and using a modified layout different from the actual memory cell. Because of the measurement, it is difficult to accurately measure the refresh characteristics, and the process of determining the refresh characteristics by analyzing the measured values is complicated, and thus, there is a problem that errors are likely to occur.

The present invention is to solve the above problems, to form a cell capacitance and a gate capacitance having a capacitance equal to the total capacitance formed in the memory cell of the semiconductor device, and applied to the storage node lower electrode through the gate line It is an object of the present invention to provide a test apparatus and a test method capable of obtaining more accurate refresh characteristics by measuring a reduction ratio of the applied voltage, and measuring refresh characteristics before fabrication of a semiconductor device is completed.

In order to achieve the above object, the present invention is connected to the lower electrode of the storage node of the semiconductor device in common, forming a cell capacitor between the storage node lower electrode and the first storage node upper electrode, and the storage node lower electrode and A gate capacitor is formed between the upper electrodes of the second storage node outside the memory cell.

The present invention is characterized in that the refresh characteristics are measured by measuring the ratio of the voltage stored in the lower electrode of the storage node and reduced by the gate voltage using the test apparatus having the above structure.

The cell capacitor and the gate capacitor respectively bind the gate electrode and the bit line of the memory cell transistor to form a cell capacitor formed by a dielectric film and a gate capacitor formed by a gate oxide film. By adjusting, it is set to have the same capacitance as the total capacitance of the memory cell.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 illustrates a test apparatus for measuring refresh characteristics of a semiconductor device according to an exemplary embodiment of the present invention. Referring to FIG. 1, a test apparatus for measuring refresh characteristics of a semiconductor device has a structure as follows.

A field oxide film 2 defining a device region is formed on the semiconductor P-well 1, and includes a gate 3 and a source / drain region on the device region defined by the field oxide film 2. To form a transistor. An interlayer insulating film is formed on the field oxide film 2 and the semiconductor P-well 1 so as to cover the transistor, and the storage node contact plug 6 and the transistor are in contact with the source region of the transistor on the interlayer insulating film. Bit line node contact plugs 4 and bit lines 5 are formed in contact with the drain region. In this case, all of the storage node lower electrodes 8 contacting the storage node contact plugs 6 are connected to the common electrode to be electrically connected to the gate outside the memory cell.

The electrically connected gate forms a gate capacitor by the gate insulating layer 12 between the storage node lower electrode 7 and the second storage node upper electrode 10 while a portion is placed on the active. In addition, the storage node lower electrode 7 forms a cell capacitor by the dielectric film 8 positioned between the first storage node upper electrode 9. At this time, the capacitance value of the formed gate capacitor compensates the value of the capacitance caused by the cell capacitor generated by modifying the shape of the storage node lower electrode 7 to process the value of the total capacitance applied to the storage node lower electrode. Adjust to the same value as you want to design in.

Then, the storage node lower electrode monitor terminal 11 is installed in contact with the gate outside the memory cell so that the voltage applied to the storage node lower electrode 7 can be externally measured through a gate formed outside the memory cell. .

2 shows a circuit diagram of the test apparatus described above. Referring to FIG. 2, the test circuit according to the present invention commonly binds the gate terminals of a plurality of MOS transistors constituting a memory cell to drive the plurality of MOS transistors at the same time, and the storage node lower electrode 7 is common. The gate capacitor is formed between the second storage node upper electrode 10 by connecting to the gate electrode 3 positioned outside the memory cell.

At this time, the source of the plurality of MOS transistors is charged to a high voltage by connecting the bit lines 5 to the common electrode, after charging the source of the MOS transistors or charging the source. The gate voltage is applied to measure the refresh characteristics of the semiconductor device before the process.

FIG. 3 illustrates waveforms of voltages formed on the storage node lower electrodes in the test method of measuring refresh characteristics by applying a gate voltage and a bit line voltage to a test apparatus for measuring refresh characteristics of the present invention. In FIG. 3, the bit line voltage Vbl is applied to the high state before the gate voltage Vgate is applied to the high state. However, the bit line voltage is applied after the gate voltage Vgate is first applied to the high state. (Vbl) may be applied in a high state.

When the gate voltage Vgate is applied in a high state to charge the storage node, and the voltage Vsn of the storage node lower electrode 7 sufficiently rises to the level of the gate voltage Vgate, the gate voltage Vgate becomes low. Transition to In this case, the voltage Vsn of the storage node lower electrode is measured through the storage node lower electrode monitor terminal 11 contacting the storage node lower electrode 7 through a gate.

While measuring the rate at which the voltage Vsn of the storage node lower electrode decreases after the gate voltage Vgate transitions to a low state, the voltage of the storage node upper electrodes 9 and 10 remains constant regardless of the value thereof. It just needs to be maintained. Accordingly, the bit line voltage Vbl may be maintained in a high state or may be compared with the voltage Vsn of the lower electrode of the storage node with its value set to a low state.

As described above, the value measured by detecting the decrease rate of the voltage Vsn of the lower electrode of the storage node is an average value of the total capacitances of the memory cells, and thus, when calculated statistically, the refresh characteristics of each memory cell may also be measured.

As described in detail above, according to the test apparatus and test method for measuring the refresh characteristics of the present invention, the test is performed by forming a pattern having the same capacitance as the semiconductor device actually manufactured in the state in which only the memory cell of the semiconductor device is manufactured By doing so, more accurate refresh characteristics can be measured before the production of the semiconductor element is completed, and the yield according to the semiconductor production process can be improved.

Hereinafter, this invention can be implemented in various changes in the range which does not deviate from the summary.

Claims (5)

In the test apparatus for measuring the refresh characteristics of the semiconductor device, An interlayer insulating film having a plurality of gates provided on a semiconductor substrate on which a field oxide film is formed, a plurality of MOS transistors comprising source / drain impurity regions formed on both sides of each gate, and a plurality of contacts exposing the impurity regions; A plurality of bit line node contact plugs each formed in a contact formed in a source impurity region among the plurality of contacts, a bit line connected to the plurality of bit line node contact plugs and formed on the interlayer insulating film; A plurality of storage node contact plugs respectively formed in the drain impurity region among the contacts, a lower electrode connected to the plurality of storage node contact plugs and formed on the bit line, a dielectric film formed on the lower electrode; An upper electrode formed on the dielectric layer And a cell capacitor; And an upper electrode formed on one substrate of the plurality of MOS transistors, and a gate capacitor using an impurity region formed under the upper electrode as a lower electrode. In the test apparatus for measuring the refresh characteristics of the semiconductor device, A plurality of MOS transistors each having a gate terminal connected to the gate line, a source terminal connected to the bit line, and a drain terminal connected to each other; A cell capacitor having a storage node lower electrode connected to a drain of the plurality of MOS transistors; And a gate capacitor connected to a drain of the plurality of MOS transistors and having a gate capacitor capable of measuring a change in voltage through the storage node bottom electrode monitor terminal. A number of MOS transistors, A bit line connected to a gate of each of the MOS transistors; A cell capacitor having a lower electrode connected to a drain of each of the MOS transistors; A test method using a refresh characteristic test apparatus having a gate capacitor including a monitor terminal connected to a drain of each of the MOS transistors and configured to measure a change in voltage. Applying and maintaining the bit line voltage in a high state; Applying a gate voltage to a high state while the bit line voltage is held high; Transitioning the gate voltage to a low state after the cell capacitor and the lower electrode of the gate capacitor are charged to the high state by the gate voltage of the high state; The refresh characteristic test method of claim 1, wherein the refresh characteristic of the semiconductor device is measured by measuring a rate at which a voltage charged in the cell capacitor and the gate capacitor decreases after the gate voltage transitions to a low state. The method of claim 3, wherein the bit line voltage is A refresh characteristic test method, characterized in that the high voltage is applied after the gate voltage transitions to the high state. The method of claim 3 or 4, wherein the bit line voltage is A method of testing a refresh characteristic characterized in that the voltage of the cell capacitor and the gate capacitor charged in the high state starts to decrease, and then remains in a high state or transitions to a low state.

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