KR20040008396A - A test pattern of semiconductor device - Google Patents

Abstract

PURPOSE: A test pattern of a semiconductor device is provided to be capable of testing all the cell transistors, by using a plurality of test terminals electrically connected with the source/drain region of each cell transistor through a bit line and a contact plug. CONSTITUTION: A test pattern of a semiconductor device is provided with a semiconductor substrate, a plurality of active regions(31) spaced apart from each other at the upper portion of the semiconductor substrate, a plurality of word lines(33) having a common word line(32), source regions formed at the first active regions between word lines, and drain regions formed at the second active regions between source regions. The test pattern further includes a plurality of bit lines(35) having a common bit line(34), contact plugs(37) for a storage node, arrayed parallel with the word lines and test terminals electrically connected with the common word line, the common bit line, and a connection portion of the contact plug.

Description

A test pattern of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test pattern of a semiconductor device. In particular, the present invention relates to a test pattern of a semiconductor device that improves the yield of a device and reduces the cost of device production by testing all cell transistors in an array. It is about.

The cell transistor of the chip is composed of an array, and a bit line is connected to a source region of the cell transistor to input / output data, and a capacitor is connected to a drain region of the cell transistor. Save it.

The cell transistors must be tested because the characteristics of the cell transistors, such as the threshold voltage and the breakdown voltage, influence the chip characteristics.

However, since the test pattern of the semiconductor device according to the prior art tests only one cell transistor, the cell transistors of the chip are configured in an array, so that the threshold voltages of the cell transistors are changed due to the CD (Critical Dimension) difference between word lines. The result of testing only one cell transistor is inconsistent with the result of testing only one cell transistor because the data of the in-line is changed due to such a change. There is a problem that it is difficult to represent the characteristics of a plurality of cell transistors.

The present invention has been made to solve the above problems, and the source region and the drain region of the cell transistor are electrically connected to each other test terminal through a contact line for a bit line and a storage electrode, respectively, and then in the array through the test terminals. The purpose is to provide a test pattern of a semiconductor device for testing all cell transistors.

1 is a layout showing a test pattern of a semiconductor device according to an embodiment of the present invention.

2 is a layout diagram showing an active region and a word line of the present invention.

3 is a layout diagram showing an active region, a word line, a bit line, and a storage electrode of the present invention.

<Description of Symbols for Major Parts of Drawings>

31: active area 32: common word line

33: word line 34: common bit line

35: bit line 36: connection portion

37: contact plug A for storage electrode: source region

B: drain region

The present invention for achieving the above object,

A semiconductor substrate having a plurality of active regions arranged to be spaced apart at a predetermined interval in one direction and arranged to be shifted from a neighboring column;

A plurality of word lines spaced apart from each other in the same direction as the active area on the semiconductor substrate and arranged in a bar shape intersecting the active areas in two places, each having a common word line connected to one side;

A source region of a cell transistor formed in an active region between word lines in each active region and a drain region of a cell transistor formed in an active region between the source regions;

A plurality of bit lines arranged parallel to the word line in a bar shape contacting the source region on the word lines, and having a common bit line connected to one side;

A contact plug for a storage electrode arranged in parallel with the word line in a rod shape contacting the drain region with the drain region on the bit lines, and having a connection part connected to one side;

Providing a test pattern of a semiconductor device including test terminals electrically connected to the common word line, the common bit line, and the connection unit, respectively;

The bit line is formed of a WSi layer or a polysilicon layer having a thickness of 100 ~ 3000Å,

The width of the bit line is equal to or wider than the width of the bit line in the chip,

The storage electrode contact plug may be formed of a polysilicon layer having a thickness of 100 to 5000 Å.

The principle of the present invention is that the source region and the drain region of the cell transistor are electrically connected to the other test terminals through the bit lines and the contact electrodes for the storage electrodes, respectively, and then test all the cell transistors in the array through the test terminals. It is possible to test threshold voltage and breakdown voltage of all cell transistors in the chip, which can detect chip defects and process failures and shorten chip development period, and also know the defect rate of devices at the beginning of the test. This is to shorten the test time of the chip.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a layout diagram illustrating a test pattern of a semiconductor device according to an exemplary embodiment of the present invention.

2 is a layout diagram showing an active region and a word line of the present invention, and FIG. 3 is a layout diagram showing an active region, a word line, a bit line, and a storage electrode of the present invention.

Referring to FIG. 1, a test pattern of a semiconductor device according to an embodiment of the inventive concept is arranged in an I type spaced apart at regular intervals in a horizontal axis direction, and has a semiconductor substrate having a plurality of active regions 31 arranged to alternate with a neighboring column. A plurality of word lines 33 having a common word line 32 connected to each other and arranged in a bar shape spaced apart at regular intervals in the horizontal axis direction (not shown), the two word lines 33 The plurality of bit lines 35 and the four word lines 33 having a common bit line 34 connected to each other while being arranged in a bar shape on the word lines 33 therebetween in a unit. ) And a contact plug 37 for a storage electrode having a connecting portion 36 connected to each other while being arranged in a bar shape on the upper side of the bit lines 35 between the two bit lines 35 as one unit. ) It is sex.

Here, each of the active regions 31 is formed to intersect the two word lines 33, and as shown in FIG. 2, in the active regions 31 between the word lines 33 in each of the active regions 31. The source region A of the cell transistor is formed, and the drain region B of the cell transistor is formed in the active region 31 between the source regions A.

As shown in FIG. 3, the bit line 35 is contacted to the source region A of the cell transistor through the plug P so that all the source regions A formed in the array are the common bit line 34. ) Through a first test terminal (not shown) in contact with In addition, the bit line 35 may be formed of a WSi layer or a polysilicon layer having a thickness of 100 to 3000 mW, and a nitride film or an oxide film having a thickness of 100 to 3000 mW may be formed on the bit line 35. The width of the bit line 35 formed for the test is increased to be equal to or wider than the width of the bit line in the chip.

In addition, the contact plug 37 for the storage electrode contacts the drain region B of the cell transistor so that all the drain regions B formed in the array are in contact with the connection part 33 (not shown). To be tested. The contact plug 37 for storage electrodes is formed of a polysilicon layer having a thickness of 100 to 5000 Å.

In addition, the word lines 33 are also tested through a third test terminal (not shown) in contact with the common word line 32, so that all the cell transistors formed in the array include the word line 33 and the source region ( A) and the drain region B are connected to different test terminals, respectively, to perform a test.

In this case, the bit line 35 is arranged in the horizontal axis direction, which is the same direction as the word line 33, for the reason that the bit line 35 is in contact with the storage electrode contact plug 37 and the drain region B of the cell transistor. The purpose is to increase process margins.

The storage electrode contact plug 37 is configured to be parallel to the bit line 35, and the reason is that when the storage electrode contact plug 37 is perpendicular to the bit line 35, To prevent a phenomenon in which a bridge between the bit line 35 and the storage electrode contact plug 37 is generated by applying an attack to the bit line 35 when the storage electrode contact plug 37 is formed. It is for.

In the test pattern of the semiconductor device of the present invention, the source region and the drain region of the cell transistor are electrically connected to each other test terminal through a contact line for a bit line and a storage electrode, respectively, and then all cell transistors in the array are connected through the test terminals. By testing, the threshold voltage, breakdown voltage, etc. of all cell transistors can be tested in the array, which detects chip defects and process failures, shortening the chip development period, and also knowing the defect rate of the device early in the test. Shortening the test time of the chip improves the yield of the device and reduces the cost of device production.

Claims (4)

A semiconductor substrate having a plurality of active regions arranged to be spaced apart at a predetermined interval in one direction and arranged to be shifted from a neighboring column; A plurality of word lines spaced apart from each other in the same direction as the active area on the semiconductor substrate and arranged in a bar shape intersecting the active areas in two places, each having a common word line connected to one side; A source region of a cell transistor formed in an active region between word lines in each active region and a drain region of a cell transistor formed in an active region between the source regions; A plurality of bit lines arranged parallel to the word line in a bar shape contacting the source region on the word lines, and having a common bit line connected to one side; A contact plug for a storage electrode arranged in parallel with the word line in a rod shape contacting the drain region with the drain region on the bit lines, and having a connection part connected to one side; And a test terminal electrically connected to the common word line, the common bit line, and the connection unit, respectively. The method of claim 1, The bit line is a test pattern of a semiconductor device, characterized in that formed of a WSi layer or a polysilicon layer of 100 ~ 3000Å thickness. The method of claim 1, The width of the bit line is the same or wider than the width of the bit line in the chip test pattern of the semiconductor device. The method of claim 1, The contact plug for the storage electrode is a test pattern of a semiconductor device, characterized in that formed of a polysilicon layer of 100 ~ 5000Å thickness.