KR20020094984A - Method for testing reliability of dielectric - Google Patents

Abstract

PURPOSE: A method for testing the reliability of dielectric is provided to shorten a testing time and to reduce testing costs by measuring an FBC(Fail Bit Count) after applying a stress to the dielectric. CONSTITUTION: A wafer including a plurality of cells formed in a storage node electrode(26), a dielectric film(28) and a plate electrode(30) is prepared. A first FBC of each cell is measured without applying a stress to the dielectric film(28). A stress is applied to the dielectric film(28) for a desired time. Then, a second FBC of each cell is measured. Thereby, it is determined whether the dielectric film(28) is degraded by comparing the first FBC to the second FBC.

Description

Method for testing reliability of dielectric

The present invention relates to a test method for a semiconductor device, and more particularly, to a test method for reliability of a capacitor dielectric.

As the design rule of the semiconductor device decreases, a capacitor dielectric film of dynamic random access memory (DRAM) also needs to secure sufficient capacitance. The capacitance and characteristics of these dielectric films are estimated by dielectric reliability tests.

Here, the process for measuring the dielectric reliability can be largely measured at the wafer level (wafer level) and the method at the package level (package level).

Here, the method of measuring at the wafer level is a constant current stress (CCS) method of applying a predetermined current to the dielectric to give a stress, and a constant voltage stress (CVS) of applying a predetermined voltage to the dielectric to give a stress. In addition, there is a time dependent dielectric breakdown (TDDB) method in which the reliability of the dielectric material is determined by applying a predetermined stress to the dielectric material according to the time when the breakdown occurs.

On the other hand, a method of measuring at the package level is typically a burn-in test, and the test at the package level exposes a potential defect in a short time by operating the DRAM under high temperature and high pressure conditions.

However, the conventional dielectric reliability test method has the following problems.

The test method at the wafer level described above measures reliability by applying a current or voltage of about 10 times or more, which is substantially higher than the current or voltage (hereinafter, a stress source) applied when the device is operated. Therefore, reliability is difficult to predict in the real device operating area.

On the other hand, a test method at the package level requires a device to be packaged and then its characteristics must be analyzed for a long time (days or months), which consumes a lot of time and money. Moreover, the test method at the package level results in the packaging of undesired dies in which deterioration has been detected due to the detection of failures in the packaged state. Thus, material and process costs are increased.

Accordingly, a technical object of the present invention is to provide a dielectric reliability test method that is capable of measuring dielectric reliability at the wafer level and substantially applicable in the device operating region.

1 is a circuit diagram of a DRAM device for explaining a dielectric reliability test method according to the present invention.

2 is a cross-sectional view of a DRAM device for describing a dielectric reliability test method according to the present invention.

(Explanation of symbols for the main parts of the drawing)

26: storage node electrode 28: dielectric film

30: plate electrode

Other objects and novel features thereof, together with the objects of the present invention, will be apparent from the description and the accompanying drawings.

Among the inventions disclosed herein, an outline of representative features is briefly described as follows.

In a wafer state including a plurality of cells in which a storage node electrode, a dielectric film, and a plate electrode are formed, there is no electrical influence on the dielectric, and then the number of fail bits in each cell is measured. Thereafter, stress is applied to the dielectric film for a predetermined time, and then the number of fail bits in each cell is measured again. Thereafter, the number of fail bits before applying stress to the dielectric film and the number of fail bits after applying stress to the dielectric film are compared to determine whether the dielectric deteriorates.

Here, before the step of measuring the number of fail bits of the cell, " 0 " data is written to the storage node electrode. In addition, data is continuously written so that the storage node electrode can maintain " 0 " data while stressing the dielectric.

In addition, the step of applying stress to the dielectric film, at a temperature of 80 to 90 ℃, to apply a predetermined voltage to the plate electrode, the voltage applied to the plate electrode is about 3 to 5 times the operating voltage of the device desirable.

In addition, according to another embodiment of the present invention, in the state of the wafer including each cell in which the storage node electrode, the dielectric film and the plate electrode are formed, and the process up to forming the package is completed, " 0 " Write the data. Next, the number of fail bits in each cell is measured. Thereafter, a predetermined voltage is applied to the plate electrode at a predetermined temperature so that the dielectric film is stressed, and then the number of fail bits in each cell is measured again. Next, the number of fail bits before applying voltage to the plate electrode and the number of fail bits after applying stress to the dielectric film are compared to determine whether the dielectric deteriorates.

At the wafer level, the FBC of the cell is measured and then the FBC is measured after stress is applied to the dielectric. At this time, if a difference in the value of the FBC occurs, it is determined that the dielectric is deteriorated, and the die having the deteriorated dielectric is not packaged.

This eliminates the need to package a degraded die, thus reducing unnecessary costs.

Moreover, by applying the stress applying voltage not so much higher than the device operating voltage, it is possible to easily predict the reliability in the device state.

In addition, since the reliability test process is performed at the wafer level, the operator can freely adjust the applied voltage for stressing, and the time for testing the reliability is greatly reduced.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. Here, the embodiments of the present invention can be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Accordingly, the shape and the like of the elements in the drawings are exaggerated to emphasize a more clear description, and the elements denoted by the same reference numerals in the drawings means the same elements. In addition, where a layer is described as being "on" another layer or semiconductor substrate, a layer may exist in direct contact with the other layer or semiconductor substrate, or a third layer therebetween. Can be done.

1 is a circuit diagram of a DRAM device for explaining the dielectric reliability test method according to the present invention, Figure 2 is a cross-sectional view of the DRAM device for explaining the dielectric reliability test method according to the present invention.

First, referring to FIG. 1, one cell of a general DRAM device includes one transistor 100 and one capacitor 110. This transistor 100, as is known, has three terminals: a gate 14, a source 16a, and a drain 16b. Here, the gate 14 is connected to the word line (W / L) to selectively turn on / off the transistor, the source (16a) is connected to the capacitor 110, the drain (16b) is the data It is connected to the bit line (B / L) for transmitting.

This DRAM device is implemented as shown in FIG. 2 on a semiconductor substrate.

That is, the gate electrode 14 is formed at a predetermined interval on the semiconductor substrate 10 where the active region is limited by forming the device isolation region 12. Here, the gate electrode 14 of the present embodiment will be interpreted as a structure including a gate insulating film, a conductive layer on top thereof, a hard mask film, and spacers formed on the sidewalls of the conductive layer and the hard mask film. Sources and drains 16a and 16b are formed in the active region between the gate electrodes. The contact pads 18 are formed in the space between the gate electrodes 14 in the upper portion of the active region so as to be in contact with the source and drains 16a and 16b, respectively. The bit line 22 is formed on the pad 18 in contact with the drain 16b, and the storage node electrode 26 is formed on the pad 18 in contact with the source 16a. Here, the storage node electrode 26 is composed of a storage node pad 26a and a cylinder 26b. The dielectric film 28 is covered on the surface of the cylinder 26b of the storage node electrode 26, and the plate electrode 30 is covered on the surface of the dielectric film 28, thereby forming a capacitor 110. At this time, a tantalum oxide film, an aluminum oxide film, or a laminated film thereof may be used as the dielectric film 28. Here, reference numerals 17, 20, and 24 denote the interlayer insulating film. Thereafter, although not shown in the drawing, the metal wiring process and the passivation film are sequentially formed, and the process until the package is formed is performed. The dielectric reliability is then measured before performing the package process.

In the present invention, a method for measuring dielectric reliability of a DRAM device is as follows.

First, the DRAM device is driven such that data "0" is written into the storage node electrode 26 of the wafer formed up to the passivation layer, that is, until the package is executed. For example, after turning on the transistor 100, a "0" signal is applied to the bit line. Then, data "0" is stored in the storage node electrode 26. Here, the storage node electrode 26 has "0" data to measure whether or not to fail in the absence of any electrical influence on the dielectric. That is, since it becomes a reference for measuring dielectric reliability, the storage node electrode 26 holds the data in the zero state.

Then, the FBC (fail bit count) of each cell is measured. In this case, the FBC measures the number of bits in which a fail has occurred in a cell, and is usually monitored in test equipment.

Next, stress is applied to the dielectric film 28 for a predetermined time, for example, about 1 hour. At this time, the stress in this embodiment is applied by applying a predetermined voltage to the plate electrode 30 of the capacitor at about 80 to 90 ° C. Here, the voltage applied to the plate electrode 30 is preferably applied to a degree slightly larger than the operating voltage range of the actual device (about 3 to 5 times), for example, about 3 to 5V. At this time, the process voltage is shortened as the voltage applied to the plate electrode 30 increases. However, if the applied voltage is too large, it is impossible to predict the dielectric reliability during device operation, and therefore, it is preferable to apply in a range that is slightly larger than the operating voltage, for example, in the range of 3 to 5 times the operating voltage. Here, the DRAM device repeatedly writes and reads the data so that the storage node electrode 26 maintains a "0" state during a stressed time.

Thereafter, stress is applied to the dielectric film 28 for a predetermined time, and then the FBC of the cell is measured again.

At this time, if the FBC before applying the stress to the dielectric film 28 and the FBC after applying the stress are the same, it is determined that the reliability of the dielectric film 28 is excellent, and the subsequent package process is performed. However, if there is a difference between the FBC before applying the stress and the FBC after applying the stress, it is determined that the dielectric film 28 is deteriorated, and the corresponding cell is discarded.

As described above, in the present invention, since the reliability of the dielectric 28 is determined before the packaging process, the packaging process is not performed on cells that are unnecessary, that is, the dielectric is degraded. Therefore, the package process for the degraded die is excluded, thereby reducing the cost.

In addition, although the reliability test process at the package level has been carried out over several days, the reliability test process of the present invention can be performed within a few hours, thereby reducing the process time.

In general, when applying a voltage at the package level, a stress was applied by applying a Vcc voltage. However, in this embodiment, since it proceeds at the wafer level, the voltage for stressing can be easily adjusted.

As described in detail above, according to the present invention, the FBC of the cell is measured at the wafer level, and then the FBC is measured after stress is applied to the dielectric. At this time, if a difference in the value of the FBC occurs, it is determined that the dielectric is degraded, and dies having the degraded dielectric are not packaged.

This eliminates the need to package a degraded die, thus reducing unnecessary costs.

Moreover, by applying the stress applying voltage not so much higher than the device operating voltage, it is possible to easily predict the reliability in the device state.

In addition, since the reliability test process is performed at the wafer level, the operator can freely adjust the applied voltage for stressing, and the time for testing the reliability is greatly reduced.

In addition, various changes can be made in the range which does not deviate from the summary of this invention.

Claims (9)

Providing a wafer comprising a plurality of cells having a storage node electrode, a dielectric film, and a plate electrode formed thereon; Measuring the number of fail bits in each cell, with no electrical influence on the dielectric; Applying stress to the dielectric film for a predetermined time; Measuring the number of fail bits of each cell; And And comparing the number of fail bits before applying stress to the dielectric film with the number of fail bits after applying stress to the dielectric film to determine whether the dielectric deteriorates. The method of claim 1, wherein before measuring the number of fail bits of the cell, And writing "0" data to the storage node electrode. 3. The method of claim 2 wherein the data is written continuously so that the storage node electrode can maintain " 0 " data while stressing the dielectric. 3. The method of claim 1, wherein the applying of stress to the dielectric film comprises applying a predetermined voltage to the plate electrode at a temperature of 80 to 90 ° C. 4. The method of claim 4, wherein the voltage applied to the plate electrode is about three to five times the operating voltage. Providing a wafer including each cell having a storage node electrode, a dielectric film, and a plate electrode formed thereon, the process being completed before forming a package; Writing "0" data to the storage node electrode; Measuring the number of fail bits of each cell; Applying a predetermined voltage to the plate electrode at a predetermined temperature such that stress is applied to the dielectric film; And Measuring the number of fail bits of each cell; And comparing the number of fail bits before applying a voltage to the plate electrode and the number of fail bits after applying stress to the dielectric film to determine whether the dielectric deteriorates. 7. The method of claim 6, wherein the data is written continuously so that the storage node electrode can retain " 0 " data while applying a predetermined voltage to the plate electrode. The method of claim 6 or 7, wherein the plate electrode is applied with a voltage about 3 to 5 times the operating voltage. 9. The method of claim 8, wherein the temperature is maintained at a temperature of about 80 to 90 ℃ when applying a voltage to the plate electrode.