KR100390939B1 - Test pattern for semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test pattern of a semiconductor memory device, wherein the bit lines and word lines of a memory cell arranged in a matrix form are formed independently, and then adjacent bit lines and word lines are connected to one transistor, And the transistors connected with word lines are connected to other adjacent bit lines and transistors connected with word lines so that all transistors are finally connected by one transistor, so that defects can be more correctly and accurately identified and applied again to the process. The test pattern of the semiconductor device which can improve the productivity of is presented.

Description

Test pattern for semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test pattern of a semiconductor device, and more particularly, to independently form bit lines and word lines of a memory cell array arranged in a matrix form, and then connect adjacent bit lines and word lines into one transistor, The transistor connected to the word line relates to a test pattern of a semiconductor device capable of quickly and accurately determining a defect by connecting an adjacent transistor to another transistor.

At present, semiconductor memory devices have been increased in capacity and high density, and according to this trend, high difficulty technologies have been introduced. Self-aligned contact is the most problematic problem in the manufacturing process of 64M flash memory devices using 0.18㎛ technology. Contact) process. The fundamental purpose of this self-aligned contact process is to replace the gate spacer from the oxide film to the nitride film, and to use the nitride film for the contact etching process. That is, since the interlayer insulating film made of the high temperature thermal oxide film and the BPSG film is an oxide film-based, the gap between the gate and the contact is reduced by using an etching selectivity with the nitride film.

Currently, semiconductor memory devices using a self-aligned contact process usually have a gap between the gate and the contact as zero. This reduces the cell size by about 0.2 μm and reduces the overall chip size by about 20%, compared to a conventional 0.2 μm gap between the gate and the contact. However, despite these advantages, the introduction of the process is not easy because of the difficulty of the process. The biggest problem in the self-array contact process is to etch the oxide film using the nitride film, which is a gate spacer, as an etch stop layer. Becomes bad.

This problem has no problem in checking lot variation or wafer variation in a conventional test pattern in which the memory cells illustrated in FIG. 1 are arranged in a matrix form and selected as word lines and bit lines. However, when any defect tendency occurred, it was neglected to physically analyze and identify it in some form. Therefore, when a defect caused by a contact occurs, it takes a long time to analyze it and reapply it to the process.

An object of the present invention is to provide a test pattern of a semiconductor device that can improve productivity by reapplying to a subsequent process by early detection and analysis of defects due to contacts in the manufacturing process of a semiconductor device applying a self-aligned contact.

The test pattern of the semiconductor device according to the present invention for achieving the above object is connected to the adjacent bit line and word line of a memory cell arranged in a matrix form a transistor, the transistor connected the bit line and word line The transistors are connected to other adjacent bit lines and word lines so that all transistors are finally connected by one transistor.

1 is a schematic diagram of a test pattern of a conventional semiconductor device.

2 is a schematic view of a test pattern of a semiconductor device according to the present invention.

3 is a schematic diagram illustrating an array configuration of switch transistors of a word line in a test pattern having 40 pads.

The flash memory cell array selects the word line and the address of the bit line to access the cell in bits. At this time, if the gate and drain contacts are shorted (bridged), the cell access itself becomes impossible, and functions such as a program and an erase are also defective. However, such defects are not easy to analyze because they occur in combination with other defects. In addition, in the nitride film spacer self-aligned contact adopted in highly integrated devices such as 0.18 mu m 64M flash memory devices, the successful application of this process is not an exaggeration to say that the process is life or death.

In the present invention, it is to quickly and accurately determine and analyze the presence and failure of the contact and the gate to reapply to the process quickly based on this.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2 is a schematic diagram of a test pattern of a semiconductor device according to the present invention. Referring to FIG. 2, bit lines and word lines of a memory cell arranged in a matrix form are independently formed, and adjacent bit lines and word lines are connected to one transistor. Then, adjacent transistors are connected to other transistors. Repeat this over and over. That is, bit line 1 BL1 and bit line 2 BL2 are connected to the first NMOS transistor N11, and bit line 3 BL3 and bit line 4 BL4 are connected to the second NMOS transistor N12. Let's do it. The adjacent bit lines are connected using one transistor. The first NMOS transistor N11 and the second NMOS transistor N12 are connected to the third NMOS transistor N13. In this way, adjacent transistors are connected. In the same manner as the bit line, the word line is connected to the adjacent word line WL by using a transistor, and the neighboring transistor is connected by using another transistor. Although an NMOS transistor is used here, it may be implemented as a PMOS transistor according to the characteristics of the device or the applied voltage.

In the above description, an example in which two adjacent bit lines or word lines are connected to one transistor has been described, but two or more bit lines or word lines may be connected to one transistor.

As described above, when the word line and the bit line are independently implemented by accessing the test pattern and accessing and applying the test line, the result of the specific success or failure of the cell is displayed. In addition, to make it similar to the main cell array, the number of accessible cells must be increased. In the present invention, the number of cells can be increased without special decoding as a switch transistor. In this way, more cells can be accessed to determine the presence or absence of defects between contacts and gates, thereby identifying the tendency of defects in the main cell array, which can be reapplied to the process more quickly.

As shown in FIG. 2, when the flash memory cell array is configured, the number of cells that can be monitored is 40 when the number of pads is present.

Word line: 2 ⁸ = 256 pieces-> 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 = 16 pads

Bitline: 2 ⁸ = 256 pieces-> 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 = 16 pads

And if you connect the source and well nodes of the four pads,

A total of 256 x 256 = 64k (bit) cells can be accessed independently, and through this, defect analysis can be done more easily and accurately through BV test between the contact and gate of each cell.

Figure 3 shows the array configuration of the switch transistors on the word line side in the test pattern with 40 pads as shown above. The configuration of the bit line switch transistor may also be configured as shown in FIG. 3.

Although the test pattern mentioned only the defect between the contact and the gate, which are most defective in the manufacturing process of the semiconductor device, the similar interlayer insulating film evaluation between the first metal wiring and the second metal wiring or the first metal wiring and the first The present invention can also be applied to the evaluation of the interlayer insulating film between the third metal wiring and the second metal wiring and the third metal wiring. The method of applying this may be, for example, to evaluate the interlayer insulating film between the first metal wiring and the second metal wiring, so that the first metal wiring can be accessed independently and the second metal wiring can be accessed independently. This can also be increased by placing switch transistors.

As described above, the contact monitoring method using the test pattern according to the present invention can monitor cells of 64k bits, thereby quickly and accurately analyzing defects.

Claims (2)

In the test pattern of the semiconductor device, After the bit lines and word lines of the memory cells arranged in a matrix form are independently formed, the adjacent bit lines and the adjacent word lines are connected to one transistor, and the transistors connecting the adjacent bit lines and the adjacent word lines are the other adjacent bits. A test pattern of a semiconductor memory device, characterized in that all transistors are finally connected by one transistor by using a transistor connected to a line and an adjacent word line and another transistor. The test pattern of claim 1, wherein the number of adjacent bit lines and adjacent word lines connected by the one transistor is two or more in number.