JPH06309899A - Semiconductor memory and testing method - Google Patents

Abstract

PURPOSE:To reduce the pretesting time of each memory cell by providing a precharging means, potential state control means, and Y-decoders for a plurality of bit lines and, especially, means which hold the potential states of the bit lines to each bit line. CONSTITUTION:When a precharge (Pc) signal 300 turns on the transistor (Tr) 4a of a Pc circuit 4, precharging is performed by storing charges in bit lines 101-104 from a power source 4a. The signal 300 then turns off the Tr 4a of the circuit 4 and data are settled by setting the bit lines to 'L' or 'H' levels by or without discharging the charges by means of a memory cell array 1 on a word line selected from among word lines 211-214. After a charge holding circuit 5 maintains the 'H' level by replenishing the bit lines 101-104 with charges by means of an inverter 5c and Tr 5b, a Y-decoder 3 successively selects the word lines 211-214. Then, word decoders 3 respectively installed to the word lines 211-214 test output data 100 by successively selecting the bit lines 101-104. Therefore, the pretesting time of all memory cells can be shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit, and more particularly to a semiconductor memory built in a microcomputer or a microcontroller.

[0002]

2. Description of the Related Art An integrated circuit of a microcomputer or a microcontroller may require a low speed operation in addition to a normal high speed operation. For example, in a magnetic recording / reproducing apparatus currently on the market, even if the outlet is unplugged or a power failure occurs, the stored contents such as the recording reservation will not be erased. This is because the auxiliary power supply operates and holds the stored contents. In order to keep the voltage of the auxiliary power source as long as possible, it is necessary to reduce the power consumption, and therefore the microcomputer and the like are operated in the low speed mode.

In a semiconductor memory built in an integrated circuit such as a microcomputer, it is tested in advance whether or not each memory cell has a defect that causes a leak current or the like. For a microcomputer that can operate at a low speed like this, even if it is tested at a high speed, it is not possible to accurately detect defects that occur during low speed operation, so in the case of testing as well, low speed operation (precharge or discharge at low speed) And have to.

When testing a conventional semiconductor memory, the test is performed for each address, that is, for each memory cell. A conventional semiconductor memory and its testing method will be described below with reference to the drawings.

FIG. 2 shows a circuit configuration of a conventional semiconductor memory. This circuit includes a memory cell array 1, a Y decoder 2,
Output decoder 3, precharge circuit 4, potential holding circuit 5
It consists of zero. The precharge signal 300 is input to the precharge circuit 4, and the bit lines 101 to 104 are input.
The electric charge is accumulated in and the potential becomes the power supply level. The upper addresses 203 and 204 are input to the Y decoder 2 and the row addresses 211 to 214 are output. Bit line 101-
104 is connected to the memory cell array 1, the output decoder 3, and the precharge circuit 4. The lower addresses 201 and 202 are input to the output decoder 3, and the data 100 is output. A charge holding circuit 50 is connected to the data 100.

The operation of the semiconductor memory having the above-described structure when performing a test will be described.

One cycle of the operation of this circuit consists of a precharge operation and an operation of fixing data. The precharge operation is performed from the precharge circuit 4 to the bit lines 101 to 10
4 is an operation for accumulating electric charges, and a data fixing operation is an operation for fixing 0 or 1 of data by discharging or not discharging the charges accumulated in the bit line through the N-channel transistor.

In the precharge operation, the precharge signal 300 turns on the P-channel transistor of the precharge circuit 4 to accumulate charges in the bit lines 101 to 104. Addresses 201-20 within the above operation
4 is fixed. The Y decoder 2 has addresses 203, 20
4, one of the word lines 211 to 214 is selectively set to the high level. Further, the output decoder 3 selectively connects any of the bit lines 101 to 104 to the data 100 by the addresses 201 and 202.

On the other hand, in the operation of determining the data, the precharge signal 300 first turns off the P channel transistor of the precharge circuit 4 and is accumulated in the bit line by the N channel transistor driven by the selected row address. The charge is discharged or not discharged, and the bit line is set to low level or high level. Then, the output of the selected bit line is the data 10
It is obtained as an output of 0. In this case, the low-level state is created by discharging the electric charge through the N-channel transistor, and the high-level state is created by operating the potential holding circuit 50 to replenish the electric charge to precharge the precharged potential. Hold.

Conventionally, one of the precharge operation and the data confirmation operation described above is performed every time an output from one memory cell is obtained, that is, every time one memory cell is tested.
By repeating the cycle, these tests were finally completed for all the memory cells.

[0011]

However, in such a conventional configuration, in the preliminary test of the semiconductor memory, one precharge and one data confirmation are performed each time one memory cell (one address) is tested. In order to test all the memory cells (all addresses) that make up the semiconductor memory, it is necessary to perform the precharge operation and the data confirmation operation the same number of times as the number of memory cells. Especially when the integrated circuit is used at low speed,
Since the test operation is performed at a low speed to guarantee the operation, the time required for one precharge and data confirmation becomes long, and there is a problem that the entire test takes a very long time.

Specifically, one test cycle (one precharge and data confirmation) requires only about 0.5 × 10 ⁻⁶ seconds for high speed operation, but one test cycle for low speed operation. The cycle takes about 125 × 10 ⁻⁶ seconds. That is, in the case of low speed operation, if precharging and data confirmation are repeated a plurality of times, a remarkably long time is required.

SUMMARY OF THE INVENTION The present invention solves the conventional problems, and an object of the present invention is to provide a semiconductor memory and a test method thereof, which can reduce the number of precharge and data confirmation operations in the test stage and shorten the test time.

[0014]

A semiconductor memory of the present invention comprises a precharge means for bringing a plurality of bit lines into a high potential state, a plurality of transistors and a Y decoder for controlling the potential states of these bit lines, and a plurality of 1 from the bit line
An output decoder for selecting a book and a potential holding unit for holding the potential state of each bit line are provided in each of the plurality of bit lines.

Further, according to the semiconductor memory testing method of the present invention, a plurality of bit lines are precharged in a semiconductor memory in which a potential holding means is provided for each of the plurality of bit lines.
After holding or discharging the potential states of these bit lines to determine the data, one word line is selected, and a plurality of bit lines on the selected word line are sequentially selected one by one. Definite data is output in order and tested. Then, the above operation is set as one test cycle, and all memory cells are tested by repeating this test cycle for all word lines.

[0016]

With these configurations, when a semiconductor memory is tested, a plurality of memory cells can be tested by one precharge and data confirmation, and the entire semiconductor memory can be tested with a smaller number of precharges.

[0017]

Embodiments of the semiconductor memory and the test method therefor according to the present invention will be described below with reference to the drawings.

FIG. 1 shows a circuit configuration of a semiconductor memory of the present invention. In the figure, reference numeral 1 denotes a memory cell array in which a plurality of N-channel MOS transistors (memory cells) are arranged in a matrix. Reference numeral 2 denotes a Y decoder for controlling the word line of each memory cell. The Y decoder 2 receives the upper addresses 203 and 204 and outputs the row addresses 211 to 214. Reference numeral 3 is an output decoder for controlling each bit line of the memory cell, which inputs the lower addresses 201 and 202 and outputs the data 100. Reference numeral 4 is a precharge circuit that brings each bit line into a high potential state by supplying electric power, and is provided for each bit line. The precharge circuit 4 inputs the precharge signal 300 to the gate electrode of the P-channel MOS transistor 4a and outputs the bit lines 101 to 104.
Electric charge is accumulated in the memory cell and the potential of each bit line is set to the level of the power supply 4b. Reference numeral 5 is a potential holding circuit composed of a power supply 5a, a P-channel MOS transistor 5b and an inverter 5c, which keeps the potential state by continuously supplying power so that the potential of each precharged bit line does not drop. . Conventionally, only one potential holding circuit is provided at the output terminal as shown in FIG. 2, but in the present invention, it is provided for each bit line. In addition, the bit lines 101 to 104
Are connected to the memory cell array 1, the output decoder 3, the precharge circuit 4, and the potential holding circuit 5.

The operation of testing the semiconductor memory configured as described above will be described.

One cycle of the operation of this circuit consists of a precharge operation and a data fixing operation. That is, the precharge operation is performed by accumulating charges in the bit line, and the data is determined by discharging (discharging) the charges accumulated in the bit line or by fixing the data to 0 or 1 without discharging. Done by.

In the precharge operation, the precharge signal 300 turns on the P-channel MOS transistor 4a of the precharge circuit 4, whereby charges are accumulated in the bit lines 101 to 104 from the power supply 4b.

Next, in the operation of determining the data, the precharge signal 300 first turns off the P-channel transistor of the precharge circuit 4. The N-channel transistor driven on the selected word line of 211 to 214 discharges or does not discharge the charge accumulated on the bit line, and sets the bit line to the low level or the high level. For example, word line 2
When 11 is selected, since the N-channel transistor (memory cell) 1a is connected to the bit line 102, the bit line 102 is discharged to the low level, and in the case of the N-channel transistor 1b, connected to the bit line 103. Since it has not been discharged, the bit line 103 is maintained in a high level state without being discharged. In this high level state, the charge holding circuit 5 operates. That is, when a high-level signal is input to the inverter 5c of the potential holding circuit 5, a low-level signal is input to the gate electrode of the P-channel transistor 5b and the P-channel transistor 5b is turned on to turn on the power supply 5a.
The charge is replenished to the bit line from. Therefore, the bit line can hold the high-level potential.

On the other hand, the addresses 201 to 204 are determined during the above precharge operation. The Y decoder 2 selectively sets any one of the row addresses (word lines) 211 to 214 to a high level by a combination of high and low of the addresses 203 and 204. Further, the output decoder 3 is
Depending on the combination of high and low of the addresses 201 and 202, one of the bit lines 101 to 104 is used as the data 100.
Selectively connect to. Then, the fixed data for the selected bit line is obtained as the output of the data 100.

In this way, the data is output for one memory cell, and the presence or absence of a defect is judged depending on whether the output is normal or not to perform a memory test.

In order to test the next memory cell, the addresses 201 and 202 of the output decoder 3 are set to the high level.
The row combination is changed and the definite data of the next bit line on the same word line is output. In this way, the combination of the addresses 201 and 202 of the output decoder 3 is sequentially changed,
Data output is repeated to test all memory cells on the same word line. In the present invention, first 1
All the memory cells on the same word line can be tested only by switching the output decoder after precharging and confirmation of data only once. In this way, one test cycle is completed.

Then, in the next cycle, the same test is performed on the memory cells on the second word line, and the test cycle is sequentially repeated to complete the test for all the memory cells. That is, according to the present invention, a plurality of memory cells on the same word line can be tested for each operation of precharging and data confirmation.

More specifically, referring to FIG. 1, for example, after the first precharge and data confirmation, the word line 211 is selected by the Y decoder and the output decoder 3 is selected.
The bit lines 101 to 104 are sequentially selected to output data for testing. Next, a second precharge and data confirmation operation are performed, and the word line 2 is read by the Y decoder.
12 is selected, and the bit line 101 is selected by the output decoder 3.
To 104 are sequentially selected and output to test the data. This operation is repeated to test all memory cells.

As described above, according to the present embodiment, since the data is determined for each bit line by providing the potential holding circuit for each bit line, a large number of data can be determined by a small number of precharges and data determination. Since the memory cell can be tested, the semiconductor memory can be tested in a shorter time. Note that in the present invention, the number of operations such as precharging and the like is reduced as compared with the conventional example, but the operation of switching the output decoder for selecting the bit line is additionally increased. Since the time required to switch lines is much shorter than the time required for precharge operation and the time required for data confirmation, there is almost no effect on the entire test time.

Although the potential holding circuit is provided in the circuit which constitutes the semiconductor memory in the above embodiment, the present invention is not limited to this, and the potential holding means may be provided for each bit line in some way. It suffices to provide them. For example, in the conventional circuit configuration, an external terminal may be provided for each bit line and a potential holding circuit may be connected and used.

Further, the present invention can be widely applied to semiconductor memories in general, and the OR type RO shown in the above embodiment.
In addition to M, it can be applied to, for example, AND type ROM and RAM.

[0031]

According to the present invention, the potential holding circuit is provided for each of the bit lines selected by the output decoder, so that a plurality of bit lines on a plurality of bit lines can be placed between one precharge operation and data fixing operation. Data can be obtained, and a semiconductor memory can be tested in a short time.

Particularly in an integrated circuit which requires a guarantee at a low speed,
By performing one cycle of precharge / data confirmation at a low speed during the test and switching the output decoder at a high speed, the inspection time can be shortened while guaranteeing the operation at a low speed.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a semiconductor memory according to an embodiment of the present invention.

FIG. 2 is a circuit configuration diagram of a conventional semiconductor memory.

[Explanation of symbols]

 1 Memory Cell Array 2 Y Decoder 3 Output Decoder 4 Precharge Circuit 5 Potential Holding Circuit 100 Output Data 101 to 104 Bit Lines 201 to 204 Address 211 to 214 Word Line 300 Precharge Signal

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display location H01L 21/66 W 7630-4M 27/108

Claims (2)

[Claims] 1. A plurality of bit lines, and precharge means for supplying charges to the plurality of bit lines to bring them into a high potential state.
A plurality of transistors and a Y decoder for controlling discharge of charges accumulated in each of the plurality of bit lines, an output decoder for selecting one from the plurality of bit lines, and a plurality of bit lines are provided for each of the plurality of bit lines. A semiconductor memory having potential holding means for holding the potential state of each bit line. 2. In a semiconductor memory having a potential holding means for each of a plurality of bit lines, precharging the plurality of bit lines and holding or discharging the potential state of the bit lines to determine data. All test cycles including a step, a step of selecting one word line, and a step of sequentially selecting a plurality of bit lines on the selected word line one by one and testing the defined data in sequence. A semiconductor memory test method in which all memory cells are tested by repeating the operation for word lines.