JPH05234398A - Test circuit of semiconductor memory device - Google Patents

Abstract

PURPOSE:To obtain a test circuit wherein the interference between data-line pairs can be judged by a line test. CONSTITUTION:Transistors 131, 141,... which constitute a first switch SW1i,... are inserted, at a data-line pair (Di, the inverse of Di),... alternately with the data line Di and the inverse of the data line Di. As a result, pieces of write data can be changed at individual data-line pairs. Thereby, the interference between the individual line pairs can be judged by a line test.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION This invention relates to a semiconductor memory device (D
RAM, SRAM, etc.), and more specifically, to a test circuit thereof.

[0002]

2. Description of the Related Art In recent years, with the increase in storage capacity of semiconductor memory devices, test circuits for shortening test time, such as a multi-bit parallel test, have been made. A conventional test circuit writes the same data in a plurality of bits to be tested at the same time, compares the data at the time of reading, and determines that even if there is any different data, it is defective.

However, the above conventional test circuit is
The same data must be written to multiple bits to be tested, and the written data must be compared when reading. For this reason, there is a drawback in that even if all the data is erroneous, it is determined to be good.

Therefore, the applicant of the present application does not need to compare the written data, and can judge whether each data is correct or not, and even if all the data are erroneous, the semiconductor memory device can be judged as defective. Test circuit of Japanese Patent Application No. 1
-304983.

The test circuit of the semiconductor memory device is shown in FIG.
, The data input signal D and the complementary data input signal bar D, which are input at one of high and low levels opposite to each other, are received based on the data selection signal ST. A first switch SW ₁ for selecting and outputting one of the signals, and an output signal line S for temporarily holding an expected value of either high or low level.
A first switch SW provided between the output signal line S and the fail signal line bar S; _When the second switch SW ₂ turned on or off by the signal from ₁ and the expected value given to the output signal line S and the data input signal D match, the data input signal D and the complementary data input signal bar D The signal for turning off the second switch SW ₂ among the first switch SW ₁
On the other hand, when the expected value and the data input signal D do not match, the second switch SW ₂
Is provided with a data signal selection circuit 2 for outputting a data selection signal ST for causing the first switch SW ₁ to output a signal for turning on. Note that W ₁ , ... Are word lines and M is a memory line.

Further, it is desirable that a plurality of the first and second switches be provided so that data on a plurality of data lines can be determined simultaneously.

When the data input signal D matches the expected value, the first switch SW is activated based on the data selection signal ST.
_{The 1} turns off the second switch SW ₂ . Therefore, the expected value is directly output from the output signal line S.
When the data input signal D is out of phase with the expected value and does not match, the first switch SW ₁ turns on the second switch SW ₂ based on the data selection signal ST, and the fail signal line S and the output signal line S are connected. To conduct. As a result, the level of the output signal line S changes to the level of the fail signal line bar S that constantly holds the level of the opposite phase with respect to the output signal line S. Therefore, after this change, the output signal line S outputs a level opposite in phase to the expected value. In this way, the test is performed with the pair of data input signals D and D from one bit. Therefore, it is not necessary to compare data input signals from a plurality of bits. Further, by providing a plurality of first and second switches, data input signals from a plurality of bits are individually judged, and even if all the data are erroneous, it can be recognized as defective. That is, by arranging the first switch SW ₁ and the second switch SW ₂ as many as the number of the data input terminals D, the pass signal is precharged to the output signal line S at the time of the test, and the data selection signal ST is stored as the data selection signal ST. By giving it to the selection signal terminal, the pass signal is output when all the data are correct, and the fail signal bar S is output when there is even one error in the data, and multiple data can be judged simultaneously. it can.

The above-mentioned conventional test circuit will be described in detail below with reference to the illustrated concrete example.

FIG. 5 shows a test circuit of a semiconductor memory device which is one specific example of the conventional test circuit, and FIG. 6 shows input waveforms of control signals φ ₁ , φ ₂ and φ ₃ inputted to the test circuit. Is shown.

In FIG. 5, 1 is an expected value generation circuit, 2 is a data signal selection circuit, 3 to 8 are inverters, and 9 is a P-type M.
OS transistors, 10 to 14 are N-type MOS transistors, and 15 and 16 are NAND gates. The transistors 12 to 14 are the first switch SW.
_1, the second switch SW ₂ is composed of a transistor 11. Further, the transistors 9 and 10 form a switch SW ₃ that causes the output signal line S to temporarily hold the expected value.

This test circuit confirms whether the expected value output from the expected value generating circuit 1 and the level of the data line D are the same as follows. In addition, here, the expected value is set to a binary value of VCC or GND. Further, the data lines D and the bar D are always input with data in opposite phases. One of the data is obtained by inputting a signal output from one bit terminal to an inverter (not shown), and the other data is obtained directly from the bit terminal.

First, as shown in FIG. 6, the signal φ ₁ is lowered (t ₁ ), and the N-type MO is passed through the data signal selection circuit 2.
The S transistors 13 and 14 are turned off. Next, the signal φ ₂ is lowered (t ₂ ), the transistor 12 is turned on through the inverter 8, and the node connected to the gate of the N-type MOS transistor 11 is discharged. As a result, the N-type MOS transistor 11 is turned off. Further, the signal φ ₃ is lowered (t ₃ ) and the P-type MOS transistor 9
Then, the N-type MOS transistor 10 is turned on, and the expected value is given to the output signal line S.

In order to compare the expected value with the level of the data line D, first, the signals φ ₂ and φ ₃ are raised (t ₄ ) and the transistors 9, 10 and 12 are turned off. Next, φ ₁ is raised (t ₅ ), and the data signal selection circuit 2 is enabled, that is, in a state in which it can operate by receiving an expected value.

When the expected value is VCC, the transistor 13 is turned on through the data signal selection circuit 2 and the output of the data line bar D is input to the gate of the N-type transistor 11. Here, if the expected value and the level of the data line D match, the level of the data line bar D is GND, so the N-type transistor 11 remains off, and the output signal line S is expected to have the expected value. The value is output as is. On the contrary, if the expected value and the level of the data line D do not match, the data line bar D is at VCC, the N-type transistor 11 is turned on, and the output signal line S becomes the level of the fail signal line bar S. The data is rewritten, and as a result, data having a phase opposite to the expected value is output to the output signal line S.

On the other hand, when the expected value is GND, the transistor 14 is turned on through the data signal selection circuit 2 and the level of the data line D is output to the gate of the N-type transistor 11. Here, if the expected value and the output of the data line D match, the output of the data line D is GND, so the N-type transistor 11 remains off, and the output signal line S has the expected value. Is output as is. On the contrary, if the expected value and the level of the data line D do not match, the data line D is at VCC, the N-type transistor 11 is turned on, and the output signal line S is rewritten to the level of the fail signal line bar S. As a result, data having a phase opposite to the expected value is output to the output signal line S.

As described above, if the expected value and the output of the data line match, the transistor 11 is turned off and the expected value is output to the output signal line S. If the expected value and the output of the data line do not match, the transistor 11 is turned on, and as a result, the level of the fail signal line S, that is, the data having a phase opposite to the expected value is output to the output signal line S.

In this circuit, the data selection signal ST from the data signal selection circuit 2, the output signal line S, and the fail signal line bar S can be shared by a plurality of data line pairs.
For example, a semiconductor memory device (DRAM, SRAM, R
When it is used for OM etc., the data output to the plurality of data lines D and the bar D can be determined at one time, so that the device test time can be shortened. Further, even if all the bit data are incorrect, it can be detected that they are incorrect. Further, it is possible to avoid using a complicated circuit configuration such as EXOR.

[0018]

In the conventional test circuit described above, the data can be changed for each word line, but the data cannot be changed for each data line pair. Therefore, it was not possible to determine the interference between the data line pairs by the line test.

The present invention has been made in view of the above points, and provides a test circuit capable of changing data for each data line pair and thereby determining interference between data line pairs by a line test. It is a thing.

[0020]

As shown in FIG. 1, a test circuit for a semiconductor memory device according to the present invention is provided for each data line pair (D _i , bar D _i ) and has a data selection signal ST.
In response to the data selection signal ST, a plurality of data input signals and complementary data input signals, which are input at one of high and low levels opposite to each other, are selected and output. First switch SW ₁₁ , SW ₁₂ , S
W ₁₃ , ..., And an output signal line S which is temporarily held by being given an expected value of one of high and low levels, and an output signal line S which is provided with an opposite phase level and is constantly held. The fail signal line bar S is provided between the output signal line S and the fail signal line bar S, and the first switch S
A plurality of second switches SW ₂₁ , SW ₂₂ , SW that are turned on or off by signals from W ₁₁ , SW ₁₂ , SW ₁₃ , ...
₂₃ , ... And the expected value given to the output signal line S ((2
When the (n-1) -th (or 2n-th, where n is a natural number) data input signal is matched, the second switch (SW ₂₁ ,
The signal for turning off SW ₂₂ , ..., Is the (2n−1) th (or 2nth) first switch SW ₁₁ , SW.
_13, whereas to output a ... (or SW _12, SW _14, ...), the expected value and the (2n-1) -th (or 2n-th) when the data input signal of the mismatch, among the two signals, The (2n-1) th (or 2nth) first switch SW ₁₁ , SW ₁₃ , ... (Or SW ₁₂ ) is used as a signal for turning on the second switch (SW ₂₁ , SW ₂₂ , ...). , SW ₁₄ , ...) And when the expected value and the 2n-th (or (2n-1) -th) data input signal do not match, the second switch of both signals is turned off. 2n-th signal (or (2n-
1) The first switch SW ₁₂ , SW ₁₄ , ...
(Or SW ₁₁ , SW ₁₃ , ...) And while the expected value and the 2n-th (or (2n-1) -th) data input signal match, the second of the two signals is output. The signal for turning on the switch is the 2n-th (or (2n-1) -th) first switch SW.
₁₂ , SW ₁₄ , ... (Or SW ₁₁ , SW ₁₃ , ...) And a data signal selection circuit 2 for outputting a data selection signal ST.

[0021]

[Action] memory cell M ₁₁ in data 1, data 0 to the memory cell M _12, the data 1 into the memory cell M _13, the memory cell M ₁₄
The data is written by changing the data for each data line pair, such as data 0. The expected value is 1. Then, the line test is executed by the same method as the conventional method. At this time, if the data writing is performed correctly, 0 level is applied to the gates of all the second switches SW _2i ,
The output signal line S holds 1 level. On the other hand, when the data in one of the memory cells is inverted due to the interference between the pair of data lines, one level is applied to the gate of the second switch corresponding to the memory cell, and the switch is turned on. Thus, the output signal line S changes to 0 level.

[0022]

The present invention will be described in detail below with reference to the embodiments shown in the drawings.

FIG. 1 shows a test circuit of a semiconductor memory device according to an embodiment of the present invention, and FIG. 2 shows input waveforms of control signals φ ₁ , φ ₂ and φ ₃ input to the test circuit. There is.

In FIG. 1, 1 is an expected value generation circuit, 2 is a data signal selection circuit, 3 to 8 are inverters, and 9 is a P-type M.
OS transistors, 10, 11 ₁ , 11 ₂ , ..., 12, 1
3 ₁ , 13 ₂ , ..., 14 ₁ , 14 ₂ , ... Are N-type MOS transistors, 15 and 16 are NAND gates, and transistors 12, 13 _i , 14 _i (i = 1, 2,
,) Constitutes the first switch SW _1i , and the transistor 11 _i constitutes the second switch SW _2i . Further, the transistors 9 and 10 form a switch SW ₃ for temporarily holding the expected value on the output signal line S. In addition, W ₁ ,
W ₂ , ... Are word lines, D _i , bar D _i are each data line pair, M
_ij (i = 1, 2, ..., j = 1, 2, ...) Is each memory cell.

The difference from the conventional test circuit shown in FIG. 5 lies in the way of providing the transistors 13 _i and 14 _i , and the other structures are the same. That is, in the conventional test circuit, all the transistors 13 are the data line bar D.
All of the transistors 14 inserted in the _i side are data lines D _i
On the other hand, in the test circuit of the present invention, all the transistors are
, And the data lines D _i , the data line bars D _i , ... Are alternately inserted.

Next, the operation will be described.

The case of testing the memory cells M ₁₁ , M ₁₂ , ... Connected to the word line W ₁ will be taken as an example. First, the data 1 into the memory cell M _11, the data 0 to the memory cell M _12, the data 1 into the memory cell M _13, by changing the data for each of the data line pair and so data 0 in the memory cell M ₁₄ performs writing. The expected value is 1.

First, as shown in FIG. 2, the signal φ _{1 is made} to fall (t ₁ ), and the N type M signal is passed through the data signal selection circuit 2.
The OS transistors 13 _i and 14 _i are turned off. next,
The signal φ ₂ is lowered (t ₂ ), the transistor 12 is turned on through the inverter 8, and the N-type MOS transistor 11 is turned on.
Discharge the node connected to the gate of _i . As a result, the N-type MOS transistor 11i is turned off.
Further, the signal φ ₃ is lowered (t ₃ ), the P-type MOS transistor 9 and the N-type MOS transistor 10 are turned on, and the expected value 1 is given to the output signal line S.

In order to compare the expected value with the level of the data line D _i , the signals φ ₂ and φ ₃ are first raised (t ₄ ),
The transistors 9, 10 and 12 are turned off. Then φ ₁
Is started (t ₅ ), and the data signal selection circuit 2 is enabled, that is, brought into a state capable of receiving an expected value and operating. Since the expected value is 1, the data signal selection circuit 2 outputs the data selection signal ST which turns on the transistor 13 _i and turns off the transistor 14 _i .

If the data is written correctly,
The level of the data line bar D _2n-1 (n = 1, 2, ...) Is 0,
Further, since the level of the data line D _2n also becomes 0, 0 level is applied to the gates of all the second switches SW _2i ,
Since the second switches SW _2i are all turned off, the output signal line S holds the expected value level 1.

On the other hand, it is assumed that the data in one of the memory cells is inverted due to the interference between the pair of data lines. For example, if the data in the memory cell M ₁₃ is inverted to 0, the level of the data line bar D ₃ becomes 1, so that the second switch SW ₂₃ is turned on and the level of the output signal line S changes to 0 level. To do. The same applies when data inversion occurs in another memory cell.

Therefore, the interference between the data line pairs can be determined by the line test.

In the case of the test of the memory cell connected to the word line W ₂ , the write data is set to 1, 0,
When the values are 1, 0, ..., The expected value is 0. Alternatively, if the expected values are the same, write data to 0
(M ₂₁ ), 1 (M ₂₂ ), 0 (M ₂₃ ), 1 (M ₂₄ ), ...

The N-type MOS transistors 11 _i , 1
P-type MOS or CMOS may be used instead of 2, 13 _i and 14 _i , and the first switch SW _1i may be replaced with a logic circuit as shown in FIG. 3, for example.

[0035]

As described in detail above, according to the present invention, the data can be changed for each data line pair, and thus the interference between the data line pairs can be determined by the line test, which is a very useful test. A circuit can be provided.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a test circuit according to an embodiment of the present invention.

FIG. 2 is a signal waveform diagram of a control signal for operating the test circuit.

FIG. 3 is a diagram showing an example in which a part of the test circuit is modified.

FIG. 4 is a block diagram showing a conventional test circuit.

FIG. 5 is a circuit diagram showing a conventional test circuit.

FIG. 6 is a signal waveform diagram of a control signal for operating the conventional test circuit.

[Explanation of symbols]

1 expected value generation circuit 2 data signal selection circuit SW _1i first switch SW _2i second switch D _i , bar D _i data line pair S output signal line bar S fail signal line ST data selection signal

Claims (1)

[Claims] 1. A data input signal, which is provided for each data line pair, receives a data selection signal, and is input based on the data selection signal at either a high or low level opposite to each other and a complementary data input. A plurality of first switches for selecting and outputting one of the signals, an output signal line for temporarily holding an expected value of one of high and low levels, and the output signal line A plurality of second signal lines provided between the output signal line and the fail signal line, which are provided with a level of the opposite phase and are constantly held, and which are turned on or off by a signal from the first switch. And the expected value given to the output signal line and the (2n-1) th (or 2nth, where n is a natural number) data input signal match, the data input signal and the complementary data input signal Of The signal of the direction which turns off the serial second switch (2n-1) -th (or 2n-th) while allowing output to the first switch, the expected value and the (2n-1)
When the second (or 2nth) data input signal does not match, the one of the two signals that turns on the second switch is the (2n-1) th (or 2nth) signal.
Output to the first switch, and when the expected value and the 2nth (or (2n-1) th) data input signal do not match, the second switch of both signals is turned off. 2n-th signal (or (2n
-1) th) the above first switch, while
Above expected value and above 2nth (or (2n-1) th)
When the data input signal of is matched, of the above two signals,
And a data signal selection circuit for outputting a data selection signal for outputting the signal for turning on the second switch to the 2n-th (or (2n-1) -th) first switch. And a test circuit of a semiconductor memory device.